A Sub-200 fs RMS JBased PLL in 28

CommBurak Çatlı, Ali Nazemi, Tamer A

Mahmoud Reza AhmBroadcom Corporation, 5300 Calif

Abstract An 8.0 GHz to 12.2 GHz PLL wmultiplier-based active loop filter is designed inCMOS process. A passive loop filter-based versalso implemented for comparison. While thcomparable to that of digital PLLs, the PLL pgood as that of an analog PLL that employs a pThe capacitor multiplier-based active loop filterperformance of 198 fs (rms), while its passivecounterpart shows a jitter performance of 195 foccupies 0.093 mm2 and consumes 15.5 mA at 1.

I. INTRODUCTION

The ever-increasing demand for higherexpanded the scope of wireline applicationcellphones to cloud data centers. While therates have made wireline applications msophisticated to meet the tougher speccustomers perspective, the expectations havsame: compact form and low-power operation With its considerable area and power cPLL is one of the key building blocks that prole in the performance of wireline transceivthese factors, researchers have proposed usinthat has a smaller PLL loop filter area tocompact. Although some reported exampldemonstrated a jitter performance of 190 fsMHz) [1], the operation frequencies remaineto 6 GHz or lower [2], and designs with hiaround 10 GHz suffered from high jitter [3other examples report the current limits of twith a jitter performance as low as 295 fs in aor 345 fs with high power consumption [5]. In this paper, we investigate a technique tPLLs still competitive in terms of area, whiexcellent jitter performance. To reduce the athe loop filter was targeted, and the area integrator capacitance, Cint, (Fig.1a) was reducbased on a capacitor multiplier technique. Tevaluate the performance of the C-multiplier its passive counterpart, two identical traimplemented with two similar PLLs that can from each other only by the filter type that thefollowing sections, we explain the concemultiplier and show how it can be applied addressing practical issues such as noise, swwe present the experimental results of the imtaking its passive counterpart as a benchmark

1

itter Capacitor Multiplier Lnm CMOS for High-Spee

munication Applications li, Siavash Fallahi, Yang Liu, Jaehyup Kim, Moham

madi, Hassan Maarefi, Afshin Momtaz, Namik Kocafornia Avenue, Irvine, CA 92617, USA, e-mail: burak@b

with a capacitor n a 28 nm digital sion of the PLL is he PLL area is performance is as passive loop filter. r PLL has a jitter

e loop filter-based fs (rms). The PLL .0V.

r data rates has ns, ranging from e increasing data more and more cifications, from ve remained the n. consumption, the play an important vers. Because of ng a digital PLL o make it more le designs have s (1 kHz to 10 ed around 5 GHz igher frequencies 3]. Nevertheless, the digital PLLs, a SOI CMOS [4]

that keeps analog le demonstrating area of the PLL, covered by the

ced significantly, To compare and based PLL with

ansceivers were be distinguished

ey employ. In the ept of capacitor

to a loop filter, wing, etc. Finally, mplemented PLL, k. To the best of

our knowledge, this study is the firC-multiplier based loop filters implementation level with a passive

II. THE LOOP F A. Capacitor Multiplier

The capacitor multiplier conceporiginally proposed by Larsson [6simple series RC (RX and C) filter ccapacitor multiplier. A unity gain band an auxiliary resistor RY caimpedance of the filter Z. With the the voltage drop on RX is copied current is drawn proportional to the(Fig. 1c). This additional currentoriginal impedance of the loop fi(Fig. 1d). The benefit of the technidecomposed to its equivalent R andn+1 times less series resistance capacitance, which is the key featloop filter implementation (Fig. 1e)

B. The Loop Filter Noise Analysis

The equivalent noise circuit for tFig. 2. For the completeness of the ais also shown. In Fig. 2, Vx and Vy resistors RX and RY, and Vo showsthe buffer. The noise contribution noise at node P can be given as in th

Fig. 1. Basic concept of the ca

Loop Filter-ed Serial

mmed Abdul−Latif, man roadcom.com

rst comprehensive work on at both the theory and

e counterpart comparison.

FILTER

pt used in this work was 6]. Fig. 1b shows how a can be modified to obtain a buffer inserted between RX an redefine the effective

introduction of the buffer, on RY, and an additional

e resistance ratio n=Rx/Ry t effectively modifies the ilter by n+1, Zeff=Z/(n+1) que is seen better if Zeff is

d C configuration that gives and n+1 times higher

ture that enables compact .

the loop filter is shown in analysis, shunt capacitor CP shows thermal noise of the

s the input-referred noise of of each component to the

he following:

apacitor multiplier.

978-1-4673-6146-0/13/$31.00 ©2013 IEEE

, 1, 1, 1

where vp,x, vp,y, and vp,o are the noise voltages the buffer. Thus, the total noise at node P canin the following:

The calculated loop filter noise is used insimulations. Table I shows a jitter estimationPLLs with C-multiplier based and passive loexample, PLL loop parameters (charge-pumgain, etc.) are kept constant while the loop ba

Table I. Jitter estimation for the PLLs with C-multiplieloop filter.

PLL with Passive LF

Ceff [pF]

Reff [kΩ]

BW [MHz]

LF J-rms

PLL J-rms

300 1.8 2.8 67 fs 188 fs 300 2.4 4 67 fs 185 fs 300 3.2 5.6 68 fs 187 fs

Fig. 3. Transistor level schematic of the rail-to-r

Fig. 2. Equivalent noise circuit for the loop

1

Rx Ry

C

x 2 2

y

2o

C

2PP

2

1

2

3

due to Rx, Ry and n be expressed as

4

n jitter estimation n example for the oop filters. In this mp current, VCO andwidth is varied

by changing only the effective sefilters. For each loop filter configuracalculated and added to estimation jitter generated by the filters and tconfiguration. Although the total Rof many jitter components, we canincreasing the effective series recontribution of the loop filter to thRMS jitters of both PLLs becomshown experimentally in section IV C. Buffer Design

A Miller opamp based unity gaibuffer. Special attention is paid to One should note that the C-multiplproperly in the control voltage rangthe charge pump circuit. Practicallyto-rail buffer in this applicationdifferential input stage is utilizedconstant-gm circuit is avoided to kopamp is designed to achieve a GMHz, for the worst case) than the tto 10 MHz). This margin ensures thas a unity gain amplifier in the PLmultiplier can continue to emulate t

D. Circuit Implementation Fig. 4 shows the schematic of tdifferential charge pump. Because the VCO are differential, two buffein addition to single-ended CSE portion of the capacitor C is implemAs shown in Fig. 4 both Rx programmable as different applicabandwidth, peaking, and noise requ

Fig. 4. The loop filter implementation dripump.

er based and passive

PLL with C-Multiplier LF

LFJ-rms

PLLJ-rms

101 fs 203 fs 90 fs 194 fs 82 fs 192 fs

rail opamp.

p filter.

Cpto VCO

eries resistance of the loop ation, the loop filter noise is process. Table I shows the

the total RMS jitter in each RMS jitter is a combination n still see from Table I that sistance reduces the noise he point at which the total e equal, as it will also be

V.

in stage is designed as the minimize the opamp noise. ier based filter should work ge defined by the VCO and y, this range requires a rail-

n. Thus, a complementary d as shown in Fig. 3. A keep the area compact. The

GBW sufficiently larger (80 targeted PLL bandwidth (up hat the opamp can still work LL bandwidth range, and c-the integrator capacitor.

the loop filter driven by a both the charge pump and

er stages are employed, and capacitors, a considerable

mented differentially (Cdiff). and Ry are implemented tions demand various PLL irements. To use the area

ven by a differential charge

efficiently, the programmable resistor is varremoving unit resistors in series fashion. Taparameter set that can be used for the reconloop filter. For each row in Table II, n=4, anRX, whereas C is always 300 pF ([n+1]×[2×Cd

n coefficients, however, can be realized by selindependently. For example, if one picks thvalues in Table II, n would be equal to reconfigure the filter for the (1.75 kΩ) and C (480 pF) values.

Fig. 5 shows the comparison of impedancof a C-multiplier based loop filter with a trangain buffer and its passive counterpart for th

Fig. 6. VCO control voltage in locking phaC-multiplier based and passive loop filt

Fig. 5. Comparison of the loop filter characteristicsb) phase.

Table II. Loop filter parameter set for reconfiguration,RX

[kΩ]

RY

[kΩ] Reff

[kΩ] Ceff [pF]

6 1.5 1.2 300 7 1.75 1.4 300 8 2 1.6 300 9 2.25 1.8 300 10 2.5 2 300 12 3 2.4 300 14 3.5 2.8 300 16 4 3.2 300 18 4.5 3.6 300

3

ried by adding or able II shows the nfiguration of the nd Reff scales with diff+CSE]). Various lecting RX and RY

he shaded resistor 7, which would

desired Reff

ce characteristics nsistor level unity he parameter set

given in the 3rd row of Table II. Thmatches the expected characteristicand beyond.

The large signal characteristic also be compared, especially for ththe loop filter experiences large tranespecially important to guarantee Fig. 6 shows the VCO control voltaphase for both the C-multiplier basAlthough the control voltage transeach other, they still track together.

III. PLL

The PLL consists of a phase acharge pump, a loop filter, a programmable integer divider, a oscillator, and 10 GHz CMOS clCML logic is used in the entire PLthe area. The VCO core is directlyD2C (CML-to-CMOS converter)

ase for ter.

s: a) amplitude,

Fig. 8. Die of the PLL with TX and R

Fig. 9. Measured RMS jitter of the PL

Pump curre

, n=4 for each row.BW

[MHz] 1.4 1.6 1.8 2

2.2 2.8 3.5 4

4.5

Fig. 7. Block diagram

he C-multiplier based filter cs over the PLL bandwidth

of the loop filters should he locking phase in which nsients. This verification is

proper locking behavior. age deviation in the locking sed and passive loop filter. sients slightly deviate from

and frequency detector, a 10 GHz LC VCO, a

10 GHz injection locked lock buffers (Fig. 7). No L to reduce the power and y connected to the CMOS ) block for a compact

RX blocks of the transceiver.

LL for various RX and Charge-nts.

m of the PLL.

implementation. D2C drives both the integer-and the ILO that generates the full-rate quTapered CMOS buffer stages that are employof the ILO draw 8 mA from a 1V supply at four RX-TX lanes.

IV. MEASUREMENT RESULTThe presented PLL was integrated in a Se

chip in 28 nm CMOS. The clock performancthrough the output of the designed full-rate presented PLL chip operates from 8 GHzFig. 8 shows the die micrograph of the PLL sconsumes 15.5 mW from a 1V supply and oc0.093 mm2.

To see the jitter performance consistencyloop bandwidth values, the PLL was measuredfor several charge pump currents and all effvalues shown in Table II. Fig. 9 shows thrmeasurements for different effective resistthese measurements, charge pump current wasmA to 1.5 mA for each measurement sbandwidth range from 1.3 MHz to 6.5 MHzThe peaking changed from 0.2 dB to 1 dpeaking was observed for lower loop bandRMS jitter changed between 198 fs and 23stable jitter performance over a wide BW rangcorresponding spectrum measurements at 198 fs jitter performance. The measured r

Fig. 10. Spectrum measurement at 10. 2 GHz at the owith a constant 1-0 pattern.

Table III. Performance sum This Work

Jitter-RMS (fs) 198/207 Jitter Integration Range (Hz) 1k–100M

Output Carrier Frequency (GHz) 10.2/12.0 Tuning Range (GHz) 8–12.2

Reference (MHz) 156.25 Oscillator LC VCO

Core Power Dissipation (mW) 15.5/16.5 Core Area (mm2) 0.093

PLL Type Analog Technology (nm) 28-CMOS

1Includes 100 fs trigger jitter of instrument. 2Range is slightly highe

4

-N divider block uadrature clock. yed at the output 10 GHz driving

TS erDes transceiver ce was measured transmitter. The

z to 12.2 GHz. section. The PLL cupies an area of

y under different d around 10 GHz fective resistance ree sets of jitter tance values. In s varied from 0.1 set, and a loop z was measured.

dB, while higher dwidths. Overall, 30 fs, showing a ge. Fig. 10 shows 10.2 GHz with eference spur is

-61 dBc. The PLL performance wasThe jitter increases slightly at 12 Gattributed to the relatively higher pthis frequency. The measured referthe carrier frequency. The PLL empsubblocks but the passive loop filterfs RMS jitter performance was version, which confirms the claim in

Table III compares the performstate-of-the-art examples from the As can be seen, the designed PLL othat of a digital PLL [5], consumebest jitter performance.

V. CONCLUS

A compact PLL with a capacitor muimplemented in a wireline transceivPLL exceeds or is comparable todigital PLLs or PLLs employed Moreover, we present a comprehemultiplier based loop filters inexperimental results, and providimplementation and a comparison all-passive counterpart.

REFERENC[1] C. W. Yao, et al., “A low spur802.11a/b/g/n/ac with 0.19 ps rms jitter,” iDig., Jun. 2011, pp. 110–111. [2] D. Park, et al., "A 14.2 mW 2.55-to-3 GHInjection and 800 MHz Delta-Sigma ModulJ. Solid-State Circuits, vol.47, no.12, pp.298 [3] S. Yang and W. Chen, “A 7.1mWSynthesizer with Dynamically ReconfiguraCMOS,” ISSCC Dig. Tech.Papers, pp. 90-91[4] A. Goel, et al., “A compact 6 GHz to 1dual-LC tank DCO,” inVLSI Symp. Dig. Tec[5] A. Rylyakov, et al., “Bang-Bang Digital 200fs Integrated Jitter for High-Speed SeriISSCC Dig.Tech. Papers, pp. 94-95, 2009. [6] P. Larsson, “An offset-cancelled CMOhalf-rate linear phase detector for 2.5 Gbp/s Int. Solid-State Circuits Conf. Dig. Tech. Pap[7] N. Kocaman, et al., "11.3Gb/s CMOS Sboth RZ and NRZ applications," ISSCC Di2011 [8] J. Savoj, et al.,"Design of high-speed wcommunications in 28nm CMOS," IEEConference (CICC), 2012 IEEE , pp.1,4, 9-1[9] G. Ono, et al., “A 10:4 MUX and 4:10Gigabit Ethernet link,” IEEE J. Solid-State C3112, Dec. 2011.

output of the TX

mmary of the PLL and state-of-the-art example PLLs operating around Yang [3] Goel [4] Rylyakov [5] Kocaman [7]

9001 295 345 2503 N/A 7M–5.82G 1k–10G 50k–80M 9.92 11.65 11 11.3

9.75–10.17 7.89–11.642 8.1–11.8 8.5–11.3 40 N/A 275 706.25

LC DCO LC DCO LC DCO LC VCO 7.1 20.8 31 N/A

0.352 0.111 0.088 N/A Digital Digital Digital Analog

90-CMOS 45-SOI 65-CMOS 65-CMOS

er for Push Mode. 3 Jitter measured at TX output.

s also measured at 12 GHz. GHz to 207 fs, which can be phase noise of the VCO at rence spur is 58 dB below ploys exactly the same PLL r was also measured. A 195 obtained for the passive

n Section II-B. mance of the PLL with the

literature around 10 GHz. occupies an area as small as es less power, and has the

IONS

ultiplier-based loop filter is ver. The performance of the o that of recently reported

in wireline transceivers. ensive picture of capacitor n PLLs, from theory to de a description of its of its performance with its

CES r fractional-N digital PLL for in Symp. VLSI Circuits (VLSIC)

Hz Cascaded PLL With Reference lator in 0.13 um CMOS," in IEEE 9-2998, Dec. 2012

W 10GHz All-Digital Frequency able Digital Loop Filter in 90nm 1, Feb. 2009. 12 GHz digital PLL with coupled ch. Papers, Jun. 2010, pp.141–142 PLLs at 11 and 20GHz with sub-

al Communication Applications,”

OS clock-recovery/demux with a optical communication,” in IEEE

pers, Feb. 2001, pp.74–75. SONET-compliant transceiver for ig. Tech.Papers, pp.142-144, Feb.

wireline transceivers for backplane EE Custom Integrated Circuits 2 Sept. 2012 0 DEMUX gearbox LSI for 100-Circuits, vol. 46, no. 12, pp. 3101–

10 GHz. Savoj [8] Ono [9]

3993 4293

N/A 10k–100M13.1 12.89

8–13.1 N/AN/A 625

LC VCO LC VCON/A N/AN/A N/A

Analog Analog28-CMOS 65-CMOS