Design and Analysis of an Energy Recycling Electronic Load System

Qian Guo, Hao Ma, Jing Li and Longyu Chen

College of Electrical Engineering, Zhejiang University Hangzhou, 310027 China

E-mail: ichliebe2032@ zju.edu.cn, mahao@cee.zju.edu.cn

Abstract— An energy recycling electronic load system with multiple input channels for DC power supply burn-in test is proposed. It has high efficiency and good performance. The theoretical analysis and the control strategy are presented in this paper. The proposed system employs Input-Parallel and Output-Series Interleaved ZVS Flyback-Forward (IPOS-IZFF) converters with active-clamp circuits as the front-end stage, which can step up the low voltage of DUTs (Device Under Testing) to a high dc-bus voltage efficiently. A 3-phase 4-wire (3P4W) grid-connected inverter with neutral line current control is used as the back-end stage, which can feed the energy back to the utility grid. An improved repetitive controller is applied to achieve high quality of feedback power. A 15-kW prototype has been built and tested to verify the theoretical analysis.

I. INTRODUCTION Power supply products usually take 24 to 72 hours of burn-

in tests in the manufactory to verify their quality, reliability and performance. Traditionally, the procedure employs resistor bank as the loads, which has the disadvantages of energy consuming, heat dissipation and non-continuous adjustment. A perspective solution capable of avoiding power waste is the energy recycling electronic load. It feeds the output power of the burning-in power supplies to the utility grid, and the only energy consumed is the power loss of the power supplies and the electronic load.

The energy recycling electronic load has smaller volume, lighter weight and higher testing precision. The approaches in this field are developing rapidly. In recent years, researches for the electronic load mainly focus on AC power sources such as UPS, AC motor drivers. The system topology often bases on two back to back bidirectional PWM voltage source rectifiers [1-4]. Control strategies are developed to compensate the harmonic and reactive components of input currents in the AC sources.

With the wide utilization of DC power supplies, the demand for the energy recycling electronic load for DC power supply burn-in tests is becoming greater and greater. For DC power sources, the problem is to step up the low output voltage of DUTs efficiently to a dc bus, which should be high enough for the back-end grid-connected inverter [5-8]. One

way is that several DUTs connect in a series string having the same current instructions [5-6]. The DUTs cannot be tested individually and the deficient DUT may break down the whole system. Also it is only appropriate for isolated-output DUTs. Another way is to use a front-end boost converter to gain voltage [6-8]. The high peak current in the switch and diode increases the conduction loss and degrades the efficiency.

In this paper, an energy recycling electronic load system with multiple input channels for DC power supplies is proposed, as shown in Fig.1. It has high efficiency and good performance. The front-end Input-Parallel and Output-Series Interleaved ZVS Flyback-Forward (IPOS-IZFF) converters are connected respectively to the DUTs to imitate different loads. They boost the low output voltage of DUTs efficiently. A central 3-phase 4-wire (3P4W) grid-connected inverter feeds the energy back into the utility grid. An improved repetitive controller, which has faster dynamic response than the conventional repetitive controller, is designed to improve the power quality. The system topology, the theoretical analysis, and the control strategy are presented. An SCADA (Supervisory Control And Data Acquisition) scheme with tree topology is implemented to control the whole system. A 15-kW prototype is built and the experimental results verify the effectiveness of the system.

IPOS-IZFFDC/DC

Converter

dc bus 3P4W

DC/ACConverter

DSP

DUT

DUT

DUT

……

……

Monitor

Stage 1 Stage 2

CHANNEL 1

CHANNEL 2 DSP

CHANNEL n DSP

DSP

CAN FieldBus

3Phase 4Wire Utility Grid

Central Controller

Fig.1 Proposed energy recycling electronic load system topology

978-1-4673-4355-8/13/$31.00 ©2013 IEEE 1590

II. DESIGN CONSIDERATIONS FOR IPOS-IZFF CONVERTER The IPOS-IZFF Converter is designed for the load

imitation stage (Stage 1), which interfaces the output of the DUT. It meets the following demands: low input current ripple, high voltage gain, high efficiency, isolation scheme and mid power application. The operational principle of a single unit is presented in literature [9], so analysis below focuses on its design considerations.

As shown in Fig.2, iS are the main switches; CiS are the

active clamp switches; CiC are the clamp capacitors; SiC are the parallel capacitors (i=1,2,3,4). The coupling of the inductors is marked by open circles and dash lines. The equivalent circuit of each coupled inductor consists of a magnetizing inductor, an ideal transformer with corresponding turns ratio and a leakage inductor in series with the magnetizing inductor. In a single unit, when one main switch is on and the other is off, the corresponding inductors work in the forward mode and flyback mode respectively and both of them transfer energy to the secondary-side. Though the magnetic components are fully utilized, the design should base on a continuous flyback transformer with power storage and larger cores are required for higher power volume. So the Input-Parallel and Output-Series structure is suitable, especially in large input current and high step-up situations.

All switches of the circuit operate in zero-voltage-switching (ZVS) mode during both turn on and turn off periods. The Output-Series topology lowers the voltage stress of the secondary-side diodes, so diodes with better reverse recovery performance can be adopted. The current-fed and input parallel characters give a low input current ripple. The coupled inductors not only make the input and the output isolated, but also contribute to a high voltage gain:

41

out

in

V NMV D

⋅= =−

(1)

where N is the turns ratio and D is the duty cycle.

If D<0.5, there is a subinterval when the main switches in the single IZFF are off. The power stored in the coupled inductors flows to the resonant capacitors other than transfer to the output, which leads to unnecessary power circulation. In addition, a higher D means higher voltage stress of main switches and more serious diodes reverse-recovery problems. So a preferable D is slightly larger than 0.5.

The ZVS-on of main switches is realized by the resonance of the leakage inductor kL and the resonant capacitor. kL should be large enough to extract all the energy stored in the corresponding parallel capacitor. The restrictions for a proper resonant time constant are given by:

2 2_

_

min max

/ 4(1 )

2

2(1 ) 3 2(1 )

C

C

k L peak Si C

C outL peak

k

k C

L I C V

V VI D T

NL

D T L C D T

⎧ ≥⎪

−⎪ = −⎨⎪⎪ − ≤ π ≤ −⎩

(2)

where T is the switching period; _L peakI is the resonant

current peak; CCV is the voltage of the clamp capacitor.

With the interleaved structure, the input current ripple is highly reduced, which is:

(3 4 )(2 1) , (0.5 0.75)2(1 )

intotal

M

VD DI T DD L

− −Δ = ≤ ≤−

(3)

III. CONTROL STRATEGY

A. The Improved Repetitive Controller A 3-phase 4-wire grid-connected inverter is adopted as the

second stage to feed back the energy to the utility grid. It is a proper choice for high power application and the neutral line is for safety concerns in the manufactory.

Vin

+

-

S1

S2

Sc1

Sc2

Cs1

Cs2

Cc1

Cc2

L1a

L2a

L1b

L2b

C1s

D1s

D1o

Co1

S3

S4

Sc4

Cs3

Cs4

Cc3

Cc4

L3a

L4a

L3b

L4b

C2s

D2s

D2oSc3

Co2

-

+

Vout

iin iL1

iL2

iL3

iL4

1:N

1:N

1:N

1:N

Fig.2 Input-parallel and Output-series converter of Interleaved ZVS Flyback-Forward (IPOS-IZFF) converter

Fig.3 3-phase 4-wire grid-connected inverter

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Fig.3 shows the main circuit of the 3P4W grid-connected inverter, including six IGBT switches, three L filters and the equivalent series resistors r . ae , be , ce represent phase voltages of the grid. Two capacitors are connected in series in the dc bus. The neutral point of the grid is connected to the mid-point of split-link capacitors. The grid-connected inverter has two main functions: (1) stabilizing the system by establishing the dc-bus voltage to a specific value and control power flow; (2) inverting the current into the sinusoidal waveform in phase with the utility grid to feed the energy back.

From Fig.3, we can derive the mathematical model of the 3P4W inverter in the stationary frame using Clarke transformation to have decoupled currents in αβγ axes:

2

23

2 2

2 2 3

3

dc

dc

dc

dc in

UdL i ri S edt

UdL i ri S edt

UdL i ri S Udt

idC u i S S S i idt

i

dC u idt

⎧ + = −⎪⎪⎪ + = −⎪⎪⎪ + = − Δ⎪⎨⎪ ⎡ ⎤⎪ ⎢ ⎥⎡ ⎤= − +⎪ ⎣ ⎦ ⎢ ⎥⎪ ⎢ ⎥⎣ ⎦⎪⎪

Δ =⎪⎩

α α α α

β β β β

γ γ γ

α

α β γ β γ

γ

γ

(4)

where i , S , dcU are inductor current, average switching function, dc bus voltage, respectively. The subscripts α, β and γ denote the variables in the three axes of the stationary frame.

2 1C CU U UΔ = − is the voltage difference between the dc bus capacitors. From (4), we obtain the control block diagram shown in Fig.4 with two outer voltage loops and three inner current loops.

Two voltage loops are both based on Proportional-Integral (PI) controller with zero error tracking. The dc voltage loop keeps the dc bus voltage dcU to a constant value by

controlling the power flow directions. If dc dc refU U< , the inverter works as a rectifier to draw energy from the grid and charge the dc bus. If dcU tends to be bigger than dc refU , the inverter works in its normal mode to inject the energy to the grid. In both modes, the dc bus voltage is maintained. The reference of neutral current is set to the output of the voltage balance loop instead of setting to zero, so the voltage unbalance of dc bus capacitors is eliminated.

There are abundant low-order harmonics in the utility grid, which introduce periodic disturbance to the grid current. Each of the current loops employs an improved Repetitive Controller (RC). According to the internal model principle, repetitive controller has the ability of zero error tracking of

periodic reference signals [10-12]. However, it has bad dynamics due to a fundamental period delay. So a Proportional (P) controller is combined for fast response.

Three inner current loops employ repetitive controller in parallel with P controller, which is shown in Fig.5. The closed loop transfer function can be obtained:

( ) ( ( ))( ) 1( ) 1 ( ( )) ( ) ( )

1

N

p Nk

Nref

p N

zP z k S zi z Qz

zi z k S z P z H zQz

−

−

−

−

⋅ + ⋅−=

+ + ⋅ ⋅−

(5)

The characteristic equation is:

( ) ( )(1 ( ) ( ))[1 ( ( ))]1 ( ) ( )

Np

p

P z H zk P z H z z Q S zk P z H z

− ⋅Δ = + ⋅ ⋅ − − ⋅+ ⋅ ⋅

(6)

The characteristic equation can be divided into two parts: (1) The inverter with a P controller; (2) The P controller revised inverter with a repetitive controller. Both parts contribute to the sufficient stability condition. So the design procedure begins with the P controller using root locus method, and then comes to the repetitive controller. As the inverter with L filter is a first-order system, a compensator with a second-order LPF and a time leading unit is enough. The designed parameters are given in TABLE.I

1Ls r+

1Ls r+

1Ls r+

Fig.4 Control block diagram of the 3P4W grid-connected inverter

refiNz−

NQz −

pk

ei ki( )S z ( )P z

( )H z

Fig.5 Control block diagram of the improved repetitive controller

0 2 50ω π= ⋅

0ω 02ω 03ω 04ω 05ω ⋅⋅⋅

Fig.6 Magnitude curve of the open loop transfer function with the designed current controller

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TABLE.I Parameters of the current controller Proportional gain pk 2

Filter or constant ( )Q z 0.95

Inverter plant ( )P z 0.1468

0.7042z −

Feedback function ( )H z 46.5

Compensator ( )S z

Second-order LPF 2

0.04245 0.036591.562 0.6413

zz z

+− +

Time leading unit 9z Samples in a fundamental period N 200 Sampling frequency 10kHz

The magnitude curve of the open loop transfer function with the designed current controller is plotted in Fig.6. The high gain is achieved with fundamental and its low-order integer frequencies. The zero error tracking and low-order harmonic suppress of the grid current is guaranteed.

According to the small gain theorem [13], the sufficient condition for system stability is:

( ) ( )| ( ) | 11 ( ) ( )

j T j Tj T j T

j T j Tp

P e H eQ e S ek P e H e

ω ωω ω

ω ω

⋅− ⋅ <+ ⋅ ⋅

(7)

To explain (7) geometrically, a unity circle centered at Q is pictured on the Nyquist plane. The end of the vector

( ) ( ) ( )1 ( ) ( )

j T j Tj T j T

j T j Tp

P e H ee S ek P e H e

ω ωω ω

ω ω

⋅ ⋅+ ⋅ ⋅

should be inside

the unity circle when ω varies from zero to the Nyquist frequency. The system stability is checked in Fig.7. The vector locus is within the unity circle. Therefore, the designed controller is stable.

B. The System Operation The energy recycling electronic load system should

operate according to a specific time sequence, which is implemented by an SCADA (Supervisory Control And Data Acquisition) scheme. In Fig.1, it is seen that each converter is supervised by a DSP, and then all the DSPs are supervised by

a cabinet monitor, which is linked to a computer. The computer is the central controller with an HMI (Human Machine Interface). The dashed lines illustrate the communication network based on a tree topology CAN fieldbus. A communication protocol is drafted to guarantee commands and data transfer in the 2-level network.

The flow chart of system operation is shown in Fig.8. All the instructions are input through the HMI on the computer. The central controller sends the messages to the cabinet monitor and then the cabinet monitor handles the messages and dispatches them to the corresponding node. The central controller collects the acknowledgements after a short time delay.

After the start command is received, the power stages start with the inverter. The inverter firstly operates in a rectifier mode to charge the dc-link capacitors. Only after the dc bus is stabilized at the required voltage can the first stage IPOS-IZFF converters begin drawing current from DUTs. In the stop process, the IPOS-IZFF converters are ceased prior to the back-end inverter. Otherwise, the power flows to the dc bus but can not inject to the grid, thus the whole system fails.

Nowadays, the final outcome of whether a power source is deficient is not enough for the manufacturer. The SCADA scheme collects the test data of the power sources during the test, such as the actual output voltage and current. These data

0

0ω =

/ Tω π=

Fig.7 Stability verification on the Nyquist plane

N

Y

Start HMI

Initialization

Check

An abnormal channel?

Start the burn-in test

Data acquisition at regular time

Time out?

Stop the burn-in test

Output Excel reports

Exit HMI

Solve manually

N

Y

Setup

Fig.8 System operation flow chart

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are preferred since they can reflect more information of the power sources and apply for further analysis and forecast. They are reported in the output Excel reports and curves are shown on the HMI.

IV. EXPERIMENTAL RESULTS A 15kW prototype of the proposed energy recycling

electronic load system was built to verify the theoretical analysis in the previous sections. Five 3kW IPOS-IZFF converters in parallel are connected respectively to the DUTs, and a central 3P4W inverter feeds the energy back to the utility grid. The DUTs used are OT7014-004 AC/DC Mid Power Rectifiers of AcBel Polytech Inc. with the nominal output voltage of 48V.

The detailed components and parameters used are listed in Table Ⅱ.

TABLE.Ⅱ Parameters of the system IPOS-IZFF converter

Power volume (Pin) 3kW Input voltage(Vin) 42~56V

Output voltage(Vout) 750V Main Switches(S1, S2, S3, S4) IPP110N20N

Secondary-side Diodes(D1o, D1s, D2o, D2s) MUR1560Magnetizing Inductors(Lm1, Lm2, Lm3, Lm4) 55µH

Turns ratio(n2/n1) 16:10 Clamp Capacitors(Cc1, Cc2, Cc3, Cc4) 2.2µF Secondary-side Capacitors(C1s, C2s) 4.7µF

Switching frequency(fs) 100kHz Digital controller DSPIC33FJ16GS504

Grid-connected inverter Power volume (Pin) 15kW Input voltage(Vin) 750V

Output phase voltage(rms) 220V Output inductors(L) 4mH

Fundamental Frequency 50Hz Switching Frequency(fs) 10kHz

Digital controller TMS320F2808

Fig.9 shows the waveforms of ZVS soft switching of IPOS-IZFF converter at rated power when the input voltage is 48V. In the dashed ellipse, the gate signal and DS voltage of the main switch S1 make it clear that the ZVS is achieved with resonance and clamping during turning on and off respectively, which reduces the switching losses. The voltage stress is depressed, so low voltage mosfets can be used here to reduce conduction losses and improve performance.

The total input current and the current through the inductor L1 are illustrated in Fig.10.The input current ripple is very small due to four phases interleaved structure.

The three-phase output currents of the 3P4W grid-connected inverter are shown in Fig.11, which are highly sinusoidal with 120° phase shift. The harmonic spectrum of the output current at 15kW is shown in Fig.12, and the measured THD is 1.05%, far below the international standard.

In Fig.13 (a), the voltages of two dc bus capacitors are balanced. In Fig.13 (b), the neutral current has only switching frequency ripple with the zero-sequence current control strategy.

Fig.9 ZVT performance of main switch

2μs/div

il15A/diviin5A/div

iin

il1

Fig.10 Input current and inductor current

Fig.11 Grid current of three phases

0.00%0.10%0.20%0.30%0.40%0.50%0.60%0.70%0.80%0.90%1.00%

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Fig.12 Harmonic spectrum

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The efficiency of the proposed system is given in Fig.14. It is measured on condition that five front-end IPOS-IZFF converters are draining the same current and the input voltages are the rated 48V. The efficiency is higher than 90% at most of the load conditions and the highest point is above 92.2%.

V. CONCLUSION This paper presented an energy recycling electronic load

system for DC power supply burn-in test with high efficiency. The proposed system consists of high step-up IPOS-IZFF converters with active-clamp circuits and a 3-phase 4-wire grid-connected inverter. It has the following advantages.1) High efficiency is obtained with the designed high step-up IPOS-IZFF converter. 2) The interleaved structure of IPOS-IZFF converter attains low input current ripple. 3) Low THD of feedback current is achieved with an improved repetitive controller. The mathematical model analysis and design considerations are presented in detail. A 15-kW prototype has been built and experimental results confirm the validity and applicability of the proposed system.

ACKNOWLEDGMENT This project is supported by Zhejiang Key Science and

Technology Innovation Group Program (2010R50021), and National Nature Science Foundation of China (51177149).

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[6] C. A. Ayres and I. Barbi, "Power recycler for DC power supplies burn-in test: design and experimentation," in Proc. 1996 Applied Power Electronics Conference and Exposition. APEC 1996. pp. 72-78.

[7] V.Y. Golikov, V.I. Meleshin, V.I. Antonov, and D.A. Ovchinnikov, "Efficient and adaptive energy recycling load," Industrial Electronics, 2008. IECON 2008. 34th Annual Conference of IEEE. pp.723-728.

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[11] P. Mattavelli, and F.P. Marafao, "Repetitive-based control for selective harmonic compensation in active power filters," IEEE Transactions on Industrial Electronics, vol.51, no.5, pp. 1018- 1024, Oct. 2004.

[12] K. Zhang, Y. Kang, J. Xiong and J. Chen, "Direct repetitive control of SPWM inverter for UPS purpose," IEEE Transactions on Power Electronics, vol.18, no.3, pp. 784- 792, May 2003.

[13] G.F. Franklin, J.D. Powell, and A.Emami-Naeini, Feedback Control of Dynamic Systems. Addison-Wesley, MA, 1991.

Fig.13 (a) Voltages of dc bus capacitors. (b) Neutral line current.

87%

88%

89%

90%

91%

92%

93%

0 2 4 6 8 10 12 14 16

Input Power (kW)

Effic

ienc

y

Fig.14 System efficiency

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