……

……

Fig.1 Energy recycling load system

Energy Recycling Load System with a High Gain DC-DC Converter for Ultra Low Voltage Power

Supplies Hao Ma, Qian Guo, Xiaoming Han and Longyu Chen College of Electrical Engineering, Zhejiang University

Hangzhou, 310027 China E-mail: mahao@cee.zju.edu.cn

Abstract— An energy recycling electronic load system with an input-parallel and output-series (IPOS) active clamping current-fed half-bridge converter is proposed in this paper. It is suitable for ultra low voltage high current DC power supplies in the burn-in test. The current-fed half-bridge converter has advantages of high voltage conversion ratio, low input current ripple and high efficiency. Its duty cycle range is wide, proper for the large input current. Moreover, the circuit component is reduced, for the clamp switches shares one clamp capacitor. The operational processes and design considerations are presented. Finally, a 1V/200A-input and 48V-output current-fed half-bridge converter is built for a 3kW electronic load system and the experimental results testify the effectiveness and feasibility.

Keywords—Energy recycling load system; input parallel and output series current-fed half-bridge converter; ultra low voltage high current; high gain

I. INTRODUCTION Energy recycling load is widely used in burn-in tests of

power supplies to verify their quality. It feeds the output power of the DUTs (Device Under Testing) back to the utility grid. It has advantages of energy saving, less heat dissipation, smaller volume over the traditional load bank. Although a lot of researches have been done in energy recycling electronic load for DC power supply burn-in tests [1-6], there are rarely electronic loads for ultra-low voltage power supplies.

Nowadays, ultra-low voltage, high current DC power products are widely used in microprocessors’ power supplies to accord with the increasing working clock frequencies [7]. Intel VRM (Voltage Regulator Module) 11.1 requires a usable voltage range of 0.5V-1.6V. The required maximum continuous load current and maximum peak current are 130A and 150A, respectively [8]. So the demands for electronic loads for ultra-low voltage high current power supplies are increasing.

In order to transfer energy to the grid, the back-end grid-connected inverter of the energy recycling electronic load needs a high dc-link voltage. In the past, several DUTs are connected in series to form a high dc bus [4]. These DUTs can not be tested individually and they should have isolated output. A front-end boost converter is commonly employed to step up the voltage to a high dc bus [5-6]. However, the boost converter has a limited ability of voltage gain. In the high voltage conversion ratio applications, there are high peak currents in the switch and the diode, which increase the

conduction loss and degrade efficiency. The current-fed half-bridge converter is a good candidate for low voltage high current input applications [9-10]. Unfortunately, in ultra low voltage large current situations, a wide range of duty cycle is a requirement from light load to full load to deal with the voltage drop on the PCB broad. The conventional current-fed half-bridge converter is not allowed to work with a duty cycle smaller than 0.5. If its two main switches turn off simultaneously, the energy stored in the leakage inductor causes severe voltage overshoot.

In this paper, an energy recycling electronic load system for DC power supplies with ultra low voltage high current is proposed. An IPOS active clamping current-fed half-bridge converter is employed as the first stage and is presented in detail. Its input-parallel structure shares the large input current and the output-series structure doubles the voltage gain, which ensures a good performance in this application. Furthermore, the circuit is simple with reduced component, and it works well with a wide range of duty cycle. The paper addresses the circuit features, the operational principle and the design considerations. A 1V/200A-input 48V-output current-fed half-bridge converter is built for a 3kW electronic load system and the experimental results validate the feasibility of the design.

II. THE CIRCUIT TOPOLOGY

A. The Energy Recycling Load System Fig. 1 shows the configuration of the energy recycling load

system for ultra low voltage high current DC power supplies in the burn-in test. It consists of three stages: the load imitation stage, the voltage step-up stage and the power feedback stage.

L1 L2

C1

DR1 DR2

DR3 DR4

Da1 Da2Ca1 Ca2

Cc1

iin

iL1 iL2

iS1

iD1

iCc1

iL12

+

vo

-

+

vin

-

io

1:n

S1

Sa1 Sa2 iS2

Lk1

Ds2

Cs2S2Ds1

Cs1

L3 L4

C2

DR5 DR6

DR7 DR8

Da3 Da4Ca3 Ca4

Cc2

iL3 iL4

iS3

iD2

iCc2

iL34

1:n

S3

Sa3 Sa4 iS4

Lk2

Ds4

Cs4S4Ds3

Cs3

ilk2

ilk1

Fig.2 Topology of IPOS active clamping current-fed half-bridge converter

Fig.3 Key waveforms with duty cycle no larger than 0.5

The load imitation stage (Stage 1) consists of a parallel of high gain dc-dc converters, which connect to the output of the DUTs respectively to imitate different loads. These converters boost the low input voltage all to a 48V dc bus. This ensures a flexible design, for these converters can be designed separately to comply with DUTs of different rated output voltages, e.g. 1V, 3.3V, 5V, 12V. The current-fed half-bridge converter is employed in this stage for DUTs with 1V output.

An Interleaved ZVS Flyback-Forward (IZFF) converter is adopted for the voltage step-up stage (Stage 2) [11]. With interleaved structure, two coupled inductors works in the flyback mode and forward mode alternatively in the different switching subintervals, and both modes can transfer energy to the secondary-side. All the switches work with ZVS operation and this improves the efficiency.

The power feedback stage (Stage 3) is a single-phase full-bridge grid connected inverter. Its responsibility is to inject a sinusoidal current into the utility grid. The low THD, high power factor, good dynamics are the requirements.

B. IPOS Active Clamping Current-fed Half-bridge Converter The circuit topology of the IPOS active clamping current-

fed half-bridge converter is shown in Fig.2. It is in Stage 1 of the system to boost the low 1V output voltage of the DUTs to the 48V dc bus efficiently. The operational modes of a single unit with duty cycle 0.5D > have been summarized in [12]. However, in ultra low voltage high current applications, the duty cycle increased significantly from light load to full load to compensate the voltage drop on the PCB broad. The operational modes with 0.5D ≤ are unavoidable for light load and are presented below.

In Fig.2, iS are the main switches and aiS are the clamp switches. siC and aiC are the parasitic capacitors of the according main switches and clamp switches respectively ( i =1,2,3,4). CjC are the clamp capacitors; kjL are the leakage inductor ( j =1,2). In a single unit, there is only one clamp capacitor, which is shared by the clamp switches, so the components of the circuit are reduced. For the interleaved control pattern, the control signals for the two unit has a 90°shift.

The key waveforms of the circuit with 0.5D ≤ are shown in Fig.3. Due to the symmetrical feature, only half of the main subintervals in one switching period of a single unit are analyzed, and the remaining subintervals are similar. The circuit operational processes are shown in Fig.4.

1) Subinterval 1 [t0-t1]: The main switches are in the OFF state and the clamp switches are in the ON state before t1. The primary winding of the transformer is in short circuit and the output capacitor 1C transfers energy to the load. Both of the inductor currents charge the clamp capacitor. The current of each inductor ( LjI ) and the voltage across the clamp capacitor ( 1CcV ) are expressed by:

10( ) ( ) in Cc

Lj Ljj

V VI t I t t

L−

= + (1)

1 21 1 0

1

( ) ( ) L LCc Cc

C

I IV t V t t

C+

= + (2)

2) Subinterval 2 [t1-t2]: The antiparallel diode 2aD of the clamp switch 2aS conducts, so 2aS can turn off with ZVS at t1. The voltage across the main switch 2S equals the voltage on the clamp capacitor. The current 2LI flows though 2aD and charges the clamp capacitor 1CC .

3) Subinterval 3 [t2-t3]: The turn on signal of the main switch 2S is given at t2. The current of the inductor 2L is caused by the input voltage to increase linearly. The clamp capacitor 1CC and the leakage inductance 1kL form a resonant circuit. The transformer is about to transfer energy to the secondary side and the output capacitor is charging. The current of the leakage inductor is described as:

1 1 0 2( ) [1 cos( ( ))]lk Li t I t tω= − − (3)

where 01 1

1

k CL Cω = is the resonant angular frequency. A

portion of the current of 1L is still charging the clamp capacitor, and this current is decreasing.

4) Subinterval 4 [t3-t4]: The current of the clamp capacitor reverses at t4. The clamp capacitor transfers energy to the primary winding. The leakage inductor current is the combination of the inductor current and the clamp capacitor current:

1 1 0 2( ) [1 cos( ( ))]lk Li t I t tω= + − (4)

5) Subinterval 5 [t4-t5]: At t5, 2S turns off and its parasitic capacitor is charging, while the parasitic capacitor 2aC of the clamp switch is discharging. The leakage inductor current begins falling.

6) Subinterval 6 [t5-t6]: At t6, the antiparallel diode 2aD of the clamp switch conducts as the parasitic capacitor 2aC finishes discharging. Then the clamp switch 2aS can turn on with zero voltage at this moment. The voltage across the main switch 2S is clamped to the voltage on the clamp capacitor.

The converter is superior to the conventional one in terms of the wide operating range. Compared with the modes of

0.5D > , the operational principles of 0.5D ≤ have different characteristics. The clamp capacitor stores energy when both of the main switches in a single unit are in the OFF state, and it releases energy when either of the main switches is in ON state. Only the clamp switches operate with ZVS performance. Fortunately, the clamp capacitor depresses the voltage peak of the main switches. With light load, the switching losses of the main switches are not large due to the low voltage and low current. As the duty cycle of the circuit can be gradually increasing from zero, it works well in the starting process and an auxiliary starting circuit can be omitted.

The working point for heavy load is set at 0.5D > for high efficiency. All the switches operate with ZVS performance in both turn on and turn off switching transitions, so the switching losses are reduced greatly.

(a)

(b)

(c)

(d)

(e)

(f)

Fig.4 Operational processes of the current-fed half-bridge converter: (a) Subinterval 1 [t0- t1]; (b) Subinterval 2 [t1- t2]; (c) Subinterval 3[t2- t3]; (d) Subinterval 4 [t3- t4] ; (e) Subinterval 5 [t4- t5] ; (f) Subinterval 6 [t5- t6]

Fig.5 Current ripple with interleaved structure

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Dduty cycle

ΔΔ

in

Li

ii

Fig.6 Normalized total input current ripple in relationship with duty cycle

III. DESIGN CONSIDERATIONS As the load imitation stage of the electronic load system,

the IPOS active clamping current-fed half-bridge converter is designed with high voltage conversion ratio and low input current ripple. The design considerations are illustrated in this section. For simplicity, the circuit is considered as ideally symmetry, and the voltage of the clamp capacitor is assumed to be constant.

A. Voltage Gain Applying the volt-second balance principle to the inductor

and neglecting the leakage inductance, a simplified result of the voltage conversion ratio for practical application can be obtained as follows:

( )(1 )in s Cc in sV DT V V D T= − − (5)

12

=Cc outV Vn

(6)

2(1 )

= =−

out

in

vM

Dv n (7)

The voltage gain is doubled owing to the output-series structure.

B. Input Current Ripple On the primary side, the large input current is shared

among the four input inductors and conduction losses are reduced. The waveforms of each inductor current and the total input current are shown in Fig.5. With the four phases interleaved structure and the current sharing control strategy, the four inductor currents Lii have the same shape and average value. Their only difference is the phase shift. The total input current ini is the sum of four inductor currents and its ripple frequency is four times of theirs. The time points t1 and t2 can be calculated based on the duty cycle. The normalized total

input current ripple ΔΔ

in

Li

ii

with the relationship of the duty

cycle D can be derived as:

1 4 ,0 0.251(2 4 )( 0.25) ,0.25 0.5

(1 )(3 4 )( 0.5) ,0.5 0.75

(1 )4 3 ,0.75 1

−⎧ ≤ ≤⎪ −⎪− −⎪ ≤ ≤⎪ −Δ ⎪= ⎨ − −Δ ⎪ ≤ ≤

⎪ −⎪

−⎪ ≤ ≤⎪⎩

in

Li

D DD

D D DD Di

D Di DD D

D DD

(8)

(8) is drawn in Fig.6. When the duty cycle is 0.25 or 0.5 or 0.75, the total input current ripple is cancelled. With a limited duty cycle between 0.2 and 0.8 from light load to full load, the maximum total input current ripple is approximately a quarter of the inductor current ripple.

C. Load Simulation Principle To imitate a load bank with a certain resistance, the

electronic load should have the same current draining capability. Assuming the load bank of the DUT is a resistor R , the DUT’s output current satisfies:

=dUiR

(9)

where U is the DUT’s output voltage and is determined by the DUT’s type. Therefore, if the input current of the front-end load imitation converter is controlled as di , the electronic load is imitating the resistor R . Besides, there is a precondition that the load imitation converter has very low input current ripple, which is satisfied owing to the above design. The front-end converter should work at an input current controlled mode. To implement a simple control strategy of input current sharing between two interleaved units, their input currents are controlled separately and the references are both set to half of

di , which is expressed by:

12 34 2= = =ref ref d

L Li Ui i

R (10)

Fig.7 Turn-on waveforms of (a) main switch and (b) clamp switch at light load

Fig.8 Turn-on waveforms of (a) main switch and (b) clamp switch at full load

Fig.9 Current ripple of (a) four input inductors (b) total input

By changing the current references, the electronic load can simulate different loads. The current references are given by a 2-level tree topology SCADA (Supervisory Control And Data Acquisition) system. In Fig.1, the red dashed lines and the blue dashed lines show a CAN fieldbus and a RS-485 fieldbus respectively. A LabVIEW based HMI (Human Machine Interface) is implemented on a computer, which acts as the central controller to supervise the whole system and collects data during the test.

IV. EXPERIMENTAL RESULTS A 3kW prototype of the proposed energy recycling

electronic load system is built to verify the previous analysis. Its input characteristics are shown in Table I. The detailed components and parameters used are listed in Table II. In the load imitation stage, a 1V/200A-input 48V-output IPOS active clamping current-fed half-bridge converter is employed, and the other converters with input voltage of 3.3V, 5V, 12V are omitted in this paper.

The turn-on waveforms of main switch 1S and the clamp switch 1aS of the current-fed half-bridge converter with input current of 20A are shown in Fig.7. As this is a light load, the duty cycle is less than 0.5. In the dashed ellipse, the gate signal and DS voltage clearly reveals that only the clamp switch operates with ZVS performance, which agrees with the analysis.

In Fig.8, the turn-on waveforms at full load are shown. Since the duty cycle is larger than 0.5, the ZVS performance is achieved for both of the switches with resonance. The switching losses are highly reduced. Also, due to the depressed voltage stress, low withstand voltage mosfets with low forward voltage drop can be used.

The current ripple of each input inductor and the total input current ripple at full load are illustrated in Fig.9. Since the

currents of the input inductors are interleaved, the total input current ripple is extremely small. The total input current of 200A is shown in Fig.10(a). It has almost no ac components so that the electronic load can be regarded as a resistive load bank. The grid voltage and the injected current when the system works at full load of 3kW is shown in Fig.10(b). The output current of the grid-connected inverter is highly sinusoidal and well in phase with the grid voltage. The measured THD is 2.6%, far below the standard.

The efficiency of the current-fed half-bridge converter is given in Fig.11. The losses of the circuit components as a percentage of the input power at full load are presented in Fig.12. With the ultra high input current, the loss on the PCB copper is dominant. The voltage drop on the impedance of the PCB copper calls for an increasing duty cycle from light load to heavy load. The changing trend of the measured duty cycle is drawn in Fig.13. At most of the load range, the duty cycle is larger than 0.5 and ZVS is achieved for both the main and the clamp switches. The efficiency of the 3kW system is given in Fig.14.

TABLE I. INPUT CHARACTERISTICS

Rated Voltage 1V 3.3V 5V 12V Maximum Current 200A 100A 100A 100A

Quantity 1 2 2 1

TABLE II. CIRCUIT PARAMETERS

IPOS Current-Fed Half-Bridge Converter Input voltage(Vin) 0.9~1.1V

Power volume (Pin) 200W Output voltage(Vout) 48V

Inductance(Li) 0.65µH Magnetizing Inductance 8.3µH

Leakage Inductance(Lk1, Lk2) 0.02µH Turns ratio(1/n) 1:10

Clamp Capacitors(Cc1, Cc2) 15µF Parallel Capacitors(Csi, Cai) 5.3nF

Main Switches(Si) and Clamping Switches(Sai) IPP015N04N Switching frequency(fs) 50kHz

IZFF DC/DC Converter Input voltage(Vin) 48V

Output voltage(Vout) 380V Grid-connected Inverter

Output Voltage(rms) 220V Fundamental Frequency 50Hz

Fig.10 (a) Total input current (b) Grid voltage and injected current.

55.00%

60.00%

65.00%

70.00%

75.00%

80.00%

85.00%

90.00%

8 19 29 39 49 59 69 80 92 101 111 121 130 140 150 162 172 183 192 201

Input Power (W)

Effic

ienc

y

Fig.11 Efficiency of current-fed half-bridge converter

8.11%

0.63% 0.70% 0.60%2.40% 2.48%

0.15%

15.50%

0.00%2.00%4.00%6.00%8.00%

10.00%12.00%14.00%16.00%18.00%20.00%

Fig.12 Losses of circuit components

00.10.20.30.40.50.60.70.80.9

0 50 100 150 200

Input Current (A)

Dut

y Cy

cle

D

Fig.13 Duty cycle in relationship with input current

0.7

0.75

0.8

0.85

0.9

0 500 1000 1500 2000 2500 3000

Input Power (W)

Effic

ienc

y

Fig.14 Efficiency of 3kW system

V. CONCLUSION An energy recycling electronic load system for DC power

supply burn-in test is proposed in this paper. The front-end IPOS active clamping current-fed half-bridge converter in its load imitation stage is introduced in detail. It has characteristics of high voltage conversion ratio, low input current ripple and

high efficiency. The IPOS structure divides the large input current and doubles the output voltage gain. The converter can meet the requirement of a wide duty cycle range. In addition, the circuit is simple with reduced clamp component and ZVS performance is achieved at most of the load range. A 1V/200A-input 48V-output IPOS current-fed half-bridge converter is built for a 3kW electronic load system and the experimental results confirm the proposed system with the converter is a competitive choice for ultra low voltage high current input applications.

ACKNOWLEDGMENT This project is supported by Zhejiang Key Science and

Technology Innovation Group Program (2010R50021), and National Nature Science Foundation of China (51177149).

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