Isolated Dual Boost Bridgeless Power Factor

Correction AC-DC Converter

Mohammed Mahmood, Huang-Jen Chiu, Senior Member, IEEE, Yu-Kang Lo, Member, IEEE,

Quang Trong Nha, Pham Phu Hieu, Irwan Purnama Department of Electronic Engineering

National Taiwan University of Science and Technology Taipei, Taiwan (R.O.C)

Abstract-Isolated power factor correction converters expose

several shortcomings such as: the presence of slow-recovery

diodes on conduction path leading to conduction losses and

complexity in sensing circuit. This paper presents a new

topology named isolated dual boost bridgeless PFC converter

not only to improve efficiency by discarding of the low-recovery

diodes but also to simplify the sensing circuit methodology.

Additionally, a laboratory prototype with 100-140 V input, 400 V/7S0 W output was built and verified to demonstrate the circuit

feasibility in this study. The experimental results shown that the

efficiency improved by using bridgeless converter concept.

I. INTRODUCTION

In recent years, many efforts on power factor correction (PFC) have been made to simplify the topology, improve efficiency, and comply with input current quality regulations and standards [1-3]. Most active PFC converter circuits are formed by a diode bridge rectifier at first state and are followed by ether one DC-DC converter or two DC-DC converters. Among them, the conventional boost-type topology is the most popular topology for PFC applications where unity power factors (PF), less component count require. To reduce the conduction losses by minimizing the number of the semiconductor devices in conduction path, large number of researches on bridgeless PFC topologies has been presented in [4-10]. Some researches on single-stage bridgeless PFC converter with the galvanic isolation have been presented in [11-14]. An asymmetrical half-bridge topology [12] and an asymmetrical full-bridge topology [13] are used in low-to­medium power applications due to the asymmetrical current distribution leading to high current stress and core saturation of the power transformer. A symmetrical full-bridge topology presented in [14] is suitable for high power applications due to having symmetrical current distribution in all MOSFETs and AC operation of the power transformer. However, those researches on bridgeless PFC converters cannot fully discard the low-frequency diodes for the reasons of common-mode EMI. One slow-recovery diode as well as switch carries the input current in the switch conduction interval in their

978-1-4799-0073-2/13/$31.00 ©2013 IEEE

topologies. The conductance still dominates on this rectifier diode under low-input voltage condition.

Figure 1. Circuit diagram of the proposed PFC converter

(a)

(b)

Figure 2. Equivalent circuits of the proposed circuit during (a) positive line­frequency cycle, (b) negative line-frequency cycle

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In this paper, a new bridgeless PFC converter with galvanic isolation, namely isolated dual boost converter, is proposed. The circuit diagram of proposed bridgeless PFC is shown in Fig. 1. The positive- and negative-line-frequency cycle is sensed and used to control the MOSFETs so that two pairs of M3-M4 and MI -M2 are conducted during positive and negative cycle, respectively, to reduce the conduction losses of body diodes of MOSFETs. As indicated in Fig. 2(a), the transformer T2 disables during the positive line cycle. Meanwhile, transformer T I is able to transfer input energy to the load via two capacitors CJ, C2 and two diode rectifiers DI and D2. Similarly, lower MOSFET pair MI and M2 is turned on during the negative line cycle as indicated in Fig. 2(b). During negative cycle, transformer TI is disabled due to conducting of MOSFETs MI and M2. The transformer M2 will be able to transfer energy to output by alternatively switching of MOSFET pair M3 and M4.

II. OPERATION AND CIRCUIT ANALYSIS

For simplicity, two output capacitors CI and C2 are assumed to be very large. Therefore, the output-capacitor­voltages (V CI and V C2) are constant. To operate in CCM, two boost inductors LI and L2 are also chosen to be very large. Two inductor currents (ILl and IL2) are treated to be constant value (Id within one switching period. The output voltage is treated as a voltage source (Vo). Since the line frequency is much lower than the switching frequency, the rectifier voltage Yin is therefore considered to be constant during one switching cycle. Due to having the same operation in positive and negative line-frequency cycle, in this section, only positive cycle is considered. There are four operation states within one switching cycle. Due to having similar principle of operation, only two states are considered in this study. The equivalent circuits of each stage and several key waveforms are depicted in Fig. 3(a-b) and Fig. 4.

(a)

(b)

Figure 3. Equivalent circuits within positive line-frequency cycle of (a) [tdol interval and (b) [t2-t1] interval

Vg2 b!---+---+-+---f-------JI-----+I •• I 1 VLI I I

v. _ NVo

In 2

Figure 4. Some key waveforms of the proposed PFC converter

During the positive (or negative) line-frequency cycle, the input voltage Yin is a function of AC line voltage and can be expressed by bellow equation

V;n = Ivac I = J2vac I sin [( 2Jr f) t JI (1)

During [to-td state as indicated in Fig. 3(a), two MOSFETs MI and M2 are both turned on at to. Two inductors LI and L2 are linearly increased by the input voltage. Therefore, their voltages are calculated as

VLI = vL2 = V;n (2) Two diodes DI and M2 are turned off. Therefore, two

capacitors CI and C2 are discharged their energy to the output load during this state. As shown in Figure 3(a), during this interval, the capacitor currents iCI and iC2 are calculated below

iCi = iC2 = -10 (3) During [tl-t2] state as shown in Fig. 3(b), MOSFET MI

keeps turning-on while MOSFET M2 is turned off at tl. The secondary winding voltage also reflects to the primary winding by amount of (VoN/2). As a result, the voltage across two inductors LI and L2 are computed as

Vu = V;11 (4)

vL2 = V;11 - NVo 12 (5)

On the secondary side, diode DI starts to conduct at tl. The energy is transferred from input to output via the transformer TJ, diode DI and two capacitors CI and C2. As

466

shown in Fig. 3(b), during this state, the capacitor currents iCI and iC2 are calculated as

ic, = -10 (6)

iC2 =-ipN =ILN (7) Similarly, during [trt3J interval, both MOSFETs MI and

M2 are turned on. The output load is supplied by two output capacitors CI and C2. The voltage of two inductors LI and L2 and current of two output capacitors C, and C2 have been considered in (2) and (3). During [trt4J interval, MOSFET M2 keeps conducting while M, is turned off at t3. The secondary winding voltage also reflects to the primary winding by amount of (VoNI2). As a result, the voltage across two inductors LI and L2 can be computed as

VL, = '-':/1 -NVo /2 (8)

(9)

On the secondary side, diode D2 begins to turn on at tl' The energy is transferred from input to output via the transformer T" diode D2 and two capacitors CI and C2. During [t3-t4J interval, the capacitor currents iCI and iC2 are calculated as

(10)

iC2 = -10 (11) Applying volt-second balance to two inductors L, and L2,

average voltage of two inductors over one switching period is zero at steady state. From (4), (5), (8), and (9) we obtain:

D '-':n + (1-D) ( '-':n -; N ) = 0 (12)

Solving (12), the static voltage gain of the proposed circuit is estimated by

� 2

Vrec N(1-D) (13)

Applying amp-second to two capacitors CI and C2, average current of two capacitors over one switching period is zero at steady state. From (6), (7), (10), and (11) we obtain:

(14)

Equation (14) reveals the relation between the output current 10 and two inductor currents (ILl=IL2=Id. However, the input current lin is summation of two inductor currents. The current gain is calculated as

� (I-D)N

(/1 2D

III. SENSING CIRCUIT DESIGN AND CIRCUIT

CONSIDER A TlON

(15)

Since the diode-bridge rectifier is eliminated for the bridgeless PFC topology. Therefore, the input voltage and input current sensing should be specially designed. In this study, several recommendations of the sensing circuits are provided for bridge less PFC converters. The overview of the

proposed PFC consisting of the power stage, sensing circuits, and digital signal processing (DsP) TMS320F28035 from Texas Instruments is shown in Fig. 5. To provide isolation for output voltage feedback loop, a TL431 controller can be used as a standard error amplifier in conjunction with a photo­coupler. The output voltage loop controller is recommended to be designed with slow bandwidth to gain high PF. Because there are many available guidelines for designing of the isolated feedback loop by using TL431 controller and photo­coupler, only the input current and input voltage sensing are considered in this study.

As shown in Fig. 6(a), the input current sensing circuit consists of radio frequency interference (RFI) filter, differential amplifier with low-pass filter, signal rectifier, and output filter. The input current sensing circuit requires many filters because of following reasons. Firstly, the current spikes induced by switching action appear in the sensing signal. Secondly, to reduce power loss on sensing resistor Rs, its value is chosen to be as small as possible. Therefore, the operational amplifier (op-amp) U, is designed with high gain to scale this weak input signal. By that reason, the noise contained in the input current also is amplified by the multiplication of static gain. Thirdly, strong RFIs are greatly weakened by the op-amp's radio frequency (RF) rejection. Unfortunately, op-amp's common mode rejection ratio (abbreviated as CMRR or CMR) dramatically degrades at high frequency due to inherent non-linearity. When a strong RFI is fed into the amplifier it may become rectified by the internal junction of the IC and then appear as a DC output offset leading to measurement errors of the ADC value.

The DM noise filter is to reject the high frequency noises appearing between two input pins of op-amp. Differential bandwidth BWOM (at -3dB) is calculated as follows

(16)

Where: R,=R'a=R'b, C,=C'a=C'b' The differential bandwidth BWOM is designed a bit higher the bandwidth interest of the input signal. In this case, the BW OM is designed higher two times of switching frequency.

Figure 5. The circuit implemention of the proposed PFC

467

___________________________ ,'-________________________________________ J ______________ : (a)

A111plifier ..... Rectifier

(b)

To • Rf,ADC.

Cf5 Yo!

Figure 6. Circuit diagram of (a) the input current sensing and (b) input voltage sensing

The CM noise filters are to reject the high frequency noises appearing between the op-amp's input pins to the ground. The common-mode bandwidth BW CM (at -3dB) is computed by below equation

(17)

The BW CM selection is limited by gain-bandwidth product (GBWP) of op-amp UI . For current sensing, a high GBWP op-amp is used. When the GBWP and desired gain GU1 of op­amp U I are known, the B W CM is chosen to be less than the ratio of GBWP/GU1. It notes that the front high frequency noise filter just works well when two resistor Ria-Rib and capacitor Cla-C1b pairs are well matched. Otherwise, the CM noises will be converted to DM noises at the input pins. For that reason, 5 percents capacitors C1a-C1b and 1 percent metal film resistors Ria-Rib are recommended for good matching. Moreover, as shown in (16), C2 should be chosen much bigger than CI and C2 to suppress mismatching of the time constants RI aCI a and RlbC1b.

The differential amplifier UI provides a first order band­limiting for the input current. Its -3dB bandwidth is calculated by following equation

1 BWFI = (18) 2;rRrCr

Where: Rr=Rn=RQ, Cr=Cn=CQ. The bandwidth of this stage is chosen to be higher than the input current signal bandwidth (twice switching frequency).

The differential-amplifier gain (op-amp UI ) included RFI filter will be equal to

R(I H = -�-o

Ria + R2a Rib + R2b (19)

Due to having no diode rectifier, a signal rectifier circuit (op-amps U2 and U3) is used to rectify the AC output signal of UI . Since two op-amps U2 and U3 is powered by a single­voltage supply, it is necessary to use rail-to-rail output op­amps to obtain precise output signal without DC offset. The

static gain in (19) is designed by the input current sensing signal under low line-full load condition, maximum ADC input voltage range, and sensing resistor Rs.

A simple RSrCSf low-pass filter provides only bandwidth of interest at the op-amp output. The bandwidth of this low­pass filter is calculated as follows

1 BWF5 = (20) 2;rRfsCfs

Unfortunately, most types of ADCs present a small capacitance and resistive load on their input. Therefore, the output filter's resistors should be sufficiently small to interface between an op-amp and ADC without attenuation at the bandwidth of interest. In order to simplify in calculation, the BWFS is chosen at least ten times of highest frequency of input signal.

Due to dealing with low-frequency input and having low­static gain for differential amplifier Ub the input voltage sensing is designed with less attention. Op-amp UI and output filtering RfsCrs are both designed with low bandwidth to eliminate low-frequency noise in 50/60 Hz frequency input. The time constant of RnCn is much greater than that of the input current sensing. Input resistors Ria, Rib, R2a, and R2b are also very large. Because the condition of BW CM is impossible to obey, the input voltage sensing circuitry is shown in Fig. 6(b) without CM filtering.

TABLE I. SPECIFICATIONS AND MAIN PARAMETERS OF THE PROPOSED PFC CIRCUIT

Specifications and Paramerters Value

Input (VaJt) 100-140 V/60 Hz

Outpu (V J Po) 400 V/7S0 W

Switching frequency (fsw) 37.5 kHz

MOSFETs(MI·M4) IXFHI6N80P

Diodes (01-04) F20L60

Transformers (TI and T2) Turn ratio: 28:9

Output capacitors (COl and Co2) 2x470 IlF

Boost inductors (LI and L2) 600llH

TABLE II. CURRENT AND VOLTAGE SENSING DESIGN

Paramerters Current sensing Voltage sensing

Op-amp (VI) TSV992 LM324

Op-amp (V2&V3) OPA4376 OPA4376

CM filter Rla=Rlb=820 Rla=Rlb=3MegO

Cla=Clb=820pF No applicable

OM filter CF2.2nF C2=68pF

R2a=R2b=lkO R2a=R2b=220kO lSI oder band-limiting Rf1=R12=9kO Rf1=R12=43kO

Cf1=C12=S6pF Cf1=C12=lnF

Rectifier R2=lkO R2=lkO

R4a=R4b= I OkO R4a=R4b= I OkO

Output fi Iter Rf5=1800 Rf5=lkO Cf5=220pF Cf5=lnF

IV. EXPERIMENTAL RESULTS

In order to verify the circuit operation and evaluate performance of the proposed topology, a laboratory prototype

468

has been built with following design specifications: 100-140 V input, 60 Hz line frequency, 400 V1750 W output, and 37.5 kHz switching frequency. The list of components and main parameters of the design are shown in TABLE I. The average current mode control was used to shape the input current to be in phase with the input voltage by using digital controller.

The list of components for current sensing and voltage sensing design is shown in TABLE II. The accuracy is ±1 % for resistors and ±5% for capacitors. For current sensing circuit, a TSV922 op-amp characterizing 20 MHz bandwidth at unity, rail-to-rail output is used for differential amplifier UI ' The differential amplifier U I is designed with 9V N static gain Ho and 320 kHz BWFI to provide only the bandwidth of interest (twice PWM frequency). The product bandwidth of UI at 9 VN gain is around 2.2 MHz. The BWCM is also designed at 2.2 MHz to remove the CM noise from the input signal. In this study, the BWDM is chosen at 370 kHz to provide only the bandwidth of the sensing signal. The output filter bandwidth BWF5 is designed at 4 MHz to attenuate high frequency and avoid the effect of the ADC's input capacitance. The rectifier Uz and U3 used OPA4376 op-amps featuring 5.5 MHz bandwidth, rail-to-rail output for input current and input voltage sensing circuits. For voltage sensing circuit, an LM324 op-amp with 1 MHz bandwidth is used. Similarly, the input voltage sensing is respectively assigned with 390 Hz of BWDM, 0.013 of Ho, 3.7 kHz of BWFb and 159 kHz of BWF5•

Fig. 7(a-b) shows the input current sensing (CHI), input voltage sensing (CH2), and input voltage (CH4) waveforms operated under 100 V input, 720 W output and 140 V input, 720 W output conditions. The current and voltage sensing outputs are connected to the ADC input of DsP.

, , CHI: 2.5 VIDIV

: CH2: 2.5 VIDIV

.,. J ..... . l l'

· · 1 + i'

. . . . . �

2 :"CH4 ' 250 V/Diy 'f++++t++++:j'-+ . . -rH--j-+-. H! !-+! +i +-+++-f-+.+-+. ++'-+++-1

.. / (a)

2.5 VIDIV

: CH2: 2.5 VIDIV . . . . . . . . . /. . . . . . . . . . , .

(b)

Figure 7. Input current sensing , input voltage sensing, and input voltage at (a) 180 V input, 1 kW output, (b) 240 V input, I kW output

: CHI&CH2: 500 VIDIV .1. · ····· · .. ········· ...

. CH4: 250 V/DlV

: CH1&CH2: 500 V/OIV .1 .

TIME: 4 ms/DlV . (a)

TIME: 4 ms/DlV :

(b)

Figure 8. Voltage on MOSFETs, input voltage, and input current at (a) 180 V input, 1 kW output and (b) 240 V input, 1 kW output

TABLE III. MEASURED PF AND EFFICIENCY OF PROPOSED PFC

Efficiency [%] Power Factor

Load[%] 100 V 120 V 140 V 100 V 120 V 140 V

20 91.43 92.29 93.42 0.996 0.993 0.991

40 91.95 92.51 93.81 0.998 0.994 0.993

60 92.21 92.64 93.88 0.999 0.996 0.995

80 92.45 92.85 93.92 0.999 0.999 0.998

100 92.33 92.65 93.75 0.999 0.999 0.999

FIg. Sea-b) shows the voltage stress on MOSFETs (CHl&CH2), input current (CH3), and input voltage (CH4) waveforms operated under 100 V input, 400 V I 720 W output and 140 V input, 400 VI 720 W output conditions. The measured efficiency and power factor are illustrated in T ABLE III. As seen, the maximum efficiency is 93.92%. The PF over all conditions is higher than 0.9.

V. CONCLUSIONS

The isolated bridgeless dual boost PFC converter which features high efficiency, unity power factor (PF) was studied in this paper. A laboratory prototype of the proposed PFC with 100-140 V input, 400 V1750 W output has been thoroughly

469

investigated. By careful designing of the circuit parameters, the developed prototype achieves a maximum efficiency of 93.92%. High PF and low harmonic components were also obtained by using the average current mode control with variable duty control scheme to shape line current to be in phase with input voltage.

ACKNOWLEDGMENT

The authors would like to acknowledge the financial support of the National Science Council of Taiwan through grant number NSC 100-2628-E-OII-009-MY3.

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