Impact of Modulation Schemes on the Power Capability of High-Power Converters with Low Pulse Ratios

Jie Shen ♠, Stefan Schröder ♠, Hanno Stagge ♦, Rik W. De Doncker ♦ ♠ GE Global Research,

♦ Institute for Power Generation and Storage Systems, E.ON Energy Research Center, RWTH Aachen University

E-Mail: jie.shen@research.ge.com

Keywords «multilevel converters», «Pulse Width Modulation», «modulation strategy», «Variable speed drive», «IGCT», «switching losses»

Abstract The design of modulation schemes at low pulse ratios is a known topic. However, most of previous work has focused on Optimized Pulse Patterns, e.g. Selective Harmonic Elimination (SHE). For industrial applications, standard carrier modulators are still highly attractive in many cases. Unfortunately, few papers presented insightful studies on carrier modulators at extremely low pulse ratios. This paper covers this gap. At extremely low pulse ratios, several special phenomena of carrier modulators are observed. Their mechanisms are explained in detail. Moreover, a quantitative comparison between different carrier-based modulation schemes is presented. Based on that, several design criteria for modulators at low pulse ratios are proposed at the end.

1 Introduction The design of high-power medium-voltage converters has been widely discussed for some time already [1] – [4]. Such converters typically use 3.3/4.5/6.5 kV IGCT or IGBT devices combined with multilevel topologies, e.g., a three-level neutral-point-clamped IGCT converter reaches a power level of approx. 10 MW at 3.3 kVac [2] [9]. For such MV converter designs, the power capability and the power quality are always challenging. Unfortunately, MV semiconductor devices generate considerable losses at each switching event. To avoid an unnecessary power de-rating, the switching frequencies for such MV converters are typically extremely low, e.g. 5 pulses per 180 ° fundamental for a 50 Hz load (i.e. 5X, obtained approx. by using 450 Hz carrier frequency) [5] [6] [7] [11] – [12]. The current ripple or the power quality (THD) of the converter is a major design challenge. At such low pulse ratios, it is highly attractive to explore optimal modulation schemes to enhance the power capability without dramatically sacrificing the power quality of the converter. Numerous works on the modulation schemes have been presented previously [1] – [4] [8] [10]. However, most of them focus on the THD performance and the power losses of the devices at a relatively high switching frequency, e.g. at carrier-to-fundamental frequency ratio cr =fc / f0 = 21 or higher. Here fc is the carrier frequency and f0 is the fundamental frequency [8] [10]. However, such a ratio is almost unachievable for 3L-NPC IGCT converters due to the extremely high switching losses. It is hard to find literature that conducts a systematic study on the impact of modulation schemes on the power capability of high-power converters with extremely low pulse ratios (e.g. 5X or 3X). This gap is covered in this paper. This paper provides an insight into the impact of modulation schemes on the power capability of high-power converters, when the converter operates at extremely low pulse ratios. This paper does not propose any novel modulation schemes, but focuses on several standard schemes like the continuous

(CPWM) and discontinuous carrier modulators (DPWM) and the Selective Harmonic Elimination (SHE) that have been widely used for industrial applications. Nevertheless, at extremely low pulse ratios, several special phenomena of the modulators are observed. Their mechanisms are explained in detail. Moreover, a quantitative comparison between different modulation schemes is presented. Based on that, several optimization criteria are summarized. The study is based on a 3L-NPC converter that uses 4.5 kV IGCT devices. The load is composed of a three-phase voltage source with inductors in series. The load impedance is 15 % p.u. unless specified. For the study in this paper, the output is kept at 3.3 kV / 50 Hz with unity power-factor. The dc-link voltage is 2x2.5 kV. The performance of different modulators is scanned (simulated) in a frequency-domain based circuit simulator. The simulator was developed explicitly for the performance screening of high-power converters. The simulation speed and precision of this tool has been proven in [13].

2 Impact of current ripple on converter power capability The current ripple generated by the pulse modulators can be significant at low pulse ratios, e.g. 30 % superimposed to the sinusoidal current. These ripples increase the turn-off losses Eoff and reduce the turn-on losses Eon of the devices. For hard-switching IGBT converters, the changes in Eon and Eoff are almost compensated, so that the total switching losses remain almost unchanged. However, for IGCT converters, where a turn-on snubber circuit is always equipped, the absolute Eon of IGCTs is negligible compared to Eoff (Eon/Eoff≈10 %). As a result, the higher the current ripples, the higher are the switching losses that generate thermal stress. The example in Fig. 1 shows that the thermal stress of the IGCT increases significantly, when the current ripples are considered. The impact of the current ripple on the converter power capability can be demonstrated via a power capability versus load impedance study, as shown in Fig. 2. An identical SHE-5X pulse pattern is applied for both drives. The inductive load impedance here determines the current ripple at the output. It can be the leakage impedance of a transformer, or the sub-transient impedance of a machine. The output current becomes quasi-sinusoidal (i.e. no ripple), if the load impedance is sufficiently high. For example, P1,nom and P2,nom in Fig. 2 are the power capabilities with high load-impedances. Notice that P1,nom ≠ P2,nom. It can be seen that the power capability of the IGBT converter is almost immune to the load impedance variation (i.e. the same power rating as applying the sinusoidal load current). In contrast, the power capability of the IGCT converter drops by 7 % at 0.2 p.u. load impedance, and further drops by 20 % at a lower load impedance 0.06 p.u. Hence, a considerable power capability de-rating for IGCT converters should be taken into account for loads with low load impedances. It can further be concluded that low-THD pulse patterns from the modulator are preferred to reduce the turn-off losses of IGCT converters. Meanwhile, loads with high impedance are preferred, since they help to reduce the current ripple with a given pulse pattern. It should be noted that both converters in the scenario do not reach their peak turn-off current. If the load impedance further decreases, the current ripples are further enlarged and the peak turn-off current may exceed the SOA limit. In such cases, the power capability of both converters drops dramatically.

Fig. 1 Impact of current ripples on the device stress (69.6 °C with ideal sine-current, 76.8 °C with real current): simulation results of an outer device (IGCT) in a 3L-NPC converter.

Fig. 2 Impact of load impedance on converter power capability

3 Asynchronous carrier modulation When asynchronous carriers [17] are applied for variable-frequency drive applications, the actual carrier-to-fundamental frequency ratio (cr) is changing (e.g. could be an integer or non-integer), since its carrier frequency is fixed. Strictly speaking, asynchronous carriers have no control over the carrier-to-fundamental offset angle (θinit) in real-world implementations. However, in this paper the carrier ratio is always selected to be rational so that a periodic pulse pattern can be simulated. Here θinit is defined as the offset between the carrier and the fundamental angle (0 °) of phase a (defined for the cosine function). Several pulse patterns generated at different carrier angles θinit = 0 ° to 270 ° with an integer carrier ratio “6” are illustrated in Fig. 3. It can be observed that the pulse patterns significantly differ from each other. The pulse ratio may vary between 3X and 4X (e.g. the negative pulses in (a) and (c)). Notice that the pulse widths may differ from each other, even when the pulse ratios are the same (see the negative pulses in (b) and (d)). In Fig. 3 a Phase Disposition (PD) carrier [8] [14] – [16] is selected due to the good THD performance. The min-max common mode voltage is injected to the reference [14]. Since this injection leads to a continuous switching of all legs, in this paper it is named CPWM (Continuous PWM) to differentiate against the Discontinuous PWM (details in Section 5).

3.1 Performance variation effect The example above shows that the pulse pattern generated from an asynchronous carrier is not fixed, but depends on the initial carrier angle at integer carrier ratios. It can be expected that these voltage patterns further lead to different current response waveforms, and may further affect the stress of the devices. A performance screening is done at different angles to quantify these effects. The carrier ratio “occasionally” is an integer cr=9. The current THD, the thermal and the peak-current stress of the hotspot devices in the converter are plotted versus the carrier angle, see Fig. 4.

Fig. 3 Different pulse patterns generated from an asynchronous carrier modulator with different carrier angles @ cr=6 (CPWM)

Fig. 4 Current THD and device stress vs. carrier angle at cr=9 (CPWM)

Fig. 5 Current THD and device stress vs. carrier angle at cr=6 (CPWM) Fig. 6 Current THD and device stress vs. carrier angle

at cr=6.3 (CPWM)

Interestingly, the performance of the converter varies according to the carrier angle: The worst-case thermal stress of the hotspot IGCT device occurs at θinit=240 °, while the lowest thermal stress (i.e. the best-case) occurs at 90 °. The minimum current THD occurs at θinit=0 °. Since in reality this carrier angle is random for asynchronous carriers, the power capability of the converter has to be rated to its worst-case, i.e. at θinit=240 °. This power is rated as 1 p.u. as reference. It is then the baseline for comparisons with other modulation schemes (see Fig. 14). The performance variation effect becomes more significant in a second screening with a reduced even-integer carrier ratio cr=6, see Fig. 5. The converter power is rated in such a way, that either the thermal or the peak turn-off current stress of the devices just reaches the limit at the worst-case carrier angle. This power is approximately 1.1 p.u. compared to at cr=9, i.e. increased by 10 %. The performance variation effect however disappears, when the carrier ratio “occasionally” is a non-integer. Fig. 6 shows the case at cr=6.3. It should be noted that the pulse pattern is periodical after 10 periods at this ratio (i.e. 63 carrier periods in 10 fundamental periods). The observation window is 10 times that of the fundamental period. The converter power here does not require a de-rating, since the performance curves (thermal and peak-current) are flat throughout all carrier angles, see Fig. 5.

3.2 Sideband-overlap effect To explain the performance variation effect at low carrier ratios, a so-called “sideband-overlap effect” theory is developed here. It is well-known that the spectrum of a PWM pattern is composed of multiple sidebands [8]. The generalized expression of a harmonic component in the mth sideband is:

( ) ( ) ( )( )mnmnmn tntmCth θθωθω ++++= 00cccos (1)

Here θc and θ0 are the phases of the carrier and the fundamental, respectively, Cmn and θmn are expressions depending on the modulation scheme, and m and n are integer constants. If the modulation scheme and the fundamental signal are determined (and θ0 for phase a is 0 °), the phase angle of the harmonic hmn is depending on the carrier angle θc (i.e. equal to θinit in phase a):

( ) ( )( ) °=−=+++= 0 and wherecos 00cinitinit0c θθθθθθωω mnmnmn mtnmCth (2)

For example, if the carrier angle θinit varies by 360 °, all 1st sideband harmonic components rotate by 360 °, while all 2nd sideband components rotate by 720 °. While the carrier angle θinit is shifting, the individual harmonic components are also rotating with multiple speeds depending on the sideband number except for the baseband components. A well-known application of this theory is the carrier interleaving for multiple converters. For example, the carrier angles for two legs in an H-bridge topology are typically phase-shifted by 90 °, while their reference signals are equal (but inversed in the second leg). By doing that, the amplitudes of all baseband harmonics are doubled, the amplitudes of all 1st sideband harmonics are increased by sqrt(2), and all 2nd sideband harmonics are completely eliminated at the H-bridge output compared to the spectrum of individual legs. The THD performance of the converter is therefore improved. This mechanism is illustrated in Fig. 7. Similarly, the interleaving angle can be set to 45 ° for 4 paralleled converters to cancel the 2nd and 4th sidebands [6]. More comprehensive explanations have been presented in the past [6] [16] [18]. Although it has been clearly stated in [8] that the sidebands could be overlapped especially at integer carrier ratios, this effect is negligible in most applications – even at cr=21. As far as there is a sufficient distance between the sidebands (i.e. with high carrier ratios), the amplitudes of the sideband components attenuate dramatically, before they overlap each other. The RMS value of the spectrum (i.e. THD) remains unchanged under such conditions, even when individual harmonic components rotate with different speeds (while the carrier angle is shifting). A graphical explanation is shown in Fig. 8 (a).

Fig. 7 Carrier interleaving for H-bridge topologies (a) Spectrum of the left-leg with 0 ° carrier angle; (b) Spectrum of the right-leg with 90 ° shifted carrier angle; (c) Spectrum observed from the H-bridge output. Notice: phase angles of sidebands in this figure are simplified as the relative angles between two legs

Fig. 8 Simplified explanation of sideband-overlap effect using asynchronous carrier at low carrier ratios (a) sufficient distance between sidebands at high carrier ratios; (b) Mixed sidebands at (non-integer) low carrier ratios; (c) Overlapped sidebands at (integer) low carrier ratios

Multiple sidebands start mixing with each other, when the carrier ratio is further reduced. However, Fig. 8 (b) demonstrates that components of multiple sidebands may still be decoupled from each other, if the ratio “occasionally” is not an integer. The THD value of the spectrum remains constant under such conditions, i.e. independent of the carrier angle. However, the observed spectrum components are composed of multiple overlapped sidebands, if the carrier ratio is extremely low and also an integer! E.g. the observed 4th harmonic is contributed by the 1st and the 3rd sidebands at cr=6 [8]. Under such conditions, the amplitude of an individual harmonic component varies with the carrier angle, since it contains multiple overlapped components from multiple sidebands that rotate with different speeds. Finally, the THD, the current ripple as well as the device stress are all depending on the carrier angle, as the graphical explanation shows in Fig. 8 (c). It should be noted that such sideband-overlap effects may also occur at certain non-integer ratios. For example, at cr=4.5, the 8.5th harmonic in the pulse pattern can be contributed by the components of the 1st and 5th sidebands (can be deduced from the pulse pattern theory [8]). This leads to the performance variation of the converter as well, but it is normally much weaker than with integer carrier ratios. Strictly speaking, at extremely low carrier ratios, a complete decoupling of sidebands is only valid for irrational numbers.

3.3 Performance variation vs. carrier ratio The performance variation effect is more significant at lower carrier ratios due to the reduced distances between the sidebands. As an example, the current THD variation versus the carrier ratio (including integer and non-integer ratios) is studied in Fig. 9. The THD at each given carrier ratio is scanned with carrier angles from 0 ° to 360 °. The worst and best-case THDs are recorded. It is seen that the THD curve drops continuously with the increasing carrier ratios, which is independent of any specific carrier ratio such as triple-odd orders. This observation is consistent with the according statements in [8] [18]. Moreover, the THD variation effect using asynchronous carriers occurs only “occasionally” at integer carrier ratios and disappears at the non-integer ratios shown in Fig. 9. The performance variation effect is more significant at lower ratios. The THD variation at higher ratios like cr=21 and cr=72 are negligible, and therefore they are not plotted here. All these effects can be well-explained using the sideband-overlap theory.

Fig. 9 THD performance vs. carrier ratio at integer and non-integer ratios

Fig. 10 Stress of outer devices vs. carrier angle at cr=6 (CPWM)

Fig. 11 Stress of outer devices vs. carrier angle at cr=7 (CPWM)

Fig. 12 Stress of outer devices vs. carrier angle at cr=9 (CPWM)

4 Synchronous carrier modulation From previous section it is concluded that the power capability performance of a converter using asynchronous carriers is determined by the “worst-case” carrier angle. In contrast, if the carrier angle is continuously locked at the “best-case” angle, the converter power capability can be greatly improved. This concept is called synchronous carrier modulation [17]. For example, the power capability of the converter can be maximized, when the carrier angle is locked at θinit=90 ° with minimized thermal stress as shown in Fig. 4. The rated power capability can therefore be increased by about 10 % compared to using the asynchronous carrier. Similarly, the carrier angle should be locked to θinit=0 °, if the power quality (current THD) should be optimized. By properly selecting the optimal carrier angle for synchronous carriers, either the power capability or the power quality of the converter can be maximized (but normally not at the same time).The proper selection of the carrier ratio therefore becomes an important step in the converter design. Triple-even-order carrier ratios: Fig. 5 has shown the screening result of an even-triple-order ratio cr=6. The converter power capability is now increased compared to the power at cr=9 (quantitative analysis in Fig. 14), which is the benefit from the reduced switching losses with 3(4)X pulse ratio. However, to get a better understanding of whether the device capability in the converter is well utilized, a more detailed screening should be executed: instead of recording only the global worst-case device stress in Fig. 5, the stress of individual hotspot devices (i.e. outer devices S1 and S4 in each leg) versus the carrier angle is plotted, see Fig. 10. It is interesting to observe that two outer devices in a single leg are not equally stressed (either thermal or peak-current) at any given carrier angle. The stress curves between S1 and S4 are phase-shifted by 180 ° carrier angle. This indicates that the power capability or power quality of the converter has the potential to be further improved, since not all hotspot devices are fully stressed at the same time.

This unbalanced device stress effect can be explained with the pulse modulation theory [8]. At triple-even order carrier ratios using PD carriers, there are even-order components like the 2nd and 4th in the frequency spectrum in both the voltage and the current response pattern. In other words, their patterns in the time domain are not symmetric in the positive and the negative half cycles. This leads to different turn-off current profiles of S1 and S4 in the leg. On the other hand, the patterns in three phases are identical due to the triple-order ratio. There is no further unequal stress of outer devices between phase-legs. Hence, the stress curves in Fig. 10 are identical for three phases. It should be noted that the stress of S1 and S4 could be balanced by using the POD (Phase Opposition Disposition) carrier setup [8]. However, analysis shows that POD carriers have a poorer THD performance that leads to a strong power de-rating. Generally, POD carriers are not preferred. Odd-non-triple-order carrier ratios: By selecting the carrier ratio to “7”, the positive and negative half voltage patterns and current waveforms in each leg become symmetrical using the PD carrier setup. Hence, the stress of two outer devices (S1 and S4) in a leg is equalized. However, the stress is then not equally distributed between three legs. Fig. 11 shows that the stress curves of hotspot devices are phase-shifted by 120 °. This is due to the unsymmetrical pulse patterns between three phases at non-triple order carrier ratios [8]. Since these devices are not equally stressed, the power capability of the converter is not fully utilized as well. Triple-odd-order carrier ratios: Fig. 12 shows the device stress screening at cr=9. Now the stress of all 6 outer devices is equalized! This is because of the symmetric positive and negative half pattern in each leg, as well as the symmetric patterns between three legs (triple-order ratio). In terms of this, “9” is an optimal carrier ratio because all hotspot devices are fully utilized. Below this ratio (i.e. cr<9), hotspot devices cannot be equally stressed (except for cr=3 that is obviously too low for most applications), while the THD as well as the peak turn-off current stress also becomes more and more critical. In such cases, modulation schemes such as discontinuous modulation (DPWM) or Selective Harmonic Eliminations (SHE) could be attractive candidates.

5 Discontinuous modulation For standard carrier modulators, each leg has one switching event in each sampling cycle [8], i.e. generating a continuous pulse pattern (CPWM). The basic concept of discontinuous modulation (DPWM) is to inject the common-mode voltage in such a way that one of the phase voltage references is clamped to one of the dc-link voltages when its phase current is high. Since the switching losses are reduced, the power capability of the converter can be increased [10] [19]. As a well-known modulation scheme, DPWM at high pulse ratios has been widely discussed in the past. It is well-known that DPWM has higher THD than CPWM at the same carrier ratio. Therefore, the carrier ratio for DPWM has to be significantly increased to achieve a comparable THD for both as a fair comparison. The case study in [10] shows that at cr=21 (CPWM-equivalent) there is no intrinsic benefit using DPWM over a wide modulation index range compared to CPWM. However, DPWM may have significant advantages over CPWM at extremely low pulse ratios. Fig. 13 shows an example of DPWM with cr=9, which generates 4X pulses. Compared to CPWM with cr=6, it is found that the performance variation effect using DPWM is intrinsically attenuated due to the enlarged sideband distance (by 50 %). Moreover, all hotspot devices are equally stressed due to the regained nice triple-odd-order carrier ratio “9”. The device capabilities are fully utilized that helps to improve the converter performance. A quantitative comparison will be given in Section 6.

6 Overview of a quantitative comparison Six standard modulation schemes are selected for the power capability vs. power quality study: two continuous carriers (CPWM), two discontinuous carriers (DPWM) and two Selective Harmonic Elimination (SHE) modulators are screened, see the results in Fig. 14. For carrier modulators the

power rating vs. THD trajectories are obtained by scanning the carrier angle 0 – 360 °. The enclosed trajectories contain the performance information of the asynchronous carrier mode (i.e. the worst-case) as well as the synchronous carrier mode (i.e. the best-case). It can be noted that the power capability axis is normalized according to the base-line power rating at asynchronous carrier CPWM with cr=9, i.e. defined as 1 p.u. power. Two standard SHE patterns 5X and 3X are analyzed as a benchmark. Note that the SHE patterns are well-known for good THD performance. Moreover, such highly symmetrical patterns guarantee equalized device stress in the converter.

Fig. 13 Current THD and device stress vs. carrier angle at cr=9, 60 ° DPWM

Fig. 14 Summary: impact of modulation schemes on the power capability and the power quality of a 3L-NPC IGCT converter using 4.5 kV IGCT devices

It can be seen from the trajectory of CPWM with cr=9 that the performance of the asynchronous carrier has to be rated at the worst-case power rating and the worst-case current THD, i.e. 1 p.u. power with 13 % THD. In contrast, if its carrier angle is locked at its optimum (i.e. synchronous carrier), its performance is improved to 1.09 p.u. power with 12 % THD (for the best power capability), or improved to 1.07 p.u. power with 8 % THD alternatively (for the best power quality). Similar trends are found at the trajectory of CPWM with cr=6. The performance is only 1.12 p.u. power with 14 % THD, if the asynchronous carrier is used. Notice that this power capability is not even much higher than with cr=9. This is due to the high current ripples at cr=6 so that the converter power is limited by the turn-off current stress. An important conclusion is that for high-power applications with extremely low pulse ratios, the power capability of a converter cannot be simply increased by continuously reducing the pulse ratio, since the current ripple at low pulse ratios becomes more critical and may exceed the device’s SOA. Fig. 14 shows a second trajectory assuming that the devices are not current-limited as a reference. However, for real applications, the turn-off current and the thermal limit have to be considered simultaneously. On the other hand, if a synchronous carrier is applied for CPWM with cr=6, its performance can be greatly improved to 1.34 p.u. power with 15 % THD. Notice that its power capability is increased by 22 % compared to asynchronous mode. The THD remains almost identical to CPWM with cr=9. The performance of DPWM is insensitive to the carrier angle: at cr=15, the THD is stabilized at 10 %, while the power rating varies slightly between 1.04 and 1.07 p.u. power. At a reduced ratio cr=9, its power capability varies between 1.22 and 1.33 p.u., while the THD varies slightly between 15 % and 17 %. On the other hand, the benefit from using synchronous carriers for DPWM is not as significant as for CPWMs, which is due to the attenuated sideband-overlap effect. Comparing the synchronous CPWM to SHE patterns, it is found that at a 5X pulse ratio SHE-5X has no power capability advantage over a power-optimized synchronous CPWM with cr=9. However, at 3X pulse ratio, SHE-3X has slightly higher power than optimized CPWM with cr=6 (1.37 p.u. vs. 1.34 p.u.). The reason is that at the 5X pulse ratio, both the SHE and CPWM schemes fully utilize all hotspot devices in the converter. At 3X pulse ratio, although the carrier angle of CPWM is numerically

highly optimized, it can no more equally stress the hotspot devices (while SHE-3X still can). Again, equalized stress distribution is an important criterion when selecting modulation schemes.

7 Summary This paper explores the impact of modulation schemes on the power capability of high-power converters with extremely low pulse ratios. The study is executed on a frequency-domain based circuit simulator. A 3L-NPC converter using 4.5 kV IGCT devices is selected for this study, which represents a standard MV converter with a 3.3 kV ac output. Different modulators are introduced and compared to each other. A quantitative “power capability versus power quality” chart is presented. It should be noted that several special behaviors of the modulators occur at extremely low pulse ratios. Notice that these phenomena do not occur in converters with high pulse ratios. This study demonstrates that modulation schemes do have significant impact on the power capability of high-power converters. Key design criteria are summarized as follows: 1) For high-power converters with turn-on snubber circuits (e.g. when using IGCT devices), the

power capability is sensitive to the current ripple. The higher the ripple, the higher are the turn-off losses and the peak turn-off current stress of the devices. Therefore, the power capability of an IGCT converter is much more sensitive to the load impedance than a hard-switching IGBT converter.

2) For high-power converters with low pulse ratios, the power capability of the converter cannot

always be effectively improved by reducing the pulse ratio, since high current ripples may increase the thermal stress of the devices and the currents may also exceed their SOA. Hence, low-THD pulse patterns such as SHE are highly preferred at a given pulse ratio. High THD schemes such as POD carriers increase the device stress and are not preferred.

3) For asynchronous carrier modulators, the THD performance and the device stress of a converter

may vary according to the carrier-to-fundamental angle. This can be explained by the sideband-overlap effect, which has been explored in this paper. If an asynchronous carrier is used, the power capability of the converter has to be rated according to its worst-case carrier angles.

4) In contrast, the power capability of a converter can be significantly improved, if a synchronous

carrier is used. However, at low pulse ratios it is not only important to lock the carrier ratio at integers, but also lock the carrier angle at its optimum. Only by doing both, the sideband-overlap effect may be exploited as a positive factor.

5) Equalized device stress distribution is an important indicator for evaluating the performance of a

modulation scheme. For carrier modulators, odd-triple-order carrier ratios such as “9” are preferred since they lead to a full utilization of the device capability of all devices in the converter. Below this ratio, the stress of hotspot devices can hardly be equalized independent of the carrier angle setup. Meanwhile, the THD and the turn-off current stress become more critical. Generally, CPWM schemes are less attractive below cr=9.

6) Discontinuous modulation DPWM is an attractive candidate for applications at extremely low

pulse ratios. Compared to CPWM, it has much lower performance variation due to an intrinsically increased carrier ratio. Meanwhile, it does not significantly increase the pulse ratio, so that the power capability of the converter is comparable to highly optimized synchronous CPWM. Therefore, it can tolerate asynchronous carrier mode at extremely low pulse ratios like 4X with cr=9. Notice that all hotspot devices are equally utilized in this case.

7) SHEs are neither optimized for the power capability nor for the power quality, but they are

practically a good compromise between the two criteria at extremely low pulse ratios. They are highly attractive for single-converter applications with less than 5X pulse ratios.

References [1] J. Rodriguez, S. Bernet, B. Wu, J.O. Pontt, and S. Kouro, “Multilevel Voltage-Source-Converter

Topologies for Industrial Medium-Voltage Drives”, IEEE Trans. Ind. Electron., vol. 54, no. 6, Dec. 2007, pp. 2930 – 2945.

[2] H. Abu-Rub, J. Holtz, J. Rodriguez, and B.M. Ge, “Medium-Voltage Multilevel Converters—State of the Art, Challenges, and Requirements in Industrial Applications”, IEEE Trans. Ind. Electron., vol. 57, no. 8, April 2010, pp. 2581 – 2596.

[3] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, Bin Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, ‘‘Recent Advances and Industrial Applications of Multilevel Converters’’, IEEE Trans. Ind. Electron., vol. 57, no. 8, Aug. 2010, pp. 2553 --- 2580.

[4] J. Rodriguez, Jih-Sheng Lai, and F. Z. Peng, “Multilevel Inverters: A Survey of Topologies, Controls, and Applications”, IEEE Trans. Ind. Electron., vol. 49, no. 4, April 2002, pp. 724 – 738.

[5] J. Holtz and N. Oikonomou, “Synchronous Optimal Pulsewidth Modulation and Stator Flux Trajectory Control for Medium-Voltage Drives”, IEEE Trans. Ind. Applicat., vol. 43, no. 2, March/April 2007, pp. 600 – 608.

[6] S. Schroeder, P. Tenca, T. Geyer, P. Soldi, L. J. Garces, R. Zhang, T. Toma, and P. Bordignon, “Modular High power Shunt-Interleaved Drive System: A Realization up to 35 MW for Oil and Gas Applications”, IEEE Trans. Ind. Applicat., vol. 46, no. 3, March/April 2010, pp. 821 – 830.

[7] J. Steinke, “Switching frequency optimal PWM control of a three-level inverter”, IEEE Trans. Power Electron., vol. 7, July 1992, pp. 487 – 496.

[8] D. G. Holmes and T. A. Lipo, “Pulse Width Modulation for Power Converters—Principles and Practice”. Piscatway, NJ: IEEE Press, 2003.

[9] T. Brückner, and R. Jakob, “New Medium-voltage Inverter Design with Very High Power Density”, IEEE Power Electronics Specialists Conference 2008, June 15 – 19, pp. 2962 – 2967.

[10] T. Brückner and D. G. Holmes, “Optimal Pulse-Width Modulation for Three-Level Converters”, IEEE Trans. Power Electron., vol. 20, no. 1, Jan. 2005, pp. 82 – 89.

[11] J. Holtz and N. Oikonomou, “Optimal Control of a Dual Three-Level Inverter System for Medium-Voltage Drives”, IEEE Trans. Ind. Applicat., vol. 46, no. 3, May/June 2010, pp. 1034 – 1041.

[12] H. L. Liu, G. H. Cho, and S. S. Park, “Optimal PWM Design for High Power Three-Level Inverter Through Comparative Studies”, IEEE Trans. Power Electron., vol. 10, no. 1, Jan. 1995, pp. 38 – 47.

[13] J. Shen, S. Schröder, H. Stagge, and Rik W. De Doncker, “A Fast and Precise Simulation Method for Performance Screening for High Power Converter Designs”, IEEE Energy Conversion Congress & Exposition (ECCE) 2012, Sep. 16 – 20, Raleigh, pp. 4418 – 4425.

[14] F. Wang, “Sine-Triangle versus Space-Vector Modulation for Three-Level PWM Voltage-Source Inverters”, IEEE Trans. Ind. Electron., vol. 38, no. 2, March/April 2002, pp. 500 – 506.

[15] G. Carrara, S. Gardella, M. Marchesoni, R. Salutari, and G. Sciutto, “A New Multilevel PWM Method: A Theoretical Analysis”, IEEE Trans. Power Electron., vol. 7, no. 3, July 1992, pp. 497 – 505.

[16] B. P. McGrath and D. G. Holmes, “Multicarrier PWM Strategies for Multilevel Inverters”, IEEE Trans. Ind. Electron., vol. 49, no. 4, Aug. 2002, pp. 858 – 867.

[17] J. Holtz, “Pulsewidth Modulation – A Survey”. IEEE Trans. Ind. Electron., vol. 39, no. 5, Dec. 2002, pp. 410 – 420.

[18] D. G. Holmes and B. P. McGrath, “Opportunities for Harmonic Cancellation with Carrier-Based PWM for Two-Level and Multilevel Cascaded Inverters”, IEEE Tans. Ind. Appl., vol. 37, no. 2, March/April 2001, pp. 574 – 582.

[19] B. Kaku, I. Miyashita, and S. Sone, “Switching loss minimized space vector PWM method for IGBT three-level inverter,” Proc. Inst. Elect. Eng., vol. 144, pp. 182–190, May 1997.