Design of dynamic synchronous multi-channel data acqui-sition system for lung sound based on FPGA

Benjin Wang123 Lei Miao123 Huiying Dong3

1State Key Laboratory of Robotics Shenyang Institute of Automation (SIA)

Chinese Academy of Sciences (CAS) Shenyang, Liaoning Province, China

2Shenyang Institute of Automation Chinese Academy of Sciences, Guangzhou, CAS

Guangzhou, Guangdong province, China wangbenjin@sia.cn miaolei@sia.cn

zheng8620@yahoo.com.cn

Jiangtao Li5 Zeguang Zheng24 Hongyi Li 23

3School of Information Science and Engineering Shenyang Ligong University

Shenyang, Liaoning Province, China 4State Key Laboratory of Respiratory Disease Guangzhou Institution of Respiratory Disease

Guangzhou, Guangdong province, China 5China Telecom Corporation Limited Taiyuan Branch

Taiyuan, Shanxi Province, China huiyingdong@163.com hli@sia.cn

Abstract–Dynamic lung sound signal analysis and processing re-quire synchronous multi-channel data acquisition system. In non-invasive and no pain lung sound diagnosis system, the highly ac-curate, synchronous and stable data acquisition system is the foundation of fellow-up work. In order to acquire the array data of lung sound, higher speed, reliability and synchronous data ac-quisition system can meet the requests. Lung sound signal was produced by lung vibration during air exchange. Simultaneous sampling maintains the phase information and provides us with more detailed information about physiology and pathology. Our method is to use piezopolymer sensor array attached to the back-side and capture the lung vibration information. This paper mainly presents a FPGA-based synchronous data acquisition sys-tem. FPGA as a main component offers the ADC chip timing and FIFO design using Verilog HDL source code. Furthermore, this paper solves the synchronization problems so that array phase information is saved. Test results of the data acquisition system can fully meet the need of data acquisition in array data acquisi-tion of lung sound.

Index Terms – simultaneous data acquisition, AD7606, FPGA, Lung sound, Verilog HDL

I. INTRODUCTION

As a general rule, airflow causes the vibration in lungs. Distinctive vibration produces inspiration and expiration sig-nals. Dynamic lung sound signal processing requires syn-chronous multi-channel data acquisition system. It will help diagnosis technology progress and promote treatment level. As noninvasive diagnosis, this system has been widely used in medical signal array processing. Scientists and physicians around the world observe analysis the data–from basic re-search in lab and medicine in treatment. Charleston-Villalobos, S. et al. in 2004 devoted efforts to evaluate deter-ministic interpolating functions to generate surface respiratory acoustic thoracic images based on multiple acoustic sensors and concluded that, although deterministic interpolation func-tions indicate different performances among tested techniques,

the Hermite interpolation function presents a more confident deterministic interpolation for depicting surface-type respira-tory acoustic thoracic imaging[1]. Torres-Jimenez et al. in 2008 design microphone array comprised five columns and five rows to cover completely the pulmonary area. Their work was to detect and assess the asymmetries in lung sound inten-sities[2]. Charleston-Villalobos, Sonia et al. in 2010 used li-near and nonlinear processing techniques analyzing thoracic crackle data and conclude that the time-variant autoregressive mode was fitted to count image of crackle sounds [3].

In lung sound data analysis and processing field, data ac-quisition system plays a very important role. High speed, pre-cision, synchronous of array data are vital for the fellow-up analysis. Field-programmable gate array (FPGA) is increa-singly used for AD control and FIFO design. By using simul-taneously sampled inputs AD chip and high speed FPGA, data acquisition system can achieve high precision coincidence timing and high count rate capabilities.

II. A BRIEF INTRODUCTION TO LUNG SOUND

Sounds produced by air exchange in human respiratory activity have been considered to contain relevant clinical in-formation since the stethoscope was invented in France in 1816 by René Laennec. During clinical practice, auscultation is performed by moving the stethoscope at the back of the sub-jects. Lung sounds from 294 cases of healthy Chinese were monitored and analyzed by frequency spectrogram analyzer. The results shown the mean values of main frequency were mostly less than 200Hz, although there are significantly dif-ferent between various age groups; child, middle and old ages[4]. People with respiratory diseases reflect different fre-quency characteristics. According to our experiments, inspira-tory and expiratory stridor breath sounds are mainly distri-buted in the low frequency part of the spectrum with band-width about 2 KHz, and have less energy; Vesicular breath sounds belongs to narrowband signal whose energy distributes in the peak around 1.5kHz; Stridor breath sounds with the

This work is supported by National Natural Science Foundationof China, under the contract number NSF(61102014). 978-1-4673-2237-9/12/$31.00 ©2012 IEEE

Proceeding of the IEEEInternational Conference on Information and Automation

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most wide-band frequency and energy concentrated in the vi-cinity of 2.5 kHz. Piezopolymer sensor was suitable for lung sound collection from the body surface and 3db bandwidth was from 2 Hz to 5 KHz. Fig.1. shows the piezopolymer sen-sor array.

In this paper, high-speed sampling rate and synchronous sampling technology were introduced to capture the details in breath activity. AD7606 is the ideal analog to digital convert chip with synchronous sample rate 200 KHz of each channel and meets the requirements.

III. DATA ACQUISITION SYSTEM

Data acquisition system can be classified in many ways. In this paper, it was classified based on input mode. Tradition-al input mode was called asynchronous input. Analog multip-lexer switches one of channels to a common output, depending

on the state of binary addresses and enables input. Switching time of multiplex loses the phase information in time domain which causes frequency-shift in frequency domain. Consider-ing the complexity of the lung sound signal, it is very hard to realize the phase compensation. And break-before-make switch hardly guarantees to protect against momentary short-ing. Data acquisition system for asynchronous is as shown in Fig.2..

This paper mainly discusses a synchronous data acquisi-tion system design. It contains a 8-channel swith16-bit and 200khz sample rate simultaneously sampled input ADC (AD7606), a FPGA (Altera EP3C25Q240C8N)which was used timing control and FIFO design, and power module (On Semiconductor NCP5661 series ).

IV. SYSTEM HARDWARE DESCRIPTION

A. Altera Cyclone III EP3C25 Series Features

Fig.3. synchronous data acquisition system structure

Fig.4. CONVST A, CONVST B and signals captured by digital oscilloscope

Fig.1. piezopolymer sensor array

Fig.2. asynchronous data acquisition system

block diagram

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Cyclone III EP3C25 Series Logic ElemM9K blocks, 608,256 bits ram, 66 18x18multglobal clock networks. Each M9K memory bIII device family provides nine Kbits of on-Quartus II software allows us to take advantmemory blocks by using the Verilog HDL soupaper, M9K blocks were configured as first-inbuffers. B. Analog Devices AD7606

AD7606 is an 8-channel simultaneouslAnalog to digital convert chip with true bipo16-bit ADC and 200 KSPS on all channels. Tonly 100mW from a single 5V power supp1MΩ analog input impendence regardless oquency. Antialiasing filter has a 3 dB cut-offkHz and provides 40dB antialiasing rejectionat 200 kSPS. The analog inputs accept true bnals and input range was decided by RANGchannel isolation of synchronous acquisition vents crosstalk between all input channels comasynchronous acquisition technology. C. ON Semiconductor NCP5661 series powe

The NCP5661 is a high performance lowlinear regulator suitable for high power applican ultra–fast response time and low noise with

Fig. 5. FIFO Buffer Architecture Block

Fig .6. Typical FPGA CAD FLO

ments 26,624, 66 tipliers, 4 plls, 20 block of Cyclone chip memory[5]. tage of the M9K urce code. In this n first-out (FIFO)

ly sampled input olar analog input, The devices draw ply. AD7606 has of sampling fre-f frequency of 22 n when sampling bipolar input sig-

G pin. Channel to n technology pre-mpared to that of

er module w dropout 1.0 A cations, featuring hout a bypass ca-

pacitor. In this paper, power modulput versions which have additionaand Error Flag increasing the utilimally robust and includes the safetya fault condition, which provides foLDO solution for server, ASIC pequipment applications, and many o

V. SOFTWARE

A. Design of pll-div clock This paper uses pll-div as sys

gering pulse which has lower clockcan be realized easily in software, gering pulse to reach the logic unitsis more, each pll-div with a signal vides up to five robust clock outpchanged manually and arbitrarily[8the request of AD7606 simultaneouin CONVST A pin and CONVCONVST A, CONVST B and oscilloscope. B. Design of combinational and se

Verilog HDL as hardware descsteps in the design of ADC configuerates in PARALLEL BYTE mode1, DB15 = 1). The RANGE pin irange; this pin is tied to a logic low±5 V for all channels. OS pins are upling ratio; in this system this pinover sampling was selected. CS 、Rconfigured to byte read operation mC. Design of the multi-channel hig

Multi-channel high speed FIFOtem. A FIFO buffer is a dedicated ma fixed array of registers. The regsynchronously (rising edge) with a and writing. The stack has two pointing to the next word to whicanother pointing to the next word FIFO has input and output data patas flags to denote the state of the FIFO module is divided into threechine, read state machine and flag machine transfers the data in a parater. The transmitter’s clock is notRead state machine transfers a AD7606 to a storage register. Flagble for reading and writing, the actority over the action to write data ioural modelling for combinational HDL as a vehicle designs, verifiecuit[12, 13]. Fig.5. gives a brief inarchitecture.

The Altera Quartus II design plete design environment that easilments. The design process is illustrinstructions for using the Quartus

k Diagram

OW

le was offered in fixed out-al features, such as Enable ty of NCP5661. It is ther-y features necessary during or an attractive high current ower supplies, networking

others[6].

DESIGN

stem clock and timing trig-k jitter. Phase compensation so this can ensure the trig-s at the same time[7]. What external clock source pro-

puts which phase shift can 8]. This character can meet usly receiving sample pulse

VST B pin. Fig.4. shows signals captured by digital

equential logic cription languages is at key uration circuit. AD7606 op-e (PAR /SER/BYTE SEL = is used to select the input

w; the analog input range is used to select the oversam-s are tied to logic low, no RD、FRSTDATA pins are

mode[9]. gh speed fifo O is a key part in this sys-memory stack consisting of gisters of the stack operate

common clock for reading pointers (addressing), one h data will be written and that will be read[10]. The

ths and two bit-line serving stack (full or empty)[11].

e sections: write state ma-state machine. Write state

allel format a storage regis-t available to the receiver.

channel parallel data of g state machine is responsi-ion from the FIFO has pri-to the FIFO. After behav-and sequential, the Verilog

es and synthesizes the cir-ntroduction of FIFO buffer

software provides a com-ly adapts to design require-ated by giving step-by-step II software to implement

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timing trigger and FIFO design circuits in an EP3C25Q240C8N device. Fig.6. gives a brief overview of a typical CAD flow for designing circuits that are implemented by using Altera FPGA devices, and shows how this flow is re-alized in Quartus II software[14, 15].

VI. EXPERIMENT TEST AND CONCLUSIONS

In the experiment, we acquire test signal from signal gen-erator. The results of test show that value of analog to digital convert is the typical value of the test signal. The system has fully accomplished the anticipated goals and met the needs of array data acquisition of lung sound.

This system can converts analog signals into digital sig-nals through a simultaneous ADC, which is the most impor-tant part of synchronous multi-channel data acquisition sys-tem. Synchronous multi-channel data acquisition technology reserves respiratory sounds phase information which contains mechanical and clinical pulmonary information. FPGA as trigger module makes full use of pll-div technology, and en-sure system clock and trigger pulse stability. In addition, FPGA is used to store data with on-chip ram. This function has the advantage of being small volume, low power con-sumption, high reliability and high data access speed consider-ing of exchanging data with external ram.

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[2] Torres-Jimenez, A., et al. Asymmetry in lung sound intensities detected by respiratory acoustic thoracic imaging (RATHI) and clinical pulmonary auscultation. in Engineering in Medicine and Biology Society, 2008. EMBS 2008. 30th Annual International Conference of the IEEE. 2008.

[3] Charleston-Villalobos, S., et al., Acoustic thoracic image of crackle sounds using linear and nonlinear processing techniques. Medical and Bi-ological Engineering and Computing, 2011. 49(1): p. 15-24.

[4] Binyong, T., Monttoring and frequency spectrogram of lung sound in healthy chinese--294 cases analysis. Shanghai Medicine, 1997.

[5] ALTERA, Cyclone III Datasheet. 2010. [6] Semiconductor, O., NCP5661: 1.0 A Fast Response Low Dropout Linear

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[8] Altera, Phase-Locked Loop (ALTPLL) Megafunction User Guide. no-vember 2009.

[9] Devices, A., AD7606 Data Sheet. 2010-2011. [10] Bin, H., et al. Design of a multi-channel high speed FIFO applied to

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[11] Elrabaa, M.E.S. A new FIFO design enabling fully-synchronous on-chip data communication network. in Electronics, Communications and Pho-tonics Conference (SIECPC), 2011 Saudi International. 2011.

[12] IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language. IEEE Std 1364-1995, 1996: p. i.

[13] D.Ciletti, M., Advanced Digital Design With the Verilog HDL Second Edition. 2010.04: p. 13.

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