Detection elements for on-cantilever laboratory

T. Ščepka , D. Gregušová, Š. Gaži, Š. Haščík, J. Fedor, J. Šoltýs, R. Kúdela and V. Cambel

Institute of Electrical Engineering, SAS, Bratislava, 841 04 Slovak Republic e-mail: tomas.scepka@savba.sk

Micrometer-scaled cantilever-based sensors can be utilized in electrostatic and magnetic measurements and also are perspective for future chemical and biological sensing applications. GaAs is the most used III-V material for cantilever probe development thanks to its optoelectronic properties, high mobility 2D electrons, high piezoresistivity and sufficient mechanical properties. Novel sensing probes, prepared by integration of various detection elements are perspective for specific requirements. This work is mainly focused on technology process of such micro-CLs and also on fabrication of detection elements (transistors) with the aim to integrate directly on the micro-CLs.

1. Introduction

Cantilever-based sensors have been intensively used and studied for more than two decades. Up to now, however, they have been prepared almost exclusively from silicon. Silicon has been used extensively in semiconductor industry. Due to this fact silicon technology is relatively mature and immediately available in micro-electro-mechanical systems (MEMS), which is not yet fully the case in GaAs technology.

CL sensors can be divided into two basic groups according to their functionality. The first group was developed for scanning force microscope (SPM) purposes, whereas the second was developed for biological and environmental sensing, where sharp tips are unnecessary.

Basic Si micromachining does not give the possibility to tune the CLs thickness precisely. The thickness can fluctuate between 5 and 25%, best results are achieved when combinations of Si3N4, Si, and SiO2 are used (silicon-on-insulator technology). As a result, all important CL parameters (spring constant, resonant frequency) fluctuate too [1, 2]. With Si sensors having reached maturity, they can hardly be improved and adapted to new functionalities and extreme experimental tasks due to intrinsic properties of the material. By contrast, CLs based on GaAs and its heterostructures have the potential for further innovation. GaAs as a mechanical material promising for micromechanics was introduced by K. Hjort [3]. A complete technological process to manufacture GaAs-based CL was established only recently by N. Iwata et al. [4] R.G. Beck et al. [5] reported on self-sensing GaAs/AlGaAs CLs for low temperature SPM, J.G.E. Harris et al. [6] prepared GaAs CLs as thin as 100 nm, and A.J. Brook have fabricated on-CL micrometer-scaled Hall probe with piezoresistor [7].

Using metal organic chemical vapor deposition (MOCVD), heterostructures with triangular or rectangular quantum wells (QW) can be prepared within the CLs. Such QW can serve as active layers with two-dimensional electron gas (2DEG) which can be utilized for definition of following on-CL devices: resistors, transistors, Hall probes, etc. Realization of the on-CL devices will improve the sensitivity of the sensors and it will open new application possibilities and functionalities, thus creating the sensor of choice for chemistry, medicine and for environmental purposes.

91ASDAM 2012, The Ninth International Conference on Advanced Semiconductor Devices and Microsystems, November 11–15, 2012, Smolenice, Slovakia

2. Experimental part

The cantilevers are based on an InGaP/GaAs/InGaP heterostructure grown by MOCVD (Fig. 1). By this method, one can produce very thin (100 nm) cantilevers with desired structure. The InGaP layers are used as etch-stop ones in the releasing process [8]. The presented cantilevers are rectangular beams with length in range of 100-300 μm and width of 35-65 μm. Thickness of the whole structure mainly depends on the thickness of a GaAs layer. Figure 1. A model of designed microcantilever with GaAs layer embedded between two InGaP etch-stop layers. The mean length l and width w of microcantilever is 200 μm and 40 μm, respectively, with thickness t of 2 μm. The layers are not to scale. The basic heterostructure consists of a top InGaP etch-stop layer (30-50 nm), a GaAs layer (0.1-3 μm), a second InGaP etch-stop layer (30-50 nm) and a semi-insulating GaAs (1 0 0) substrate. All layers were lattice matched to the substrate. The final heterostructure includes also so-called transistor layers. The technology includes two main steps: front-side processing to define cantilever pattern and back-side processing to release individual cantilever chips (base seats with cantilevers) [9, 10]. Figure 1 shows the model of designed micro-CL. Initial structure was at first covered with titanium layer followed by coating with photo-resist layer (AZ 5214E) on the top side. Then, cantilever patterns were defined by photo-lithography and exposed positive resist was developed in AZ 400K developer. In the next step, uncovered parts of titanium layer were removed by HF:H2O (1:15, few seconds) solution. Other parts with resist served as masks for dry ion milling. Ar+ ions with the energy of 350-550 eV were used to etch front-side layers and to perform whole front-side definition by ion milling. Various types of the protections were used to avoid an overetching of the sandwiched GaAs layer during back-side bulk etching. These include, for example, photoresist AZ 5214E, wax, titanium or ruthenium dioxide (RuO2) layers. Microcantilevers were released via back-side bulk micromachining in two solutions. The H2SO4:H2O2:H2O mixture [11, 12] was used as a fast etchant which was followed by a finer H3PO4:H2O2:H2O (1:2:8) etchant [13, 14]. The experiments were performed with various compositions, un- or stirred, in the temperature range of 25-30°C. The etching rate of the fast mixture was about 7 μm.m-1 (1:8:1, stirred) and of the slow mixture about 1.6 μm.m-1. Resulting shapes of chip edges strongly depended on the orientation of the pattern on the wafer. Second part of this work deals with the fabrication of FET transistors by electron beam lithography (EBL). Three EBL steps are required for defining individual parts of transistor. The process begins by shallow ion milling (~100 nm) across upper layers to define mesa structures. Usually, a Ti layer was used as a mask for such etching and standard lift-off process was performed. In second step, AuNiGe contacts were evaporated and thermally annealed (450°C, 30s) to connect with electron gas channel. The channel of FET transistor is formed by 2DEG and defined by mesa and source/drain contacts. The length of channel in our case was 5 μm or 8 μm. Third, leads, pads and gate 30 μm long and 2 μm wide with an extreme small capacitance were defined. To form Ohmic contacts, Au, Pt and Ti were thermally deposited (Fig. 3(b)). In addition to main gate contact, an adjustable gate can be deposited to set initial characteristics of the transistor. In final step, gate contact will be equipped with probing tip deposited by focused ion beam.

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13. Results and discussion

The fabrication of the cantilevers benefited greatly from the use of InGaP etch-stop layers, but the problem of the overetching of the embedded GaAs layer occurred. By using scanning electron microscope (SEM), fabricated cantilevers were observed and their appearance was investigated. Figure 2 shows well-shaped free-standing cantilevers which survived transport from liquid to gas environment – the transport is also challenge for the technology.

Figure 2. SEM micrographs of free-standing microcantilevers (a) and a detail of overetched cantilever edge (b). Chips with cantilevers were cut out in the shape of standard AFM holders. The resonant frequency of some well-shaped cantilevers was measured using an NT-MDT scanning probe microscope (SPM) NTEGRA using a standard AFM procedure, where resonant frequency of the cantilever is found automatically by the system. The functionality of prepared transistors was evaluated and I-V characteristics were measured by three-point method (Fig. 3(c)). From drain characteristics it is obvious that transistor opens when gate voltage increases from -1V and current flowing through the transistor was 90 μA and 110 μA for VGS=1 V and VGS=2 V, respectively. Measurements were performed at room temperature.

Figure 3. (a) Sketch of microcantilever with integrated FET transistor. (b) Scanning electron micrograph of created transistor with floating gate and 2DEG channel. Dashed line represents cantilever contour. (c) Drain characteristics for the FET for the gate-source voltages indicated.

20 μm

(b)

(a)

Source

Drain

Adjustable gate

FIB tip

2DEG FET channel (c)

(a) (b)

1μm 100μm

93ASDAM 2012, The Ninth International Conference on Advanced Semiconductor Devices and Microsystems, November 11–15, 2012, Smolenice, Slovakia

Figure 3(a) shows sketch of the FET transistor situated at the free end of the cantilever. Such arrangement, utilizing free-stranding cantilever, can be used for observation of local electrostatic charges at the sample surface. Probing tip is the nearest point to the sample surface and represents one end of the floating gate. When the tip is charged by sample surface potential, the channel side of the gate will be charged oppositely and will influence the source-drain current through the transistor. High sensitivity is achieved due to extremely small capacitance of the gate. 4. Conclusion

We have presented the fabrication of the micro-CL based on InGaP/GaAs/AlGaAs heterostructure grown by MOCVD. The system contains InGaP layers which are resistant to the bulk etching. This results in a precise definition of the CL thickness. We have also evaluated etching methods in the front-side micromachining and etching systems in back-side micromachining. In CL definition ion milling can be used for upper layers etching followed by deeper RIE etching. Chip releasing can be accomplished through a combination of fast and slow etchants. Resulting shape of chips mainly depends on etching solution concentrations and orientation of pattern to wafer flats. FET transistors were prepared by three-step EBL process. Drain characteristics of the transistors were measured at room temperature. Next step of this work is the integration of sensing and detection elements directly on the free-standing CL. The approach with 2DEG transistor channel and micrometer-sized CL can be suitable for low temperature sensing applications. Acknowledgement

This work has been supported by the Research & Development Operational Program funded by the ERDF, “HD Video”, ITMS code 26240120043 (0.8), by “CENTE I”, ITMS code 26240120011 (0.1), and by VEGA project 2/0081/09 (0.1). References

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