The Role of Impedance Control in Early Detection of Interconnect Degradation Using Time Domain Reflectometry

Michael H. Azarian and Frank C. Schneider Center for Advanced Life Cycle Engineering (CALCE)

University of Maryland College Park, MD 20742, USA

Phone: +1-301-405-7555, FAX: +1-301-314-9269

Abstract

A study was performed to investigate the feasibility of using impedance monitoring for early detection of interconnect degradation in circuits with poorly controlled impedance. The objective of this effort is to address one of the critical uncertainties affecting the implementation of interconnect monitoring in practical electronic products, including those not specifically designed for high frequencies. Time domain reflectometry (TDR) was used to monitor circuits on two different substrates, Rogers 4003 and FR4, during shear testing of solder joints. The test boards had a variety of circuit designs and ground configurations. It was found that early stages of solder joint degradation could be detected even on the circuits with poor impedance control, provided the initial healthy state of the test circuit was used as the reference condition during the calibration of the TDR instrument. This study thus opens the door to application of TDR to a wide variety of electronic products, including those without a dedicated ground plane, for interconnect monitoring.

Introduction and Motivation

The interconnects in an electronic circuit are usually intended to have as little influence as possible on the electrical characteristics of the signals being transmitted from one device to another. Once a circuit is constructed and enters use in the field, it is expected that the characteristics of the interconnects will remain virtually unchanged for the life of the product. Nonetheless, if the product's end-of-life is caused by failure of an interconnect, awareness of the transition of that interconnect from a healthy state to an unhealthy state can be of great value to both the end user and whoever is responsible for its sustainment. The ability to detect interconnect degradation in a fielded electronic product can significantly reduce the risks associated with adoption of new materials, processes, or packaging technologies; the uncertainties surrounding actual usage conditions; the likelihood of unanticipated failure in safety or mission critical applications; and the costs associated with the product's operation and maintenance.

Most of the failure mechanisms associated with interconnects involve a process of damage accumulation over time that provides an opportunity for early detection of degradation. For example, corrosion of wire bonds or metallization, fracture of solder joints or circuit traces, or pad cratering on circuit boards all entail the initiation of damage, typically near a peripheral surface, followed by an increasing severity of degradation until the interconnect no longer performs its intended electrical function. Fortunately, this sequence of events also provides a convenient means for

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detecting and tracking the degradation process in real time, prior to failure. The structural and material changes described above lead to changes in interconnect impedance, and since damage tends to initiate at a surface, the impedance is affected during the early stages of degradation due to the skin effect. Successful use of impedance monitoring for early detection of interconnect degradation has been reported in a number of prior publications [1-4], in which time domain reflectometry (TDR) was performed on simple, impedance controlled test circuits designed for use at frequencies up to at least 10 GHz.

This investigation concerns one of the key issues affecting the applicability of the impedance monitoring approach to actual electronic products. The successful use of TDR or other high frequency impedance monitoring methods for early detection of interconnect degradation depends on several considerations associated with the product design: 1. A selection must be made of the circuits which are to be monitored. Since it is generally impractical to monitor all possible interconnects in a complex circuit, preliminary testing or reliability modeling should be used to identify one or more critical interconnects, based on their probability of failure or on their criticality to the operation of the product. 2. A stable interface is needed between the test circuit and the test equipment. This could consist of a connector, to which a cable can be attached either permanently or from time to time between the circuit and external equipment; it could consist of test pads for probing the circuit; or it could consist of a permanent connection to a dedicated monitoring circuit or device that could be designed into the product, co-located on the same printed circuit board or on another board nearby. 3. The monitoring circuit and activity should not have an adverse effect on the operation or reliability of the product. This requirement can be satisfied through appropriate timing of the monitoring process, or by connecting external test equipment only during a maintenance mode of operation, or by control of signal frequencies and amplitudes, such as by multiplexing, in order to avoid interaction with normal electrical functions of the circuit. 4. The circuit must be suitable for monitoring using high frequencies, allowing detection of small changes in impedance, in the range of 1 a to 100 mOhms. Does this last requirement necessarily limit the application of impedance monitoring to impedance controlled circuit boards with relatively uniform transmission lines between the interconnect of interest and the test equipment? How complex can the circuit be and still provide sensitivity to interconnect degradation prior to loss of continuity? These are the questions to which the present study is directed.

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Experimental Set-up

To investigate the importance of impedance control for early detection of interconnect degradation, three groups of printed circuit boards were designed, each having a similar set of five microstrip line circuits of varying complexity and physical layout. Different levels of impedance control were achieved between the three groups of boards through differences in the substrate dielectric material or the design of the return path. The boards were designed so that 1206 size surface mount components could be soldered to the boards, and mechanical shear could subsequently be applied to some of these components in order to induce degradation of the solder joints.

The layout of the top side of the boards is shown in Figure 1. Both the top and bottom sides of each group of boards were coated with solder mask except where the pads needed to be exposed, in which case they were finished with e1ectroless nickel/immersion gold. The boards were constructed using two different substrates: two groups were made using FR4 and the third was made using Rogers 4003 (R04003). The R04003 boards and one of the two groups of FR4 boards were designed for controlled 50 Ohm impedance, employing dimensional control and a continuous ground (return) plane on the bottom of the board to achieve this goal. The far end of each circuit was terminated with a 49.9 Ohm resistor, which was connected to the ground plane through a plated via.

Figure 1. Image of top surface of FR4 board with

ground plane.

The other group of FR4 boards was laid out identically to the first group of FR4 boards with the exception of the ground plane. Instead, the vias at the end of each circuit were connected to a ground trace which ran along the periphery of the board. It passed directly beneath the first and last of the 5 circuits, and was of equal width to the top traces. Consequently, the return path for the second, third and fourth circuits in the middle of those boards was physically distant from the microstrip line.

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The five circuits on each board were designed as follows (see also Figure 2):

Circuit 1: straight trace leading directly to the termination resistor. (On the FR4 boards with no ground plane this circuit had a ground trace directly below it.)

Circuit 2: straight trace with a low pass filter. (On the FR4 boards with no ground plane this circuit had no ground trace directly below it.) This circuit had the least amount of impedance variation of the circuits containing a test component.

Circuit 3: straight trace with a region of expanded width and a low pass filter. (On the FR4 boards with no ground plane this circuit had no ground trace directly below it.)

Circuit 4: trace with a serpentine and a low pass filter. (On the FR4 boards with no ground plane this circuit had no ground trace directly below it.)

Circuit 5: trace with a trifurcation, in which components could be soldered along any branch, or the middle branch could be left open or shorted, followed by a low pass filter. (On the FR4 boards with no ground plane this circuit had a ground trace directly below it following the center branch of the trifurcation.)

Termination Resistors �

1 ____________ ��--� ... . ';.R.' _.

Low Pass Filters _____ LP, .............. ---.. TR2 2

3

4, I I

LP5

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LP3 TRoI ... -- .-�

/ I

Vias LP4 TR�

--... t.--- .. _-_ ... _-. lP7 5-E Copper trace Figure 2. Schematic of the test circuits.

In order to generate interconnect degradation within a short period of time, shear stress was applied to the side of the low pass filter using a Dage 2400 Tester. The probe used to apply the stress was electrically insulated using polyimide tape, to avoid causing electrical interference with the TDR measurements. The stress on the filter was gradually increased over time, which eventually caused its solder joints to crack. If the stress was allowed to increase further, the damage to the solder joints continued until the component was dislodged from the board.

To perform the shear tests, the boards were clamped onto a bracket which was fixed to the stage of the shear tester. The test sequence began with the lowering of the shear probe to the surface of the printed circuit board, at a small distance from the side of the component. After contacting the board

surface, the probe was lifted 50 J.lm off the surface and slowly displaced in a lateral direction towards the filter. Upon contact with the component, displacement continued at a constant velocity of 0.1 J.lm/sec, causing the stress on the component to gradually increase. This continued until the test was either manually stopped or automatically interrupted because the tester detected a sudden drop in the mechanical resistance to the displacement of the probe, indicating that the component had been dislodged from the board. At the end of each test the peak shear force was displayed.

TDR measurements were performed using an Agilent Technologies E8364A Vector Network Analyzer (VNA) , using an option to convert frequency domain measurements of the Sll scattering parameter to the time domain. Measurements were made in bandpass mode over the frequency range of 45 MHz to 3 GHz. Since the low pass filter had a cutoff frequency of 6.7 GHz, the component itself had essentially no influence on the measurements. TDR monitoring was automated using instrument control software so that results could be captured during the shear tests approximately every 20 seconds.

The initial design of the boards incorporated pads for measurement using a TDR probe. It was found that this arrangement was not suitable for use in real time with the shear tester, because of geometric constraints as well as the inability to maintain a stable contact with the test pads using a probe. For this reason, the boards were connectorized by cutting one end of the boards through the signal pad, and soldering female connectors to the edge of the boards such that signal and ground were appropriately connected on the top and bottom of the boards respectively.

One of the procedural steps which was found to play an important role in these experiments was the calibration of the VNA. Typically, one must perform an open, short, and load calibration in order to obtain an accurate measure of the TDR response of the device under test. It was found that the approach used for the load calibration could be modified to compensate for many of the deficiencies inherent to the circuits which were designed with poor impedance control.

Results and Discussion

A comparison is presented in Figure 3 of the TDR response of the first circuit on each of the three boards, without application of any stress. These results were generated by using circuit 1 of the Rogers 4003 board for the load calibration of the VNA, and then performing the measurements on the other boards, such that the circuit on the Rogers boards served as a reference for the other boards. This graph readily illustrates two findings. First, it shows that the FR4 substrate with the ground plane provides a response which is virtually indistinguishable from the R04003 substrate. Thus, over this frequency range it appears that FR4 does not hinder the acquisition of a good TDR response. Secondly, although there is clearly a reflection from the FR4 circuit with the ground trace, the magnitude of that reflection is less than 0.05, which is small enough to pose little hindrance to TDR monitoring. This suggests that if one wished to perform monitoring on a circuit board which did not contain a dedicated ground plane, the incorporation of a parallel ground trace on an adjacent layer could help to obtain

the electrical characteristics needed to produce an acceptable response.

In contrast, when the other circuits of the FR4 board without a ground plane were characterized, reflections of approximately 0.6 were observed for the circuits without a ground trace directly under them (i.e., circuits 2, 3, and 4), even when circuit 1 of the same board was used for the load calibration. This clearly shows that monitoring of circuits without any form of impedance control is likely to be problematic when using traditional calibration methods.

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W O�,---------------------------------3 OW�-------------------------------

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� 04U�_F_R�4 �gr _O _un _d_t_ra_ce --------------------­<=

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--------�Oc���--��=-----------------------3 -2 -1 o 4 6

time I ns

Figure 3. TDR response of circuit 1 on each of the three

boards prior to the application of stress.

To address the challenges of applying TDR monitoring to such circuit boards, an alternative calibration approach was adopted. A series of measurements was performed in which the load calibration was performed on the same circuit which was to be tested, using the initial healthy state of the circuit as a reference against which changes in impedance could be evaluated. One such case is illustrated in Figure 4, which shows a series of TDR responses obtained at various intervals during a shear test on circuit 3 of the R04003 board. In this case, the initial response of the circuit was flat, since the healthy state of the same circuit was used for the calibration. All changes during the test were easily measured against that low background. This test was terminated manually after the sixth acquisition (labeled t=6 in the graph) when the reflection coefficient reached O.l, which is much less than the response of a failed solder joint (those values are typically greater than 0.7). Under these circumstances it was possible to detect changes in reflection coefficient as small as 0.01-0.02.

'" o u c

.9 U '" 't '"

9.5

9A

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1\ L� -........ 4

time Ins

-t= l

-1=2 - 1=3

-1=4 -t=5

-1=5

-t=7

10 -1=8

Figure 4. TDR responses obtained at various intervals

during a shear test on circuit 3 of the R04003 board.

This strategy proved to be highly successful even for monitoring circuits on the FR4 board without a ground plane. For example, Figure 5 shows the peak reflection coefficient

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vs. measurement number (which corresponds to shear test duration) for circuit 2 on one of these boards. This graph demonstrates how this calibration approach reduces the initial reflection coefficient so dramatically that changes of a few hundredths are readily detectable.

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u

-= U.3 � 0.23 � 0.2 .g 0.15 � 0.1 � 0.05 a:: 0

o 4

measurement

/ /

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6 g

Figure 5. Peak reflection coefficients during a shear

test on circnit 2 of FR4 board without ground plane.

A similar test was performed on circuit 3 of an FR4 board without a ground plane. That test was terminated when the reflection coefficient reached 0.08. Fig. 6 shows an optical micrograph of a cross-section of that filter and its associated solder joint, with a partial crack visible in the image.

. --...

\ ,

.... .,a....... -

Figure 6. Cross-section of solder joint after mannal

termination of shear test of circuit 3 of an FR4 board

without a ground plane.

These results clearly demonstrate that early detection of interconnect degradation using TDR is feasible on a wide variety of electronic circuits, including those with little or no provision for the transmission of signals at high frequency. The key to successful monitoring of circuits with poor impedance control is the use of the test circuit in its initial healthy state as a reference condition. In this study this was accomplished through the load calibration process.

Conclusions

The fundamental difference between measurements made for the purpose of characterizing an interconnect and those made for detecting degradation is that health monitoring does not require an absolute measurement of impedance or scattering parameters. Given that an interconnect is healthy in the initial state, one requires only an indication that there has been a change in its electrical characteristics. With the added benefit that TDR provides of localizing the change, one can

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establish that the altered impedance is associated with an interconnection and not some other element of the circuit. This is a distinct advantage when monitoring circuits which are not optimized for high frequency. Whereas the usual procedure for load calibration entails the use of a known impedance, using the test circuit in its initial condition for the load calibration of the TDR provides sensitivity to small changes in impedance even in a circuit which lacks a ground plane. Using this approach, the results reported herein show that one can detect changes in impedance prior to the loss of continuity through a solder joint on a circuit board without impedance control, despite the use of signals extending up to 3 GRz.

This study has demonstrated that detection of interconnect degradation using TDR monitoring is feasible on circuits constructed using FR4 substrates. Design for impedance control significantly improves TDR resolution and sensitivity. In the absence of a dedicated ground plane, dimensional control combined with a localized ground trace improves the TDR response. Nonetheless, changes in TDR reflection coefficient of as little as 0.02 were detected even on circuits on FR4 boards without a ground trace. These results help to establish the design requirements for interconnect health monitoring on a wide array of practical electronic products.

Acknowledgments

The authors would like to thank Prof. Flavio Canavero of the Politecnico di Torino for many helpful discussions and suggestions. They gratefully acknowledge the contributions of Mr. Felix Bussemer to the design and initial testing of the circuit boards. They would also like to thank the over 100 companies and organizations that annually support the research of the Center for Advanced Life Cycle Engineering (CALCE) at the University of Maryland, including the members of the CALCE Electronics Products and Systems Consortium, for their support of this work.

References

[1] Kwon, D., Azarian, M. R., and Pecht, M., "Early Detection of Interconnect Degradation by Continuous Monitoring of RF Impedance," IEEE Transactions on Device and Materials Reliability, Vol. 9, No. 2 (2009), pp. 296-304.

[2] Kwon, D., Azarian, M. H., and Pecht, M., "Effect of Solder Joint Degradation on RF Impedance," 12th IEEE Workshop on Signal Propagation of Interconnects, Avignon, France, May 2008.

[3] Kwon, D., Azarian, M. R., and Pecht, M., "Identification of Interconnect Failure Mechanisms Using RF Impedance Analysis," 13th IEEE Workshop on Signal Propagation on

Interconnects, Strasbourg, France, May 2009.

[4] Azarian, M. R., Kwon, D., and Pecht, M., "Use of the Skin Effect for Detection of Interconnect Degradation," IMAPS 42nd Internat. Symp. on Microelectronics, San Jose, CA, Nov. 2009.