A New Low-Stress High Efficiency Buck Converter

Aurel Cireşan, Dan Lascu Applied Electronics Department Politehnica University Timişoara

Timişoara, Romania aurel.ciresan@etc.upt.ro, dan.lascu@etc.upt.ro

Abstract—A new step-down converter exhibiting low voltage stress across semiconductor devices, low inductor current stress and high efficiency is presented. Operation in continuous conduction mode (CCM) is analyzed in detail and main design equations are provided. The theoretical considerations were confirmed both by simulation and by experimental results.

Keywords: Buck converter, resonant stage, static conversion ratio, zero current switching, efficiency

I. INTRODUCTION In a classical buck converter semiconductor voltage stresses

are imposed by the input voltage. This could be a drawback in high voltage applications, requiring expensive semiconductor devices. High voltage transistors exhibit higher on resistance, thus leading to higher conduction losses. Moreover, inductor copper losses depend also on the dc inductor current and in a classical buck topology this current equals the output current, being quite significant. On the other side, the switching losses are also increased because of the high voltages under which hard-switching is performed, thus decreasing efficiency and imposing upper limits to the switching frequency. From the control point of view, in a classical buck converter, when the output voltage is only slightly lower than the input voltage, the required duty cycle will be very high, imposing transistor off times to be comparable to the transistor switching times and therefore making the control difficult.

Single transistor two diodes dc/dc converters could be a solution to the last mentioned drawback and in [1] Zhou introduces such a class of converters, but they still suffer from the voltage stresses and losses points of view. In [2] some families of two-transistor topologies that significantly outperform classical counterparts in terms of switch and inductor stresses are generated. However the presence of two active devices complicates their control. In [3] Ćuk proposes a new boost topology starting from a classical converter and introducing three devices: an internal capacitor, a resonant inductor and an additional diode for limiting the resonant interval to only first half cycle.

The present paper presents a new buck converter solving all the above mentioned drawbacks. The converter is derived from one of the single transistor two diodes buck representatives proposed by Zhou [1], that is modified using the same technique prof. Ćuk used for the obtaining his new boost converter [3]. Converter topology is analyzed in section II, simulation results are presented in section III, while

experimental verifications are performed in section IV in order to validate the theoretical and simulation results.

II. OPERATION AND MAIN EQUATIONS OF THE NEW BUCK TOPOLOGY

The proposed new buck topology is depicted in Fig. 1, where the associated voltages and currents are also defined.

Unless something special is mentioned, dc components will be denoted by capitals. Transistor S duty cycle will be denoted by D, switching period by Ts and switching frequency by fs. Active switch S, diode D2, inductor L and capacitor Co are inherited from the classical buck converter. CCM operation is assumed, that is inductor current iL is always positive and consequently diode D2 will never cease to conduct during transistor S off time. As the dc voltage across any inductor is zero in steady-state, evaluating the dc voltage across capacitor C in the loop consisting of C-Lr-D1-L, it immediately follows that

1DC VV = and because obviously 01

>DV , it follows that

01

>CV . During the first topological state when transistor S in on and diode D2 is off, a series resonant circuit comprising of C, Lr, D1, Co and Vg, occurs. The resonant period is

erCLπT 20 = , where o

oe CC

CCC

+= . Inductor Lr current

will exhibit a sinusoidal waveform. The resonant stage lasts only half of the resonant period due to diode D1 in series with the resonant inductor Lr. Three operation modes are possible [3], according to the transistor on-time relative to half of the

resonant period erCLπT

=20 . Although the mode with

+_

-v+

v

Lr

+ vCo Co R

D

LS

-

vo

+

iC0

iL

i

iC

i o

D 2

C

+ V -

Vg v

D2

+

+ -

v L

-

-

LrL

D1v 1

S

C

r

+

-

-

+

Figure 1. The proposed new buck topology.

A

ig

978-1-4673-1176-2/12/$31.00 ©2012 IEEE

transistor on time higher than half of the resonant period also leads to low switching losses, proper operation requires that transistor on time DTs to be equal to half of the resonant period:

ers CLπDT = (1)

As transistor on-time is imposed by (1), the output voltage is adjusted modifying the switching frequency.

The main dc relationships can be derived in the typical way [4], imposing volt-second balance across the inductors and charge balance through the capacitors. Capacitors C and Co are assumed to be high enough such that in writing the volt-second balance equations capacitor voltage ripple to be negligible and capacitor voltages to be approximated by their dc values. Thus volt-second balance across L results in:

( ) ( )( ) 01 =−−+− CoCCog VVDVVD (2)

while volt-second balance across Lr leads to:

( ) ( ) 001 =−+−+− DVVVD CogC (3)

Solving for CoV and CV from (2) and (3) in terms of Vg and Vo and taking into account that Coo VV = , we obtain:

go VD

V−

=2

1 (4)

gC VDDV

−−=

21 (5)

Form (4) the static conversion ratio g

oVV

M = is:

DM

−=

21 (6)

Note that from (3) and with Coo VV = , the dc voltage across C can be expresses as:

ogC VVV −= (7)

As 10 ≤≤ D , examining (6) the first remark is that

121 ≤≤ M , that is only output voltages higher that half of the

input voltage are possible. The next remark is that it can be easily seen that transistor and diode D2 voltage stress equals

Cg VV − . Making use of (7) it immediately follows that:

oDS VVV == maxmax 2 (8)

As it is known, in a classical buck converter transistor and diode voltage stress equals Vg. Because in a buck always

go VV < , from (8) it results that semiconductor devices are subjected to lower stresses compared to the classical topology. This leads to both lower conduction losses as lower voltage transistors exhibit lower on resistance and lower switching losses because the semiconductor devices are switched under lower off voltages. Consequently, higher efficiency and higher

switching frequencies and can be achieved. The main converter waveforms are shown in Fig. 2. It is important to note that diode D1 is turned on and turned off at zero current (zero current switching, ZCS) because of the resonant inductor in series with it. This is important especially for the turn off switching of D1, eliminating the substantial turn off losses determined by high reverse currents and long recovery time. Because all energy stored in Lr is released before turn off, there

will be no turn off losses associated with this diode. Applying Kirchhoff current law (KCL) to node A, taking into account that capacitor C dc current value is zero and assuming 100% efficiency, it results that

ogL MIII == (9)

sinus

sinus

(1 - D)·TS = TOFF

cosine linear vC0

IL-(VC0/R)

iC0

Ir

iLr

VC

cosine ΔVC linear vC

iC

-IL

ILr

vS

I

iL

TS D·TS = TON

vg - vo

t vg - 2v0

t

t

t

t

t

t

Figure 2. Main waveforms of the proposed converter.

vD1

TS(1 - D)·TS = TOFF

D·TS = TON

vsw v0

v0

v0

vD2t

t

t

As 1<M from (9) it follows that oL II < . On the other side, in a classical buck oL II = so in the proposed converter dc inductor current is lower that in the classical counterpart. This is remarkable as inductor copper losses will be lower and

inductor design much easier.

III. SIMULATION RESULTS The new buck converter was first simulated using the

Caspoc package [5]. For a fair comparison, converter parameters were the same as those that will later be used in the experiment:

uFCFμCHμLmHLVV org 6.6;2.2;6.11;04.1;30 =====

Load resistor was Ω8.37=R , while the switching frequency kHzf s 003.21= . The duty cycle estimated from (1) resulted

in 289.0=D . In Fig. 3 the simulated output voltage, capacitor C voltage, resonant inductor, active switch current and transistor voltage are presented. It can be seen that the output dc voltage equals 17.5V, as predicted from equation (6). Also the resonant part in the capacitor C voltage can be observed and its shape coincides with the resonant inductor current, as theoretically anticipated. Transistor voltage stress, excepting ripple, equals 17.5 V, as predicted by (8), while dc capacitor C voltage is 12.5V, as (7) predicts.

IV. EXPERIMENTAL RESULTS The proposed converter was breadboarded. The passive

component values and the control parameters were exactly the same as those used in the simulation in section III. Of course, semiconductor devices are nonideal, exhibiting mainly conduction losses. The transistor used was a IRF 520 HEXFET Power MOSFET, while the two diodes were PBYR10100 Schottky diodes.

Experimental capacitor C voltage and resonant inductor current are illustrated in Fig. 4. The pair consisting of capacitor C voltage and inductor L current is shown in Fig. 5. It can be seen that inductor L current is the same approximately piecewise linear shape, like in the classical topology. Resonant inductor current shows that resonance occurs during transistor on time lasting exactly half of the resonant period. Capacitor C

voltage together with transistor current are depicted in Fig. 6. It can be remarked that transistor current is the sum of the

Figure 4. Capacitor C voltage (up) and resonant inductor Lr current (down).

0

2

4

6

8

10

12

14

16

18

20

19.965m 19.980m 19.995m 20.010m 20.025m 20.040m 20.055m 20.070m 20.085m 20.100mTime(s)

_3 V[_4]

0

200m

400m

600m

800m

1

1.200

1.400

1.600

1.800

2

19.965m 19.980m 19.995m 20.010m 20.025m 20.040m 20.055m 20.070m 20.085m 20.100mTime(s)

I[LR]

0

200m

400m

600m

800m

1

1.200

1.400

1.600

1.800

2

19.965m 19.980m 19.995m 20.010m 20.025m 20.040m 20.055m 20.070m 20.085m 20.100mTime(s)

I[DMOSFET1]

0

5

10

15

20

19.965m 19.980m 19.995m 20.010m 20.025m 20.040m 20.055m 20.070m 20.085m 20.100mTime(s)

_7

Figure 3. Simulated output voltage, capacitor C voltage, resonant inductor current, transistor current and transistor voltage (this up to

down order) .

inductor L current and the resonant current, as expected. In Fig. 7 transistor voltage and resonant inductor current are presented.

Similarities to simulated waveforms are evident and the fact that transistor voltage stress is equal to the output voltage is confirmed. Fig. 8 shows capacitor C voltage, diode D2 voltage and resonant inductor current. It is confirmed that diode D2 voltage stress is equal to the output voltage. Finally converter

efficiency was measured and an excellent value of 96.02% was obtained, thus confirming the theoretical expectations.

V. CONCLUSIONS A new step-down converter is proposed. At the expense of

only three additional cheap components high efficiency, lower semiconductor voltage stresses and lower inductor current stress can be achieved. It is interesting to note that these three additional components are exactly the same that are traditionally added to obtain a quasiresonant (QRC) converter from a PWM one. Simulated waveforms and experimental results confirmed the theoretical considerations and the feasibility of the converter. Future work will focus on obtaining high performance new boost and buck-boost type topologies using the same procedure.

ACKNOWLEDGMENT This work was partially supported by the strategic grant

POSDRU 107/1.5/S/77265 (2010) of the Ministry of Labour, Family and Social Protection, Romania, co-financed by the European Social Fund – Investing in people.

REFERENCES [1] D. Zhou, “Synthesis of PWM Dc-to-Dc Power Converters”, Ph.D.

thesis, California Institute of Technology, October 1995. [2] J. Chen, D. Maksimović, and R. Erickson, “Buck-Boost PWM

converters having two independently controlled switches,” in Proc. IEEE Power Electron. Specialists Conf., 2001, pp. 736–741.

[3] S. Ćuk et al., “Voltage step-up switching dc-to-dc converter”, United States patent, Patent No. US 7,778,046 B1, August 17, 2010.

[4] R. W. Erickson and D. Maksimovic, “Fundamentals of Power Electronics”, 2nd ed., Chapman and Hall, 2001.

[5] Caspoc, user manual, Simulation Research website [Online], Available: http://www.simulation-research.com/sr/sr.php

[6] S. Cuk and R.D. Middlebrook, “Advances in Switched-Mode Power Conversion”, vol. 1, II, and III, TESLAco 1981 and 1983.

[7] P. Lee, Y. Lee, D. Cheng, and X. Liu, “Steady-State Analysis of an Interleaved Boost Converter with Coupled Inductors,” IEEE Trans. on Industrial Electronics, Vol. 47, No. 4, August 2000, pp. 787-795.

Figure 6. Capacitor C voltage (up) and transistor current (down).

Figure 7. Transistor voltage (up) and resonant inductor current (down).

Figure 8. Capacitor C voltage, diode D2 voltage and resonant inductor current (this up to down order).

Figure 5. Capacitor C voltage (up) and inductor L current (down).