EUV Lithography introduction at ChipmakersChristian Wagnera, Jose Bacelara, Noreen Harneda, Erik Loopstraa, Stef Hendriksa, Ivo de Jonga, Peter Kuerzb, Leon Levasiera, Mark van de

Kerkhofa, Martin Lowischb, Hans Meilinga, David Ockwella, Rudy Peetersa, Eelco van Settena, Judon Stoeldraijera Stuart Younga , John Zimmermana, Ron Koola, Alek Chenc

aASML Netherlands B.V., De Run 6501, 5504 DR Veldhoven, The Netherlands bCarl Zeiss SMT AG, 73446 Oberkochen, Germany

cASML Technology Development Center Asia, ASML Taiwan Ltd, Hwa-ya Technology Park, GueiShan Township, Taoyuan County, Taiwan

ABSTRACT

With the 1st NXE:3100, 0.25NA and 0.8� conventional illumination, being operational at a Semiconductor Manufacturer, we enter the next phase in EUVL implementation. Since 2006 process and early device verification has been done using the two Alpha Demo Tools (ADT’s) located at Leuven, Belgium at IMEC and Albany, New York, USA. Now process integration has started at actual Chipmakers sites. This is a major step for the development and implementation of EUVL. The focus is now on the integration of EUVL exposure tools, along with the rest of lithographic infrastructure such as mask, resist, and computational litho tools, into a manufacturing flow, preparing high volume EUVL manufacturing expected to start in late 2012. Fore high volume manufacturing with EUV, we will update on the design status of the NXE:3300B being introduced in 2012 with a productivity target of 125wph.. Featuring a 0.33NA lens and off-axis illumination at full transmission, a half pitch resolution from 22nm to 16nm can be supported.

1. INTRODUCTION AND ROADMAP

The first NXE:3100 is operational in the field, and thus a new era of lithography has started, transferring the learning from the 0.25NA tool (ADT) at IMEC and Albany [1] to the semiconductor factory.

Starting with a 0.25NA 1st generation, a 2nd generation with 0.33NA and loss less off axis illumination (OAI) [2], will enable Chip manufacturing down to 16nm half-pitch (HP) resolution. Source power roadmaps [4, 5, 6] are aligned to support high productivity, making EUVL a cost effective solution for the industry. A detailed description of the NXE roadmap can be found in [3]. Table 1 summarizes the roadmap and tool requirements, and sets the stage for the performance validation of the NXE:3100.

The main body of the paper will review the performance of the NXE:3100, followed by an outlook and status description of the NXE:3300. Further resolution enhancements using either low-k1 optics or higher NA will be described in the last Section, which is followed by a summary.

2. Performance Validation of the NXE:3100 2.1 Optical and Imaging performance of NXE:3100 All optical systems for the 6 NXE:3100’s have been delivered

and are meeting the specifications, shown in Figure 1. The full 26mm imaging field flare data is more than 3x reduction in both absolute flare level and variation across the field, compared to the ADT lens performance. A computational litho tool, with appropriate EUVL imaging model, is needed to compensate for the additional processing effects, three examples shown on the right in Figure 2, the validation data from ADT shown on the left in which, w/o OPC some features are barely opened, after OPC all unique features in the design, have a full wafer and intra field CDU < 3.8nm 3� (7.5% of target CD) for both H and V lay out.

Figure 3 shows intrafield CDU of <1.4nm, being well within specification. Exploring minimum resolution of NXE:3100, Figure 4 shows the dense lines 20nm have been obtained with good LER,

more results can be found in [7], metal layers for the 16nm Logic node (32nm hp) using an initial OPC model, and the NAND 20nm staggered contact hole layers have been resolved. In summary the NXE:3100 imaging performance has shown to be meeting its requirements.

2.2 Overlay and Focus Performance Figure 5 shows the Overlay capability of the NXE:3100. All data

discussed assume 44 field of 26mmx32mm size. The left picture shows stage accuracy <1.6nm. The mid picture dedicated chuck overlay of <2.1nm, meeting the specification of 4nm. The right picture is matched machine overlay, to a dry XT:1400, of <8.4nm. The focus performance for both chuck depicted in Figure 6 is below 30nm and in specification.

2.3 Source Performance, Productivity and Reliability With respect to productivity, source power is on the critical path

to volume production. While for the LPP type source, collector contamination and beam steering limit the implementation speed of power improvement, for DPP sources the speed is limited by EMI and thermal issues. These issues are closely linked to the respective source’s operating principle. As a result for both sources the productivity is today limited to ~ 5wph shown in Figure 7, with upgrade plans towards 60 wph in place towards the end of 2011. For a detailed description of the source progress and issues we refer to [8,9].

Thus we expect both LPP and DPP sources will be operating at customer sites of the NXE:3100 allowing for good alignment with the NXE platform also in the context of the NXE:3300.

3 Higher NA and higher Productivity - NXE:3300 Looking to high volume manufacturing with EUV we will

introduce the NXE:3300B in 2012 with a productivity target of 125wph at 15 mJ/cm2 dose. Featuring a 0.33NA lens and OAI at full transmission, a HP resolution from 22nm down to 18 or even 16nm could be supported, a detailed description of the NXE:3300 system layout can be found in [2]. A full resist simulations, using a model calibrated to one of today’s resist systems, was performed to show the process margin for a M1 layer for a 0.0264 �m2 SRAM bit cell, a cell size consistent to logic 10 nm node design rule. As shown in Figure 8, a depth of focus > 100 nm at 5% exposure latitude was possible.

Since many applications presently use the full field layout of 96 fields of 26x32mm, the productivity would be significant higher than that for the ATP layout of 125 fields (16x32mm). The system design was made in such a way that handling and scanning steps do not limit productivity when full field layouts are used, down to a dose of 10 mJ/cm2 and up to a productivity of 145 wph, as shown in Figure 9.

4 Summary This paper has reviewed the performance of the NXE:3100. To

date 20nm dense lines at 14mJ/cm2 have been imaged with 0.25NA using dipole illumination. Overlay performance is in line with the specification. Productivity is limited by installed source power. More effort is needed to close the gap between high power demonstration

978-1-4244-8492-8/11/$26.00 ©2011 IEEE

progress in the lab and actual power of shipped sources. The NA of the NXE:3300 has been increased to 0.33, enhancing the optics etendue by 6%, and recent data from LPP sources indicate that even today’s best configuration would allow >100wph productivity.

ACKNOWLEDGEMENTS The authors would like to emphasize that the work presented here has been a team effort, with contributions by a large number of people in various organizations, including our end users. Grateful acknowledgement is expressed to the Public Authorities of The Netherlands, Germany, Belgium and France for their outstanding support of the EAGLE and EXEPT projects, as well as the MEDEA+ and CATRENE organization

REFERENCES[1] H. Meiling et al, SPIE, 7271 (2009). [2] M. Lowisch, et al, SPIE, 7636 (2010). [3] For a summary see Proceedings of, 9th International Symposium on Extreme Ultraviolet Lithography, Kobe (2010). C. Wagner et al, SPIE, 7636 (2010).

[4] D. Brandt, et al, SPIE, 7636 (2010). [5] M. Corthout, et al, SPIE, 7636 (2010). [6] X.Y, et al, SPIE, 7636 (2010). [7] Suigen Kyoh, et al., SPIE, 7969 (2011) [8] D. Brandt et al, SPIE, 7969 (2011). [9] M. Yoshioka et al, SPIE, 7969 (2011).

Figure 1 Optical performance of all NXE:3100 optics, and flare verification in resist under 2�m lines, the squares giving the performance of the ADT, the diamonds the NXE:3100.

Figure 2 Overview of optical effects that have to be made part of OPC correction in order to achieve optimum image fidelity, shown on the left.

Figure 3 (left) Full wafer CDU for 27nm dense H lines, (mid/right) intrafield CD uniformity

Figure 4 (left) 20nm resolution champion data of NXE:3100 with 75deg dipole illumination, (mid) 32nm half pitch Metal 21 layer for the 16nm Logic node, (right) 20nm NAND staggered contact hole layer, with C/H pitch of 72nm

5 nm99.7%Fx: 1.6 nmy: 1.3 nm 5 nm

99.7%Fx: 2.1 nmy: 2.1 nm

20 nm99.7%Fx: 8.4 nmy: 6.9 nm5 nm

99.7%Fx: 1.6 nmy: 1.3 nm 5 nm

99.7%Fx: 2.1 nmy: 2.1 nm

20 nm99.7%Fx: 8.4 nmy: 6.9 nm

Figure 5 (left) <1.6nm stage accuracy, (mid) <2.1nm single chuck Overlay, (right) <8.4nm Matched machine overlay

Figure 6 <30nm focus performance of 2 chuck of the dual chuck NXE:3100.

Figure 7 LPP source power demonstration

Figure 8 Full resist simulations results of SRAM M1 layer, cell size = 0.0264 �m2, using 0.33NA and annular OAI.

50

70

90

110

130

150

170

50 100 150 200 250 300

Source power - clean photons [W]

Thro

ughp

ut [w

ph]

ATP 10 mJ/cm2ATP 15 mJ/cm2

FF 10 mJ/cm2

FF 15 mJ/cm2

Figure 9 Dependence of the productivity on source power for the NXE:3300B for various dose settings and wafer layouts. ATP denotes a 125 field layout and FF denotes a 96 field layout.

151510Resist dose [mJ/cm2]

15012560Productivity [wph]

3.0 / 4.53.5 / 5.04.5 / 7.0OV SMO/MMO [nm]

18/162227Resolution [nm]

OAI0.9� max

Conv 0.2-0.9�OAI optional

Conventional 0.8�

Illumination

0.330.330.25NA

NXE:3300CNXE:3300BNXE:3100

151510Resist dose [mJ/cm2]

15012560Productivity [wph]

3.0 / 4.53.5 / 5.04.5 / 7.0OV SMO/MMO [nm]

18/162227Resolution [nm]

OAI0.9� max

Conv 0.2-0.9�OAI optional

Conventional 0.8�

Illumination

0.330.330.25NA

NXE:3300CNXE:3300BNXE:3100

Table 1 NXE platform roadmap