A New Current Mode Logic Style with Feedback for

Digital Applications

Kirti Gupta 1, Ranjana Sridhar

2, Jaya Chaudhary

3, Neeta Pandey

4, Maneesha Gupta

5

1 Electronics and Communication Division, Delhi Technological University, New Delhi, kirtigupta_22@yahoo.com

2 Electronics and Communication Division, Delhi Technological University, New Delhi, ranjanasridhar@gmail.com

3 Electronics and Communication Division, Delhi Technological University, New Delhi, jiya.chaudhary@gmail.com

4 Electronics and Communication Division, Delhi Technological University, New Delhi, n66pandey@rediffmail.com 5 Electronics and Communication Division, NSIT, Delhi University, New Delhi, maneesha_gupta60@yahoo.co.in

Abstract—In this paper, a new logic style named as MOS

current mode logic with feedback is proposed as an alternative

to conventional MOS current mode logic for implementing

digital circuits operating at high frequencies. The proposed

circuit style employs a positive feedback that enhances the

switching speed of the circuit. The use of feedback reduces the

number of transistors needed to implement the circuit in

comparison to conventional MOS current mode logic. Different

circuits based on MOS current mode logic with feedback are

proposed and simulated in PSPICE using 0.18µm CMOS

technology parameters. Their performance comparison with

CMOS and conventional MCML circuits indicates that the

proposed circuits have lesser number of transistors with

minimum propagation delay values.

Keywords: MOS current mode logic, high speed, series gating.

I. INTRODUCTION

The recent developments in the area of digital signal

processing and optical communication have led to an increase

in high speed mixed signal integrated circuits (ICs) with

minimum power consumption. In these ICs, the switching

noise generated by the on-chip digital circuitry limits the

resolution of the analog circuits [1]. The traditional CMOS

logic style is usually not preferred in the design of high speed

mixed signal ICs as it produces large switching noise due to

the large voltage/current magnitudes and single wire

communication. Also, CMOS circuit has substantial power

consumption which increases with the operating frequency so

a different logic style is required [2]. Among the possible

topologies [3-7], one of the most successful logic styles is the

MOS Current Mode Logic (MCML). The logic style is

characterized by low switching noise generation, static power

consumption that is independent of frequency and is thus

suitable for implementing high-resolution mixed signal

integrated circuits operating at high frequencies [8].

A conventional MCML circuit consists of a pull-down

network (PDN), a constant current source (ISS) and a load

circuit. The PDN implements the logic function based on

series-gating approach [9] in two individual branches where

one of the branches realizes the function while the other one

realizes its complement. In this work, we propose a new

current mode logic style that is derived from conventional

MCML by introducing a positive feedback into the circuit to

improve its performance and may be abbreviated as MCML-

FB. Also, the introduction of the feedback reduces the

number of transistors used to realize agate in comparison with

the conventional MCML.

The paper begins with a brief introduction to conventional

MCML circuit configuration in section II. In the next section,

the MCML-FB logic style is introduced and different gates

based on MCML-FB are proposed. The proposed circuit is

implemented, simulated and the results are discussed in

section V, followed by some concluding remarks in section

VI.

II. CONVENTIONAL MCML CIRCUITS

The conventional MCML circuit consists of three main

components which include a differential PDN, a current

source and a pull-up load circuit as shown in Fig. 1. The PDN

consist of two branches such that one of the branch (f-branch)

implements the function in true and the other (fbar-branch) in

the complement form. The logic function is implemented by

following series gating approach which consists of stacking

two transistors on a single current source. The current source

determines the constant current, Iss whereas the load circuit

implemented by a resistor, RL determines the voltage swing.

MCML circuit works on the principle of current steering. If

the differential input voltage is high (low), the NMOS source-

coupled pair steers the bias current, Iss to one of the branches,

thereby generating a low (high) output voltage in the

conducting (non-conducting) branch. Based on this approach,

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the circuits of different gates such as AND/NAND, XOR3

and carry are shown in Fig. 2.

In some designs, MCML circuits are designed with active

PMOS loads instead of resistive load. Active loads have an

advantage of smaller area than passive resistances, but suffer

from deviation from linear behavior, especially at high

speeds. Moreover, active load add extra capacitance to the

total output load capacitance of the circuit and hence

increases both the rise and fall time of the circuit [10].

Figure.1. Conventional MCML circuit

Figure. 2. Different MCML gates (a) 2-input NAND, (b) 3-input XOR (c) 3-input Carry circuit.

III. PROPOSED MCML-FB LOGIC

The basic circuit of n-input MCML-FB gate can be

derived from the conventional MCML logic style by

implementing the logic function using stacked transistors

approach in one branch i.e. f-branch and introducing a

positive feedback in the other one i.e. pf-branch as shown in

Fig. 3. The positive feedback is obtained by connecting the

output of the gate to the input of the feedback transistor, Mfb.

The circuit works on the current steering principle. If the

combination of the inputs to the gate is such that the current

ISS is steered in f-branch, a low voltage level is obtained at its

output which at the same time makes transistor Mfb OFF due

to the positive feedback thus producing a high voltage level at

the output of the pf-branch. Similarly, the input combinations

for which the f-branch is OFF correspondingly makes its

output high and turns ON the transistor Mfb so that a low

voltage level is obtained at the output of the pf-branch. The

positive feedback in these circuits reduces the number of

NMOS transistor in comparison to conventional MCML

circuits which results in reduced implementation area. Also,

positive feedback significantly enhances the voltage gain

[11], thus it is expected that MCML-FB gates have reduced

transistor aspect ratios than conventional MCML, if designed

for equal voltage gain and bias current values. This reduction

in transistor aspect ratios will reduce the parasitic

capacitances and in turn reduce the delay of the gate.

Figure. 3. Basic circuit of n-input MCML-FB gate

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Figure: 4. Proposed circuits based on MCML-FB logic style (a) 2-input NAND, (b) 3-input XOR (c) 3-input Carry circuit.

Fig.4 shows the implementation of some basic gates

namely, NAND, 3-input XOR and carry in MCML-FB logic

style. The circuit of a NAND gate (Fig. 4(a)) consists of two

stacked transistors and a feedback transistor (Mfb) coupled to

the current source ISS. When both the inputs are high, the

current ISS flows through the f-branch and generates a low

voltage level at its output which is then fed back to the Mfb

transistor. A low voltage level does not switch ON the

transistor Mfb so a high voltage level is obtained at the output

of pf-branch.

The proposed circuit of the 3-input XOR gate (Fig. 4(b))

consist of three levels of transistors in the f-branch. For the

following input combinations

A, B, C = (000), (011), (101), (110)

the output of the f-branch (pf-branch) is low (high) whereas

for other combinations a high (low) level is obtained in the f-

branch (pf-branch). Similarly, the proposed carry circuit

produces a low (high) output values in the f-branch (pf-

branch) for the following input combination:

A, B, C = (011), (101), (110), (111)

IV. SIMULATION RESULTS

The proposed MCML-FB based circuits namely; NAND,

XOR and carry circuits (Fig. 4.) are simulated in PSPICE

with 0.18 µm CMOS technology parameters. Table I shows

the input parameters taken for the simulation of the proposed

MCML-FB circuits with a voltage swing of 0.4V.

TABLE I: SIMULATION ENVIRONMENT

Simulation Environment

Process corner Typical

Temperature 27 oC

Supply voltage 1.8V

Input signal rise/fall time 10% of Tclk

Bias current 90 uA

Load Resistor, RL 4.44 KΩ

Conventional CMOS and MCML (Fig. 2) based NAND,

XOR and carry circuits are also simulated to test the

effectiveness of the proposed circuit style. The propagation

delay obtained for the circuits through simulation is listed in

Table II for the three different styles. It may be observed

from the table that the reduced delay values are obtained for

all the circuits based on the proposed logic style as compared

to conventional CMOS and MCML circuits. Hence, the

proposed logic increases the switching speed of the gates. It

can also be noted from the circuit diagrams that the proposed

MCML-FB logic style reduces the number of NMOS

transistors used in realizing a logic function as compared to

conventional CMOS and MCML logic style.

The performance of the circuits has also been compared in

terms of power consumption. The power result of CMOS

circuits is related mainly to the dynamic power dissipation

whereas the result for MCML based implementations

includes the static power due to the presence of the constant

current source. It is found through simulations that CMOS

circuits consume more power than MCML circuits. However,

it is also found that the circuits based on conventional and

proposed MCML style consume equal static power.

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TABLE II: PROPAGATION DELAY (PS) FOR DIFFERENT CIRCUITS

V. CONCLUSIONS

This paper proposes a new MCML-FB logic style that can be used for the implementation of digital circuits operating at high frequencies. The proposed circuit style employs a positive feedback in conventional MCML that increases the switching speed of the circuit and reduces the number of transistors needed to implement the circuit. Different circuits based on proposed logic style have been simulated in PSPICE using 0.18µm CMOS technology parameters. Their performance evaluation indicates that the proposed style improves the speed of the gates as compared to CMOS and conventional MCML circuits.

REFERENCES

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[3] J. M. Musicer, J. Rabaey, “MOS Current Mode Logic for Low Power, Low Noise, CORDIC Computation in Mixed-Signal Environments,” Proceedings of ISLPED, pp.102-107, July 2000.

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[7] D. Allstot, S. Chee, S. Kiaei, and M. Shristawa, “Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs,” IEEE Transactions on Circuits and Systems I, vol. 40, pp. 553–563, 1993.

[8] H. Hassan, M. Anis and M. Elmasry, “MOS Current Mode Circuits: Analysis, Design, and Variability,” IEEE Ttransactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 8, pp. 885-898, 2005.

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Logic Style -> Conventional

CMOS

Conventional

MCML

Proposed

MCML-FB Circuit

2- input NAND 114 108ns 100

3- input XOR3 260 246 210

3-input CARRY 142 119 102

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