Crosstalk Avoidance in RLC Modeled Interconnects using Low Power Encoder

G. Nagendra Babu, Deepika Agarwal, B. K. Kaushik, S. K. Manhas and Brijesh Kumar

Department of Electronics and Computer Engineering Indian Institute of Technology Roorkee

Roorkee, INDIA na955pec@iitr.ernet.in, deepikaagarwal0987@gmail.com, bkk23fec@iitr.ernet.in, samanfec@iitr.ernet.in, brijesh2228@gmail.com

Abstract— Most of encoding methods proposed in recent years has dealt with only RC modeled VLSI interconnects. With growing importance of inductive effects, it is now almost mandatory to design encoders that operates on RLC modeled VLSI interconnects. Therefore, this research work introduces an efficient bus encoder that employs Bus Inverting (BI) method to dramatically reduce crosstalk in RLC modeled interconnects. The proposed model is one of the best and proficient method for the reduction of crosstalk in interconnects. The proposed encoder consumes very less power which makes it extremely suitable for current high-speed VLSI interconnects. The proposed model demonstrates an overall reduction of 55.43% in power dissipation and 45.87% reduction in crosstalk delay for the worst case switching scenarios of 4, 8 and 16-bit lines . Keywords - Inductance effects, Bus-invert, Crosstalk, Power dissipation.

I. INTRODUCTION

The performance of a high-speed chip in deep sub-micron technology is largely dependent on interconnects, which connect different macro cells within a VLSI/ULSI chip [1]. With ever-growing length of interconnect and on chip clock frequency, the effects of interconnects cannot be restricted to RC models. The importance of on-chip inductance is continuously increasing with faster rise times, wider wires, and the introduction of new materials for low resistance interconnects. It has become well accepted that interconnect delay dominates gate delay in current deep sub micrometer VLSI circuits. With the continuous scaling of technology and increased die area, this behavior is expected to continue. On-chip inductance has turned out to be significant in designs with giga-hertz clock frequencies [2, 3]. This increased the importance of inductive effects in interconnects, where the traditional lumped and distributed RC models [4] of interconnects are no longer accurate as they result in substantial errors in predicting delay and crosstalk. There has been recent work to include the impact of self-inductance during interconnect delay prediction. However, one aspect of on-chip inductance that has not been well studied is mutual-inductive coupling. Mutual inductance causes signal-integrity issues by injecting noise

pulses on a victim line [5, 6] as shown in Fig. 1. Most of the existing noise models and avoidance techniques consider only capacitive coupling. However, at current operating frequencies, inductive-crosstalk effects can be substantial and should be included for complete coupling-noise analysis and reduction. This diminished the performance of circuit by increasing in wire delay [6, 7].

Mutual-inductance coupling occurs when both of the interconnect lines which are adjacent have same transition (i.e. either from 0 to 1 (↑↑) or from 1 to 0 (↓↓)). In that case leftmost aggressor wire induces magnetic field on the victim wire which tends to flow a current which is in opposition to the original current [8, 9]. In case of RC modeled, the worst case crosstalk delay occurs when the adjacent wires have an opposite transition. On the contrary, this worst case pattern is the best case for RLC model [10]. Most existing works focus on reducing the effects resulting from coupling capacitance on the bus structure by introducing many bus encoding techniques [4, 11]. There is not much work in the literature considering inductive effects on the bus structure.

Fig. 1. Effect of RLC Interconnect Model

This paper mainly focuses on reducing power dissipation, crosstalk, propagation delay and chip size of encoder and decoder of RLC modeled interconnects. Here the proposed method reduces the two undesirable types of crosstalk i.e. Type-0 and Type-1 couplings which are the worst cases in RLC modeled of interconnects. Results show that the power dissipation, crosstalk, propagation delay and encoder size is considerably reduced in comparison previously designed encoders [10, 12]. The rest of the paper is described as follows. Section II describes crosstalk and power dissipation expression and their dependence on different parameter. Section III describes the working of proposed method. Sections IV

Input Output

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discusses the results of obtained for encoders driving RLC modeled interconnects. Finally, Section V draws important conclusions.

II. POWER AND CROSSTALK IN RLC MODELED INTERCONNECTS

Power dissipation in VLSI interconnects can be expressed as [13, 14] , (1)

where CL is load capacitance, Vdd is supply voltage, f is

the clock frequency and α is the average switching activity which lies between 0 and 1. For achieving low power in circuits one or more terms Vdd, f, CL and α must be minimized. Here Vdd and f are assumed to be already optimized for low power. Therefore power dissipation is proportional to the number of signal transition. Symbols and terminologies used throughout this paper are as following

: The bus value to be sent presently on the bus line. 1 : The bus value sent previously on bus line. : Control line for data bus to be sent at time . 1 : Control line for data bus sent at time 1 .

TABLE-1 3-BIT BUS CROSSTALK CONSIDERING RC EFFECTS

Type-0 Type-1 Type-2 Type-3 Type-4

- - - - -↑ - ↑ - - ↑↓ ↑↓↑ ↑↑↑ - ↑↑ ↑ - ↑ - ↓↑ ↓↑↓

↓↓↓ ↑ - - ↑ - ↓ ↑↓ - ↑↑ - ↑↑↓ ↓↑ -

- - ↓ ↑↓↓

- ↓↓ - ↓ - ↓ - - ↓ - ↓

↓↓ - ↓ - ↑ ↓↓↑

↓↑↑ ↑: switching from 0 to 1, ↓: switching from 1 to 0, - : no transition

Coupling between interconnects can be classified into five types i.e. Type-0, Type-1, Type-2, Type-3 and Type-4 as shown in Table 1. Type-0 coupling occurs when the present data bits (B(t),Inv(t)) and the previous data bits (B(t-1),Inv(t-1)) have transitions in all bit positions i.e. (from 000 to 111 (↑↑↑)) or (from 111 to 000(↓↓↓)). Two conditions cause Type-0 coupling. In this, coupling capacitance is zero but the mutual inductance is very high. Type-1 coupling occurs when there is one or two transitions in the same direction i.e. present data and the previous data have same transitions in one or two bit positions (i.e. transition from 000 to 011 (-↑↑) or from 110 to 111(- -↓)). Eight conditions cause Type-1 coupling. In Type-1, simultaneous transition of two bits in the same direction cause mutual coupling

which is less as compared with Type-0. A Type-2 coupling occurs if the center wire is having opposite transition with one of its adjacent wires (from 011 to 100(↑↓↓)) or when the other lines undergo the same state transition with the center wire as quiet (i.e. data change from 100 to 001 (↓-↑)). Ten conditions cause Type-2 coupling. A Type-3 coupling occurs when the center wire undergoes opposite transition with one of the adjacent wire while the other wires are quiet i.e. when the data changes from 010 to 001 (i.e. -↓↑). In this case the mutual inductance is very less. In Type-4 coupling, all three-wires are having transitions in opposite direction with respect to each other i.e. from 010 to 101 (i.e. ↑↓↑). Here inductance coupling is zero but it is the worst case of RC model. With the findings of the best case and worst case patterns, a new encoding scheme is proposed for on-chip bus to minimize coupling delay with the dominance of inductance effects. The key idea is that inductance coupling effects should be alleviated by transforming the data sequences transmitting through on-chip buses. However, the architectures of the encoder and decoder should be of low complexity so that the power and delay overheads due to the codec circuitry can be compensated by the significant reduction of bus delay.

III. IMPLEMENTATION OF PROPOSED SCHEME A new model is proposed which is based on bus invert

method [16]. The proposed scheme consists four blocks as shown in the Fig. 2 i.e. Transition Detector, Type-0 Detector, Type-1 Detector and Multiplexer.

Fig. 2. Main Block Diagram of Proposed Encoder.

The first block is the transition detector which detects the transition by comparing the present data with the previous data. The next step after detecting transition is to examine whether these transitions causes crosstalk or not. The proposed method employs two detectors i.e. Type-0 detector to detect the Type-0 couplings and Type-1 detector check the Type-1 couplings. If either of coupling is present then the pin becomes ‘High’.

A. Transition Detector Transition detector checks the occurrence of transition

by using AND gates. The top 5 AND gates detects the low to high transition (↑) and the bottom 5 AND gates detects the high to low transition (↓) as shown in Fig. 3. For this purpose it uses the data which is transmitted previously, it compares the present data with the previous data. If there is

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any transition the output becomes ‘High’ otherwise it is ‘Low’.

Fig. 3. Block Diagram Representation of Transition Detector.

B. Type-0 Detector Type-0 coupling consists the two cases which has been tabulated in Table I. Transition detector detects the transition which means that the output lines (S0, S1, S2, S3, S4) goes high (i.e. ↑↑↑↑↑). But coupling occurs between the adjacent lines so there is a need to divide the five lines (4 data lines and 1 invert pin line) into a group of three and so there are three combinations (S0S1S2, S1S2S3, S2S3S4) as shown in Fig. 4. The bottom lines are complement to the top five lines i.e. these lines are at logic low if there is a high to low transition and when there is no transition (↑and-).

Fig. 4. Block Diagram Representation of Type-0 Detector.

The proposed model uses these lines to detect a Type-0 coupling. These three lines (S5, S6, S7) are given to OR gate to detect a Type-0 coupling between line0, line1, line2. When output of OR gate goes low then there is no coupling between the lines. OR gate is implemented by using NAND gate in this model. Thus Type-0 coupling due to low to high transition (↑↑↑↑↑) are detected using S5, S6, S7, S8, S9 lines.

Similarly, high to low transition (↓↓↓↓↓) are detected using the S0, S1, S2, S3, S4 lines.

A. Type-1 Detector

Fig. 5. Block Diagram Representation of Type-1 Detector.

Type-1 coupling consists eight cases which has been tabulated in Table I. In this Type-1 coupling of low to high transition between lines 1, line 2, line 3 are detected using S0, S6, S7 and that of high to low transition is detected using S5, S1, S2 and so on as shown in Fig. 5. In this the model combines the four cases which cause crosstalk and are implemented using one 3-input NAND gate.

D. Multiplexer Fig. 6 shows that when either N1_OUT or N0_OUT is

“high” inverted data must be transmitted, otherwise original data is to be transmitted. The data is given as one of the input for the XOR gate and control line (INV(t)) is given as the other input for the 2-input XOR.

Fig. 6. Multiplexer

IV. RESULTS The proposed method has been simulated to find power

dissipation and propagation delay of the bus codec with the 0.18, 0.13, 0.09 and 0.07-μm technology by using HSPICE. Although internal diagrams of encoder has been shown for only 4-bit, the model has also been extended to 8-bit and 16-bit using a shielding method. The lines are shielded from each other as shown in the Fig.10.The length, width, thickness and spacing of the interconnects used are 1300, 0.99, 0.53 and 1.37-μm respectively.

Inv(t-1) Inv(t)

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A. Crosstalk Reduction

The proposed method has eliminated the worst case crosstalk effect which is introduced in between redundant bit and clusters. Fig. 7 shows the use of redundant shielding line to eliminate Type-0 and Type-1 couplings between inter-cluster regions.

Fig. 7. Interconnect routing for an 8-bit bus

The proposed method is the best method to reduce Type-

0 coupling because they fully eliminate Type-0 coupling (i.e. 100%). It also reduces the Type-1 coupling by 82.8% which is less severe compared to Type-0 coupling.

B. Total Power Reduction

Total power dissipated by the System includes the power dissipated by encoder, decoder and interconnects. The total power dissipated by the total set up is as shown in Table 3. In the same feature size, as the number of bits increases the power dissipation also increases.

Table-3 Power Dissipation in Different technologies for various bus widths

Technology (μm)

Power Dissipation (μW)

4 bit 8 bit 16 bit

0.18 18.968 37.932 75.729

0.13 5.5447 10.897 21.788

0.09 5.3797 10.746 21.513

0.07 3.766 7.5343 15.065

C. Total Propagation Delay Reduction

Table 4 shows the worst case propagation delay for different technologies. On scaling down the technology, total propagation delay is increasing.

Table-4 Worst Case Total Propagation Delay on Different Bus Codec Technology (μm) Vdd Propagation Delay (ps)

0.18 1.8 1779 0.13 1.5 2035 0.09 1.2 2463 0.07 1 3003

V. CONCLUSION

This paper demonstrated the reduction in power dissipation, total propagation delay and crosstalk of RLC modeled interconnects by using bus invert method. The results show a reduction of 100% in Type-0 and 82.8% in Type-1 coupling. The encoding system also shows the power dissipation and propagation delay for different technologies. As the feature size decreases the power dissipation decreases and the total propagation delay increases.

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