2011 2nd International Conference on Instrumentation Control and Automation 15-17 November 2011, Bandung, Indonesia

Modeling and Simulation of a DC Motor Control System with Digital PID Controller and Encoder in

FPGA Using Xilinx System Generator

Prof. Behzad Behnam

Department of Electrical Engineering, Karaj Branch, Islamic Azad University, Karaj, Iran

(E-mail: b_behnam@kiau.ac.ir)

Abstract- This paper presents a novel method for design and

simulation of a DC motor closed loop control system in Field Programmable Gate Array device (FPGA). The digital designed PID controller is more advanced, beneficial and therefore produces a better response, as compared to the analog PID with velocity measurement. It can be implemented on system-on-chip devices easily. MATLAB Xilinx system generator toolbox based on Fixed-Point Arithmetic is used to design the digital PID controller using DSP architecture, plot the responses of the control system and generate the VHDL source code. The control system consists of a digital PID, the model of a real DC motor, a

real and new incremental optical shaft encoder model, encoder to

rpm and position blocks. Results show that the proposed system leads to lower the steady state and transient error.

Keyword-DC Motor Control; FPGA; System Generator; PID; Encoder; Digital System;

I. INTRODUCTION

A control system consists of a plant, driver, controller, sensor and signal condition. The plant has the mathematical model. Digital controllers need to use microcontrollers or microprocessors, and their memories need to decode, fetch and execute the program instructions. All these need to go through many machine cycles to be executed. But FPGA based PID controller is proposed because the operations on FPGA are hardware compatible operations in comparison with other types of controllers [1].

We can fmd several PID controllers with concurrent execution. There may exist one closed loop PID controller for each specialized required control system. All the PID controllers in this system may be integrated in a single FPGA device that will also contain other system components (System-on-Chip solution) [2]. There are many examples of the implementation of high order filters for radar, sound processing, and general Finite Impulse Response (FIR) filter implementation [3, 4, 5, 6]. A digital filter which is very close

978-1-4577-1460-3/11/$26.00 ©2011 IEEE

Masoud Mansouryar

Department of Electrical Engineering, Karaj Branch, Islamic Azad University, Karaj, Iran

(E-mail: masoud.mansouryar@yahoo.com)

to, the form of an Infinite Impulse Response (IIR) filter can represent most digital controllers.

In the review of literature, the FPGA approach for implementation of digital controllers is selected because FPGAs provide reconfigurable hardware designs, process information faster than a general purpose DSP, allow the controller architecture to be optimized for space or speed and bit widths for data registers can be selected based on application needs. The experimental system under control will be represented, along with the proposed structure for implementation of an adaptive controller on an FPGA [7]. Today's high-speed and high-density FPGA's provide practical design alternatives to ASIC and microprocessor based implementations [8].

In the existing literatures, it is shown that the use of Xilinx System generator and Simulink provides a powerful modeling tool that has the ability to model the controller, DC motor, encoder, driver and algorithm for measuring the RPM from the encoder output. Therefore, the objective of this study is to develop a digital PID implementation and measuring the RPM for DC motor speed control system by the use of FPGA. The simulation results show that the proposed system has an appropriate response.

II. PID CONTROLLER

This type of controller uses proportional, integral and

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Proportional Gain

Integral Integrator Gain

DerivatiVE Idesl Gain DaivativE

Figure I: Typical PID

2011 2nd International Conference on Instrumentation Control and Automation 15-17 November 2011, Bandung, Indonesia

derivative terms. Although it's complex, it is powerful and therefore very useful for industrial control systems. Fig. I show typical PID.

By tuning the three coefficients of the actions, the controller can provide the control action designed for specific process requirements. The design would be more complex and need more addition, subtraction and multiplication in converting to the OSP architecture.

In order to design digital PID controller we use the below architecture as the base and the Fixed Point arithmetic is undertaken in our design.

III. CONTROLLER OSP ARCHITECTURE

A. DSP Equations

In general, digital controllers can be implemented as digital filters in the following form, where k is the current sample in time, for a given sample period T;

n n

y(k) = L a,x(H) -L b,y(H) i=O i=]

(1)

With n=2 the z-transform of the following second order filter transfer function is concluded:

Y(k) = aoX(k) + a]X(k -1) + a2X(k - 2)

-b1Y(k -1) -b2Y(k -2)

B. PID Controller

(2)

We can implement a PID using a second order filter. The analytical equations are:

t d (t) U(t) = Kpe(t)+KI fe(t)dt+Kf)_e_+PI(O) (3)

o dt

Where,

K p = proportional gain

K D = derivative gain

e(t) = error in % of full scale range

KI = integral gain

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PI (0) = value of integral term at t = 0

Laplace K )U(S) = KpE(S) +_1 E(S) + Kf)SE(S) (4) S

D(S) = U(S) =K + K] +K S E(S)

p S D

From 2 and 5:

D(Z)=K +K T(Z+l)+KD (Z-l) (6) p I 2 (Z -1) T Z

Generally for digital controllers b2=O, b1=-1 Therefore coefficients aO,a],a2 can be given as [8]:

T Kf) ao =Kp +K]-+--2 T

a = K + K T _ 2

Kj) ] p ] 2 T

Kj) a =--2 T

IV. FPGA SIMULA nON

(5)

System Generator Can simulates and generates VHDL code for design by considering the correct hardware platform and also takes care of the synchronization and interfacing problems.

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In this work, there is a modeled DC motor control system in Simulink and outstanding results are obtained from this simulation. The whole model is shown in Fig. 2;

There is also a comparison between the digital model and an analog one (Fig. 3). The parameters of both models are the same and only the PID is changed. Also the analog PID control system has a unit feedback.

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Om:tl v:fw:::;:�r l""��,,1

Figure 2: The Digital Control model in Matlab Simulink

2011 2nd International Conference on Instrumentation Control and Automation 15-17 November 2011, Bandung, Indonesia

Figure 3: The Analog PID Control model in Matlab Simulink

Three main blocks are used. The input signal is a repeating sequence which is sweeping among 0, 500, -1000. There are other scopes for showing the important signals; also there is a wavescope in FPGA block. By using sample frequency f=1 MHz or T= 1 f.ls and PID Tuning program, and trying different numbers, the coefficients of gains compatible with the ramp input result is:

The derivative term would transform the step input signals of encoder to the impulse. This would cause the system to become instable; therefore the output of the system has to be zero. Fig. 4 shows the created PID model using Xilinx Sysgen.

This PID needs the following blocks in order to complete the model.

Encoder to RPM block is also needed in the DSP architecture which was implemented with the Sysgen. Two 24 bit counters are used in the Encoder to RPM block that makes the output signal resolution become higher. The dir (direction, cw=l, ccw=O), pos (motor shaft position) and RPM signals of this block are shown in the results of Fig. 10; the signals change by inverting the direction.

-Figure 4: Discrete PID model created with Sysgen toolbox in Simulink

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V. REAL MOTOR AND REAL ENCODER INDUSTRIAL MODELS

The plant which was under test was a DC Motor with industrial applications and some specifications as follows in TABLE l.

Fig. 5 shows the Simulink model of the motor with above parameters.

TABLE 1. THE INDUSTRIAL MODELED MOTOR SPECIFICA nONS

Maxon 2332.968.12.216-200

RA-7.94 (2

LA=1.54 mH

Kt=39.3m N.m A

Jcq-Jm-27.8 g.cm2

Bcq=Bm"" 0 "" I n(kgm2) s

I1Kb=243 (pm) => Kb=39.3m Volt

�----L--------------------'ICO

Figure 5: Simulink model ofthe DC motor

Figure 6: Current and Voltage output ofthe motor model

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2011 2nd International Conference on Instrumentation Control and Automation 15-17 November 2011, Bandung, Indonesia

The model worked properly with the real parameters. A saturation block is used to represent the motor driver. The voltages are restricted to ±24 Volts. Also the motor can sink up to 3A of currents. Fig. 6 shows the results. The optical shaft encoder was modeled with n=10000. Fig. 7 shows the Simulink model of the encoder.

The real encoder parameters were obtained from the model: DGS60-AIAIOOOO incremental encoder.

we can obtain rpm as

60 rpm = xM=KfXM 4xnxTs

(4)

Then III Equation (4), and K f is a steady coefficient

which is concern to physical specifications of encoder and

sampling time (Ts = O.5ms). In this method, the error in

each period of T, measurement is:

60 errorf = Kf = ----4xnxI:�

60 ------- = 3rpm 4xlOOOOxO.5ms

VI. RESULTS AND CONCLUSION

Figure 8 gives the comparison of the set point RPM signal and the motor RPM output signal (digital PID system). Also the RPM of the motor is kept tracking the input signal. Figure 9, shows the result for the continuous PID model (analog PID system) in Matlab Simulink. According to the simulation results, simulation of the digital PID controller would lower the steady state error as it is seen in the results. Also the digital PID would be more beneficial, accurate, compact, powerful and sharp.

Fig. 8 and Fig. 9 show that the digital and analog output signals are almost similar which can be conclude that the design would be well compatible with the real implementation. Fig. 10 shows the wavescope result in a specific period of time. This guarantees that the model is working well and gives a better understanding of the output signals statuses. Also in TABLE 2, Xilinx Resource Estimator, results the device resource summary. It provides the information regarding the number of needed Slices, Flip-Flops, lOBs and LUTs which gives us estimation for choosing the best FPGA.

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"""""a Figure 7: Encoder model with input RPM and 2 outputs CHA and CHB

Figure 9: Analog PIO controller response

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2011 2nd International Conference on Instrumentation Control and Automation 15-17 November 2011, Sandung, Indonesia

TABLE 2. RESOURCE ESTIMATOR OUTPUTS

Slices - 3835

Flip Flops = 3145

BRAMs = 0

LUTs - 7402

lOBs = 190

MultsIDSP48s = 0

TBUFs - 0

rpm

dir

pos

Clock

I 0 0.5 1.5

Time in P -seconds

Figure 10: Wavescope signal comparison

This system is developed with the closed loop control system (encoder in feedback) in comparison with the unit feedback control system [I, 8], and sampling time of Ts=1 Ils with Ts=lOO Ils [8]; More stability and better response is achieved.

It is not the first time that a PID system is implemented in FPGA, but the method of velocity measurement and control and the structure of PID are unique in this article. Aslo, according to the encoder specifications and low sampling time, most of the microcontroIIers cannot be used in this system, unless a OSP chip is used which is more expensive than a suitable FPGA. So this is system is more beneficial. In future works, we are planning to implement this system on real hardwares.

REFERENCES

[I] Vikas Guptal, Kavita Khare& R. P. Singh, " Efficient Design and Fpga Implementation of Digital Controller Using Xilinx SysGen®", International Journal of Electronics Engineering, 2(1), 2010.

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[2] Joao Lima, Ricardo Menotti, Joao M. P. Cardoso, and Eduardo Marques," A Methodology to Design FPGA-based PID Controllers".

[3] Moeller, T. L and Martinez, D. R.,"Field Programmable Gate Array Based Radar Front-End Digital Signal Processing", Proc. 7rh Annua Iggg Symp on Field-Programmable Custom Computing Machines, pp. 178-187, 1999.

[4] Kaluri, K.; Wen Fung L_ong; Kah-Howe Tan; Johnson,L.; Soderstrand,M.," FPGA hardware implementation ofan RNS FIR digital filter", Conference Record of the Thirty-Fifth Asilomar Conf on Signals, Systems and Computers, 2001, Vol. 2 ,pp. 1340 -1344, 2001.

[5] Mishra, A; Hubbard, AB., A cochlear filter implemented with a field­programmable _t_ array, IEEE Trans. on Circuits and Systems.II: Analog and Digital Signal Processing, Volume: 49 Issue: I, pp. 54 - 60 Jan. 2002.

[6] Yamada, M.; Nishilmra, A , High-speed FIR digital filterwith CSD ctmt_ficients implemented on FPGA ,Proceedings of the Aria and South Pacific Design Automation Conf, pp 7-8, 2001.

[7] David A, Gwaltney, Kelmeth D. King and Keary 1. Smith," Implementation of Adaptive Digital Controllers on Programmable Logic Devices ", NASA Marshal/Space FlU Center, Huntsville, AL.

[8] VCET, Vasai, MANIT, Bhopal," Efficient FPGA Design and Implementation of Digital PID Controllers in Simulink®"lnternational Journal of Recent Trends in Engineering,2009.

[9] Franklin, G.F., 1.0. Powell and M.L., Workman 1990."Digital Control of Dynamic System". Regarding. MAAddison-Wesley Publishing Company.Yan Yan, Master Thesis KTH/ ICT / ECS - 2007 -88.

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