[IEEE 2011 28th National Radio Science Conference (NRSC) - Cairo, Egypt (2011.04.26-2011.04.28)] 2011 28th National Radio Science Conference (NRSC) - Design and laboratory testing

28th NATIONAL RADIO SCIENCE CONFERENCE (NRSC 2011)

April 26-28, 2011, National Telecommunication Institute, Egypt

Design and Laboratory Testing of 802.15.4 2.4 GHz Baseband Modem

Loay D. Khalaf, Abdel-Latif AIShalaljah2, Daoud Burghal3 'Electrical Eng. Dept., The University of Jordan, Amman, Jordan, [email protected]

2SRTD, Amman, Jordan, [email protected] 3Zain Jordan, Amman, Jordan, [email protected]

ABSTRACT

The 802. 15.4 was chosen by Zigbee as the physical layer due to its characteristics; low power and low hardware complexity. This will make it available in a large number of devices ranging from remote controls to wireless sensors. We present a design for the Baseband section of the PHY and a laboratory testing environment where the real world impairments are simulated and controlled by the user to test the hardware implementation in real time. The Modem was implemented on a field programmable gate array (FPGA) software defined radio ( SDR).

Keywords: Software Defined Radio, Zigbee physical layer, baseband modem 802. 15.4

I. INTRODUCTION

The 802. 15.4 2.4GHz IEEE standard describes a low complexity communication system that can be used in short to medium range up to 100 meters for personal area networks (PAN) [ 1 ]. This standard was chosen by Zigbee as one of the physical layer communication links to be used in Zigbee devices [2]. The Zigbee Alliance produced standards for low cost, low power, wireless networked products to be used in home automation, healthcare, remote control, smart energy, telecommunications, and more. Zigbee transceivers can act as coordinated sensors to form large networks over large distances that extend many times the maximum distance achievable by a single device. Requirements for Zigbee devices include low hardware complexity, network capable and low power consumption.

Low hardware complexity in a wireless device means that the signal processing for modulation method used is simple. Some modulation methods require complex algorithms to perform channel estimation for coherent detection, or use Transforms methods for frequency equalization as in OFDM, or rake receivers as in other COMA systems [3 ]. The 2.4 GHz 802. 15.4 is a simple Direct Sequence Spread Spectrum (DSSS) packet based, that is robust enough to work in low power (at 1 milli Watt transmitter output) in the unlicensed bands, and yet to use simple Algorithms that do not require complex hardware.

Low power consumption requires efficient designs that use minimal hardware and clocking in an efficient technology such as CMOS. The radio transceiver should be able to turn off the components that are not being actively used at the time, such as the DSSS de spreading detectors during packet sensing or AGe. Different use of the devices will dictate power consumption. The wireless sensors might be used in situations where batteries should last few months, and some devices will simply be discarded once batteries run out. The devices have a sleep and active modes. During sleep mode, the device will send a packet then enters a very low power state where only a timer is active.

Previously published work includes RF Frontend (RFE) design [5], RF and system analysis [6], and Baseband design [7]. Here, a design for the 2.4 GHz DSSS modem is presented. The modem performs all signal processing required for the operations at Baseband, and consumes about 100 k gates as implemented on Altera Cyclone II FPGA [8]. The modem requires a RFE to perform frequency shifting for transmit and receive operations. The RFE consists of amplifiers, mixers, and frequency synthesizers. A receiver section of a RFE is shown in Fig. 1 below [4].



LNA variable gain lowpass filter

Fig. 1: Radio receiver frontend.

Analog to digital

converter

This work differs in that a laboratory testing environment that enables the user to control a wide range of channel and system impairments is implemented, and to obtain results in real time together with reference data that can be used to indicate performance problems is described. While the testing of the system is usually done at a high level in a simulation such as a C language, Scilab, or Matlab, the results collection process might take hours for few packet processing. A receiver configured using FPGA runs at actual speed and enables testing the modem in few seconds. It is to be noted that the high level testing and verification is still required during initial design and development of the Algorithms.

This paper is organized as follows: section II describes the signal, section III provides an overview of the baseband modem system, section IV describes the laboratory testing environment, and section V presents the conclusion.

II. SIGNAL DESCRIPTION

A packet is shown in Fig.2 below. A preamble is prepended to the transmitted information. The preamble contains 10 DSSS symbols that are used to perform AGC, frequency offset correction and information section frame detection. The maximum packet size is 128 bytes.

Preamble SFD Frame length PSDU (8 symbols) (2 symbols) (1 byte) (variable)

Fig. 2: Packet format with preamble and data.

Data is sent at 250 kbps. Four information bits are grouped into one symbol, forming a total of 16 symbols. Each symbol consists of32 spreading chips. The 32 chips are split into I and Q channels of 16 chips each, making the chip rate 2 Mcps over I and Q channels, with each chip duration of 1 micro sec. The chips are shaped into half sine pulses and the Q channel is delayed by one half chip duration to make an OQPSK signal. The half sine was chosen to reduce the interchip interference (lCI) between adjacent chips due to the channel limited bandwidth (BW). All these operations are done at Baseband. The I and Q channels then are modulated by the RF frequency of 2.4 GHz, amplified, and transmitted via the antenna.

The power spectral density (PSD) of the signal is shown in Fig.3 below.



The PSD of transmitted signal

-0.5

-1

-1.5

-2

-2.5 ..... , ......... : .......... : ......... :

_3 L-__ � __ � ____ L_ __ -L ____ L-__ � __ � __ � -4 -3 -2 -1 0 2 3 4

freq (Hz) x 106

Fig. 3 : PSD of transmitted signal.

The DSSS spreading codes have good autocorrelation and cross correlation properties. This enables simple algorithms to perform AGe, frequency offset estimation, and frame detection. The standards call for inexpensive crystals for the clock and the frequency synthesizer oscillator of 40 ppm. OQPSK with half sine pulse shaping is described in the standards. The OQPSK has a constant envelope to reduce nonlinear requirements on the power amplifier. A 40 ppm derived signal can have a frequency offset up to 180 KHz at 204 GHz that needs to be corrected at the receiver. Figo 4 below shows a received signal without frequency offset and with frequency offset. It is clear that this offset will cause errors and has to be corrected.

1-- IX signal without freq offset 1

0_5 --

o

-0.5

_1 L-____ �� ____ L_ ____ �� __ �� ____ � ______ � o 20 40

20 40

60

60 Sampl e

80 100 120

80 100 120

Fig. 4: Received signal without frequency offset and with offset.



III. SYSTEM DESCRIPTION

Transmitter

Fig.5 below depicts the transmitter. The data to symbol converter is a simple serial to parallel converter, or a shift register of size 4 bits. The DSSS spreader was designed from a 16x32 lookup table, or read only memory (ROM). The half sine filter is a fmite impulse response (FIR) digital filter. The transmitter is simple to design and much of its operations are described in the standards.

data .. data to .. DSSS ... half sine ...

symbol ... ...

filter

Fig. 5: Transmitter block diagram.

Fig.6 below shows the half sine filter optimized for the binary DSSS signal.

'00' 6

6 S 1 '01' 6

6 '10'

6 C 2----O>,L--,-----r----i

6 '11'

6

S -3 6

IX Filter Control 2

latch_reg

Fig. 6: Transmitter half sine filter.

Receiver

radio ... ... frontend

H S -

Parameters: C 0 = '000000' C-1 = '010110' C-2 = '011111' C=3 = '010110'

Fig.7 depicts the receiver. The receiver needs to identify a signal in a pre-assigned channel, adjust the LNA gain using AGe loop for constant signal level, estimates the frequency shift due to the transmitter and receiver clocks and oscillators, then identifies the start of frame delimiter (SFD) before the actual information is received. Once the SFD is identified, the received chips are despread to produce data symbols as described below.

antenna

1'7'

.. �



radio .. Frequency .. half sine ..

correction filter

�

Frequency estimation

Fig. 7: Receiver block diagram.

DSSS detection

The channel filter is a finite impulse response (FIR) filter of order 16, it rejects interchannel interference.

The AGC operation starts with the LNA variable gain amplifier at low gain, then the LNA output power is computed and compared to the average expected power when the signal level varies from minimum to maximum at the input of the analogue to digital converter (ADC). The LNA gain is adjusted in steps until the LNA output is equal to the expected power.

The frequency estimation process is done in two stages : coarse and fme. The coarse estimation (Fig.8) is done by averaging the angle difference between each subsequent samples over several cycles, then the fine estimator (Fig.9) uses the method of maximum likelihood to extract the frequency & phase offsets between the receiver and the transmitter with the aid of the pre-stored preamble sequence (Data Aided Estimation).

current sample

previous sample

average arguments 1----,

conjugate

Fig. 8: Coarse estimator.

map to frequency



1m { rxed signal}

e { rxed signal}

1m { rxed signal}

e { rxed signal}

Re {preamble code} angle = average [ atan( 0_1 / U ) . atan( - 1_0/0_0 ) I

�%->u �_>a_a

1m { preamble code}

.---------'%-> I_a

Fig. 9: Fine estimator.

The half sine matched filter is an FIR filter with coefficients equal to those of the half sine pulse samples. It maximizes the signal to noise ratio at its output, given the noise is A WGN.

The DSSS detector (Fig. to) is designed using the optimal detection methods. Given a signal with good properties, the communication system engineer is faced with the problem of designing the optimal receiver according to some constraints. The detection process of the transmitted data after being corrupted by additive white Gaussian noise (A WGN) can be performed using a maximum likelihood detector. DSSS detection using a bank of 16 de spreaders and matched filters is used. The output of the 16 despreaders is compared and the one with maximum energy is declared as the most likely transmitted symbol. It can be shown that if the probability of the transmitted symbols are equal, then this ML receiver is the best optimal receiver.

ed signal

xed signal

rXed signal

o

o

code 1

code 15

Find which correlation is maximum ?

symbol



Fig. 10: DSSS detector.

IV. IN-LAB TESTING

The transmitter and receiver design was captured using the Verilog hardware descriptive language (HDL). Initially, the Verilog description was simulated on a computer and the results where verified against the high level simulation results. Theses results are usually called test vectors. Once the design is verified during simulation, digital circuit implementation is carried out. This can be in the form of an application specific integrated circuit (ASIC), or in an FPGA.

The FPGA was generally used for rapid prototyping; however, large FPGA's of millions of equivalent system gates are now used in real systems. Once an FPGA is combined with a CPU and analogue and digital converters, the system is called a software defmed radio (SDR). Our test setup is depicted in the figure below. Information data is generated on a computer or read from a file. Afterwards, this data is used to compose a Baseband OQPSK signal. The signal is sent over RS232 interface to the FPGA where it is stored in a FIFO. Controlled impairments are added to the signal as specified by the user. It is worth mentioning that signal generation is much faster than signal detection, and thus hundreds of thousands of signals can be generated quickly.

PC ... ... ..... ... RS232 ... ... ..... ... FIFO

+

... ...

Fig. 1 1: System testing setup.

TX ...

emulator ... receiver r--

Generally, testing requires expensive equipment such as fast oscilloscopes, logic analysers, and spectrum analysers. The process of troubleshooting an integrated circuit can be complicated. Initially, the designers integrate several testing points into the IC to be used for signal comparisons. Testing equipment is then connected to these points and measurements are made. The number of testing points chosen are usually limited, and they can affect the packaging of the IC. Testing using FPGA prototype can be much simpler. A test point can be added to the FPGA in the laboratory and measurements made using inexpensive equipment. In our case, testing points data are routed to a special memory and then the data is read by the computer. Powerful software capabilities such as Fourier analysis are then used to make decisions. If more test points are required, then a simple process of insertion of a port to the FPGA is done. Fig. 12 shows the constellation diagram of the signal at different points.

08 06 0<

.06 .08

., . .,



-05

txed signal

() In-PhaSf!

05

signal after channel filter

1() 5 l 0 a .10

• 21)

·30

rxed signal

signal after frequency correction

.. ....

. :�"':.. ... ' . . • 1=- ' .' ' •

.. :.::; ....... . .. : ...

"' .. :�:.. ..

:"�,, - ' ..... " : . . .

. : ::'= -60 .40 ·20 () 20 40 60 o

tn-Pt\a'5:e In-PIlas.e

signal after matched filter

611

��., -.�� .:J" .... . :l�

�o : .. : .. .. ... ... ... ::. ..... ... #: .......

20

5

I ()

·20

• . . 40

� . ·i. ' .. .. ... . ....

.so So: , ..... J! . . �

·60 -40 .3) 0 3) 40 60 In-Ph.S8

Fig. 12: Constellation diagram at different points along the receiver.

v. CONCLUSIONS

A design for the ZigBee 2.4 GHz Baseband modem together with a testing environment is described. The Baseband modem occupied a low gate count around 100 k gates and easily fit on a moderate size FPGA. The receiver Algorithms were simulated and the results were used to generate test vectors to verify the modem operation. The FPGA runs at real speed with a clock of 16 MHz. The testing performed was extensive using powerful signal control on a computer and a hardware receiver implemented on FPGA. The user controlled parameters includes signal level to test the AGC loop, frequency offsets, and additive noise. Feedback at selected test-points in the receiver hardware can easily be inserted and the signals can be used for testing and troubleshooting.

ACKNOWLEDGMENT

This work has been funded by SRTD. SRTD is a European Union funded program.

REFERENCES



[1] Wireless Medium Access Control(MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (WPANs), IEEE 802.15.4-2006.

[2] Zig8ee Alliance, http://www.zigbee.org/. 2010 [3] J. Proakis, Digital Communications, 4th ed., McGraw-Hili, 2000. [4] T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed., Cambridge University Press,

2003. [5] M. Tedeschi, A. Liscidini, and R. Castello, "Low-Power Quadrature Receivers for Zig8ee (IEEE 802.15.4)

Applications," IEEE JSSC., vol. 45, pp. 1710-1719, Sep. 2010. [6] N. Oh, S. Lee, and J. Ko, "A CMOS 868/915 MHz direct conversion. Zig8ee single-chip radio," IEEE

Communications Magazine, vol. 43, Dec. 2005. [7] R. Koteng, "Evaluation of SDR-implementation of IEEE 802.15.4 Physical Layer," M. Eng. thesis,

Norwegian University of Science and Technology, Norway, 2006. [8] Cyclone II Device Handbook, Altera, 2008.

Documents

[IEEE 2011 28th National Radio Science Conference (NRSC) - Cairo, Egypt (2011.04.26-2011.04.28)] 2011 28th National Radio Science Conference (NRSC) - Design and laboratory testing