Abstract—In this paper we report a 2.4GHz ultra low power (ULP) CMOS down-converter based on current-reuse bleeding technique with resistive feedback. A new figure of merit maximizing gmfT -to-current ratio has been used to bias the transconductance stage. This single balanced mixer shows a conversion gain of 18.7dB and a noise figure of 11.5dB at 10MHz intermediate frequency (IF). Operating under 0.8V supply, the mixer core consumes 330µW and achieves an IIP3 and ICP1 of -14.9dBm and -21dBm respectively. The LO to IF and LO to RF isolations are 43dB and 28dB respectively.

Index Terms—Ultra-Low Power, Moderate Inversion, Bleeding technique, CMOS, Mixer.

I. INTRODUCTION INCE their emergence, Wireless Sensor Networks (WSN) have been growing continually becoming a key player in

many applications such as military tracking, remote monitoring, bio-sensing and home automation. These networks are based on IEEE 802.15.4 standard which is dedicated to low rate wireless personal area networks (LR-WPANs) in the unlicensed radio band (868MHz/915MHz/2.4GHz) [1]. Low power consumption, low cost of implementation and high level of integration are the main challenges of these systems. As radio frequency transceiver is one of the most power hungry block in wireless sensing node, power consumption of each block in the RF front-end (RFFE) have to be minimized among them is the down-converting mixer. To deal with these requirements, several techniques have been emerged in the literature. First is the reuse of the current between two building blocks. [2] proposes to stack the LNA on top of the mixer to share the same power supply. However, it increases the supply voltage due to stacking of transistors which is not suitable for ultra low power applications. Another technique consists in merging the building blocks functionality. [3] combines the LNA and the mixer namely Low Noise Converter (LNC). Compared with traditional cascaded LNA and mixer, this approach reduces significantly the power consumption by removing the DC current path flowing into the LNA. Nevertheless, applying the RF signal to the mixer input with a low amplification, results in a low gain and a high NF which degrades the entire receiver performance.

The mixer and oscillator combination is experienced in [4]-[6]. The very non linear operation producing the down-conversion provides a lot of output harmonics. The selection of the IF signal requires high Q filtering. Biasing techniques is a third alternative to reduce DC power consumption. [7] demonstrates that biasing all the transistors of the mixer in subthreshold region helps to dramatically lower power dissipation while maintaining reasonable performances. This approach is here investigated throughout the study of a figure of merit rating the RF behavior to drain current in MOS transistor (FOMLPRF). It is then applied to size the transconductor stage of a single balanced mixer based on a current bleeding topology. The section III relates the post simulations of the mixer and compares them with the state of art. Finally, summary and conclusion will follow in section IV.

II. CIRCUIT DESIGN

A. Moderate Inversion Operation The design of ULP RFICs in CMOS technologies entails

several design challenges. Due to the low bias current, transistor’s transconductance gm exhibits a low value [8], so to minimize power consumption effectively, transistors have to be biased in Weak Inversion (WI) region where they achieve maximum value of gm/ID. Nonetheless, in this region, transistor shows a poor frequency response, and therefore, may not be used extensively in RFIC design. In order to achieve ultra-low power consumption in RF frequencies, [8] introduces a new figure of merit, gmfT-to-current ratio (gmfT/ID). By taking into account both gm and fT, maximizing the gmfT/ID for a fixed bias current leads to the maximum achievable gain-bandwidth-product (GBW). It is drawn in fig. 1 for various transistor sizes in a 0.13µm CMOS technology. It figures out the maximum is reached operating the transistor in Moderate Inversion (MI) mode. Hence to yield the best tradeoff between performances and power consumption, MOS transistors in ULP RF building blocks should be biased in MI region.

A 2.4GHz ultra-low Power current-reuse bleeding mixer with resistive feedback

Hassen Kraimia, Thierry Taris, Jean-Baptiste Begueret and Yann Deval

S

IMS Laboratory, University of Bordeaux, 33405 Talence, France

978-1-4577-1846-5/11/$26.00 ©2011 IEEE 488

Mixer Core Buffer Stage

B. Current reuse bleeding In order to design an ultra-low power mixer, we need to

investigate the need of current reuse bleeding. Fig. 2 shows three configurations of active mixers.

The first configuration presented in fig. 2(a) is based on the

conventional single balanced current-commuting mixer. In such structure, both gain (1) and linearity (2) are directly proportional to the amount of current flowing through the transconductance stage, Ibias. On the other hand, noise figure increases significantly with this biasing current (3) [9].

biasnL IKRVCG

π2= (1)

n

bias

KIIIP

3243 ≈ (2)

SmRFSmRF

bias

SLmRFRgRAg

IRRg

NF42

12

22

2 γππγπ +++=

Where Kn = µnCox(W/L) γ : The channel noise factor and A : The LO amplitude.

The bottleneck of this configuration is the switching currents have to be half the transconductance current, which is preferable to be high enough to provide high conversion gain (1) and linearity (2). However, increasing the switching currents leads to have a non ideal switching operation [10] thus degrading the NF -i.e. the third term in (3). As well, to improve gain, linearity and noise figure, the transductor current (Ibias) needs to be enhanced without varying the switching currents. It is completed by the circuit of fig. 2(b) [11]. The principle is based on an additional current source, the bleeding transistor (Mbld), which steers the current pulled by the RF stage. By means, the DC current flowing into the switching pair is no longer controlled by the transductor stage. As well the tradeoff relying on the biasing current of the RF transistor is completely relaxed. The configuration of fig. 2(b), can evolve to the topology of fig 2(c), which takes advantages of both bleeding and current-reuse techniques. The p-channel transistor (Mbld) is used as a bleeding current source as well as a part of the driver amplifier. Thereby, the conversion gain is enhanced by increasing the overall transconductance of the RF stage from “gmRF” to “gmRF + gmbld”, where gmbld is the transconductance of the transistor (Mbld).

C. Proposed Topology for the ULP Mixer The simplified schematic of the proposed topology is

depicted in fig. 3. The mixer core is based on current-reuse bleeding configuration. The capacitor C2 is used to decouple the bias conditions of M1 and M4. Both transistors operate in MI region and are controlled by “VDD”, for the PMOS type, and “BiasRF”, for the NMOS type.

At the mixer output, a low-pass filter (RL, CL) allows for a rejection of high frequency harmonics -i.e. RF and LO signals. The buffer stage performs the output matching. It is designed as a pair of NMOS source follower (M5, M6) with current source (M7, M8).

The voltage conversion gain, input impedance and noise figure of the mixer are expressed as it follows:

0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,80

1x1011

2x1011

3x1011

4x1011

5x1011

6x1011

7x1011

g mf T/I D

(Hz/

V)

VGS

(V)

15µ/0,13µ 30µ/0,13µ 60µ/0,13µ 120µ/0,13µ

Fig. 1. gmfT/ID for various transistor sizes.

Weak Inversion

Moderate Inversion Strong Inversion

(a) (b) (c) Fig. 2. Various configurations of active mixers: current commuting mixer (a) bleeding mixer (b) current-reuse bleeding mixer (c).

Fig.3. Schematic of the the proposed ULP mixer.

VthN=0.26 V

(3)

489

1

2gs

g

S

LmT C

LRRgVCG ≈ (4)

( ) ⎥⎥⎦

⎤

⎢⎢⎣

⎡

+−+

+≈

ωω 2

0

0

0

0

CCCRg

LjCC

RCZ

gsT

fmTg

gsT

fin

⎟⎟⎠

⎞⎜⎜⎝

⎛++++=

f

S

LSmTSmP

PdP

SmN

NdN

RR

RRgRgg

RggNF 22

02

02 21

4γγπ (6)

With gmT = gm1 + gm4 ; CgsT = Cgs1 + Cgs4 and RS = 50Ω.

C0 models the capacitive loading effect of the switching

stage (M2, M3) connected to the transductor stage (M1, M4). The imaginary part of the input impedance Zin is cancelled by tuning Lg (5). Rf, in combination with CgsT and C0 adjusts the real part of Zin to 50Ω. According to (6), the larger the Rf is the lower the NF is. But Rf is also part of the matching network. So its value, in combination with Lg, is a tradeoff between NF and Zin.

The same current flows into M1 and M4, it is the bleeding technique, thus allowing the switching stage to act as an “almost perfect” passive mixer. As a matter of consequences, the noise contribution of (M2, M3) can be neglected. The NF only accounts for the RF stage (M1, M4), resistive load RL and the feedback resistor Rf in (6).

The Table I sums up the device sizes, yielding the best

tradeoff between linearity, conversion gain and noise figure. Fig. 4 shows the layout of the mixer which is implemented

in 0.13µm CMOS technology. The chip occupies an area of 0.745mm2 including PADs.

III. SIMULATION RESULTS The proposed ULP mixer operates at 2.4GHz RF signal,

2.41GHz LO signal and 10MHz IF signal respectively. It consumes 330µW under 0.8V supply voltage. “BiasRF” is set

to 360mV allowing transistor M1 to operate in moderate inversion region. “BiasLO” sets the overdrive voltage (Vgs-Vth) of the switching pair (M2, M3) to zero for an ideal switch. DC current flowing through M1 and M4 is 410µA. Fig. 5 shows the voltage gain and noise figure for various values of the feedback resistance Rf. Both characteristics improve with increasing Rf.

The feedback resistance also contributes to tune the input matching of the mixer. Fig. 6 illustrates the input return loss, S11, versus Rf. A tradeoff has to be found between a good input matching (fig. 6), a large conversion gain (CG) and a low noise figure (NF) (fig. 5). Hence, Rf has been set to 5KΩ in the implemented circuit.

Post-layout simulation of the voltage conversion gain (VCG) and single side band noise figure (SSB NF) versus LO power are reported in fig. 7. Their optimum values obtained at a LO power of 5dBm are 22.7dB and 9.3dB respectively. Considering a constrained power budget to address ultra low power applications, it is better suited to account for an LO power which does not exceed 0dBm, typically -1dBm. Under this assumption, VCG and SSB NF are 18.7dB and 11.5dB respectively.

1K 2K 3K 4K 5K 6K 7K10

12

14

16

18

20

10

12

14

16

18

20

VC

G (d

B)

NF

(dB)

Rf (Ω)

NF VCG

1,50E+009 1,88E+009 2,25E+009 2,63E+009 3,00E+009 3,38E+009-30

-20

-10

0

S11(

dB)

freq(Hz)

Rf = 1KΩ Rf = 2KΩ Rf = 5KΩ Rf = 7KΩ Rf = 10KΩ

-12 -8 -4 0 4 8 12 16 20

8

12

16

20

24

8

12

16

20

24

VC

G(d

B)

NF(

dB)

PLO(dBm)

VCG NF

(W/L)M1 (µm) 14/0.13 C2 (pF) 10 (W/L)M2=M3 (µm) 6/0.13 C3 (pF) 10

(W/L)M4 (µm) 24/0.13 CL (pF) 2 (W/L)M5=M6 (µm) 120/0.13 RL (KΩ) 2 (W/L)M7=M8 (µm) 30/0.13 Rf (KΩ) 5

Lg (nH) 12 R1, R2 (KΩ) 5 C1 (pF) 10 R3 (KΩ) 5

Fig. 5. Simulated voltage conversion gain and SSB noise figure versus Rf at 10MHz IF. LO power is -1dBm.

TABLE I. SIZES OF MIXER DEVICES

Fig. 4. Snapshot of the Mixer die, 814μm*915μm.

Fig. 6. Input return loss (S11) for various Rf.

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Fig. 7. Simulated voltage conversion gain and SSB noise figure versus PLO at 10MHz IF.

490

The single-tone 1dB compression and two tone large signal intermodulations are shown in fig. 8. The input referred 1dB compression point (ICP1) is -21dBm. The third-order intercept point (IIP3), -14.9dBm, was tested by applying a two-tone large signal at 2.4GHz and 2.401GHz.

Table II summarizes the performances of the proposed

circuit and various low power RF CMOS mixers from the literature. To compare them, we use the common figure of merit (FOMMixer) (7) which includes the conversion gain (Gain), noise figure (F), linearity (IIP3) and DC power consumption (PDC):

[ ] ( )mWPFIIPGainFOM

DClinearMixer *1

3*, −

=

It is not worthy the 3 best FOMMixer: this work, [7] and [14] bias the transistor in moderate inversion or close to the subthreshold voltage (Vth). This point figures out the interest in operating devices out of the Strong Inversion (SI) mode, typically in WI or MI, to address very low power applications in advanced CMOS technologies. Considering a comparison between our post-layout simulations and the measurements of [7] and [14], the current reuse bleeding topology achieves the second best FOM with -12.2dB and the lowest power consumption, under 0.4mW.

IV. CONCLUSION An ultra-low power down-converter implemented in

0.13µm CMOS technology has been presented in this paper. It

is based on current-reuse bleeding technique with resistive feedback. The transconductance stage operates in moderate inversion region in order to achieve the best tradeoff between performances and power consumption represented by the gmfT/ID ratio. The proposed mixer consumes only 410µA at 0.8V supply voltage. With a LO power of -1dBm, it yields a conversion gain, noise figure and third-order intercept point of 18.7dB, 11.5dB and -14.9dBm respectively. The design methodology, starting with the optimization of gmfT/ID, and then selecting the best suited topology to operate in MI region, allows the circuit to exhibit the lowest power consumption and second best FOM among the reported 2.4GHz mixers.

REFERENCES [1] IEEE Standard Part 15.4:Wireless Medium Access Control (MAC) and Physical

Layer (PHY) Specification for Wireless Personal Area Networks (WPANs), IEEE Standard 802.15.4-2003, 2003.

[2] A. Zolfaghari and B. Razavi, “A low-Power 2.4-GHz Transmitter/Receiver CMOS IC”, IEEE Journal of Solid-State Circuits, vol. 38, pp. 176-183, Feb. 2003.

[3] H. Sjöland, A. Karimi-Sanjaani, A.A. Abidi, “A Merged CMOS LNA and Mixer for a WCDMA Receiver”, IEEE Journal of Solid-State Circuits, vol. 38, pp. 1045-1050, June 2003.

[4] M. Bendak, B. Xavier, and P. Chau, “A 1.2 GHz CMOS quadrature self-oscillating mixer”, IEEE International Symposium on Circuits and Systems (ISCAS), vol. 5, pp. 434-437, Orlando, Florida, USA, May 1999.

[5] T.-P. Wang, C.-C. Chang, R.-C. Liu et al., “A low-power oscillator mixer in 0.18µm CMOS technology”, IEEE Transactions on Microwave Theory and Techniques,, vol. 54, no. 1, pp. 88-95, Jan. 2006.

[6] A. Liscidini, A. Mazzanti, R. Tonietto et al., “Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell”, IEEE Journal of Solid-State Circuits, vol. 41, pp. 2832-2841, Dec. 2006.

[7] H. Lee and S. Mohammadi, “A 500μW 2.4GHz CMOS Subthreshold Mixer for Ultra Low Power Applications”, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 325-328, Honolulu, Hawaii, June 2007.

[8] A. Shameli, P. Heydari, “Ultra-Low Power RFIC Design Using Moderately Inverted MOSFETs: an Analytical/Experimental Study”, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 105-108, San Francisco, USA, June 2006.

[9] H. Darabi and A.A. Abidi, “Noise in RF-CMOS Mixers: A Simple Physical Model”, IEEE Journal of Solid-State Circuits, vol. 35, pp. 15-25, January 2000.

[10] M.T. Terrovitis and R.G. Meyer, “Noise in Current-Commutating CMOS Mixers”, IEEE Journal of Solid-State Circuits, vol. 34, pp. 772-783, June 1999.

[11] S.-G. Lee, J.-K. Choi, “Current-reuse bleeding mixer”, Electronics Letters, vol.36, n° 8, April 2000.

[12] C. Hermann, M. Tiebout and H. Klar, “A 0.6-V 1.6-mW Transformer-Based 2.5-GHz Downconversion Mixer With +5.4-dB Gain and -2.8-dBm IIP3 in 0.13-um CMOS”, IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 2, pp. 488-495, Feb. 2005.

[13] V. Vidojkovic, et al., “A Low-Voltage Folded-Switching Mixer in 0.18-um CMOS”, IEEE Journal of Solid-State Circuits, vol. 40, pp. 1259-1264, June 2005.

[14] A.V. Do, C.C. Boon, M.A. Do, K.S. Yeo and A. Capuk, “A Weak-Inversion Low-Power Active Mixer for 2.4 GHz ISM Band Applications”, IEEE Microwave and Wireless Components Letters, vol. 19, no. 11, Nov. 2009.

[15] C.H. Wu and H.T. Chou, “A 2.4GHz Variable Conversion Gain Mixer with Body Bias Control Techniques for Low Voltage Low Power Applications”, Asia Pacific Microwave Conference, Singapore, Singapore, Dec. 2009.

-30 -25 -20 -15 -10-50

-40

-30

-20

-10

0

IIP3 = -14.9dBm

Out

put P

ower

(dB

m)

RF Input Power (dBm)

Fundamental IM3

ICP1 = -21dBm

Ref. Technology CMOS

RF [GHz]

IF [MHz]

PLO [dBm]

VDD[V]

PDC [mW]

Gain[dB]

NF [dB]

IP1dB [dBm]

IIP3 [dBm]

LO-RF[dB]

LO-IF[dB]

FOM**

[dB]

This work 0.13 µm 2.4 10 -1 0.8 0.33 18.7 11.5 -21 -14.9 28 43 -12.2 [7] 0.13µm 2.4 60 -9 1 0.5 15.7 18.3 -28.0 -9 33 22 -16.3

[12] 0.13µm 2.5 10 -1 0.6 1.6 5.4 14.8 -9.2 -2.8 70.9 54.2 -16.8 [12] 0.13µm 2.5 10 -1 0.8 7.8 15.0 8.8 -16.9 -9.5 71.1 54.2 -19.1 [13] 0.18µm 2.4 1 -2 1 3.2 11.9 13.9 - -3 - - -15.8 [14] 0.18µm 2.4 30 -2 1.8 1 32 8.5* - -14.5 60.5 - -9.6 [15] 0.18µm 2.4 10 0 0.8 2 14.5 17.1 -22 -11 - - -23

Fig. 8. IIP3 and ICP1 of Mixer at 330µW power consumption.

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TABLE II. Performance summary and comparison to other CMOS mixers

*DSB=Double Side Band **FOMdB=10log[FOMMixer, linear]

491