U sing Quadded Logic in nanoPLAs to aggressively increase circuit yield

Mahtab Niknahadt, Oliver Sandert, Luigi Carro *, Jose Rodrigo Azambuja *, Juergen Beckert, Fernanda Lima Kastensmidt*

tlnstitute for Information Processing Technology (lTIV) Karlsruhe Institute of Technology (KIT)

Karlsruhe, Germany {niknahad, sander, becker} @kit.edu

*Instituto de Informtica - PPGC - PGMICRO Universidade Federal do Rio Grande do SuI (UFRGS)

Porto Alegre, RS, Brazil { carro, jrfazambuja, fglima}@inf.ufrgs.br

Abstract-Because of the stochastic assembly, nano Pro­grammable Logic Arrays (nanoPLAs) are currently built with a costly test and characterization process. In this paper, we focus on design oriented defect tolerance instead of Physical oriented one, and propose a reliable implementation for nano devices. Our new methodology is based on Quadded NOR logic, which guarantees the circuit function for all single defects and almost all multiple ones. Under Quadded form of design we transfer the costly test and characterization phase in fabrication process of the nanoPLA to a reliable logic design. We use the wrapping feature of nanoPLAs and reduce the overhead of Quadded method on logics in nanoPLA. This feature allows implementation of quadruplicated logic on a nanoPLA by using spared nanowires. T his allows design with a very small area overhead. Results show about 100 percent availability of Quadded logic XOR gate implemented on nanoPLAs.

Index Terms-Nano Architectures, nanoPLA, Defect Tolerance Techniques, Quadded Logic

I. INTRODUCTION

kind of molecular scale logic. Nano Fabrics [5] are an ex­ample of this vision. They use two terminal diode crosspoints nanowires. [6] has explored how to use nanowires to build sub­lithographic PLAs and interconnected PLAs which is called nanoPLA. They built a two plane PLA with decorated silicon nanowires and device building blocks.

However, either in Nano Fabrics or in nanoPLAs, nanowires are a few atoms long in the diameter. The contact area between nanowires contains only a few tens of atoms. Nano scale architectures come with a new set of challenges due to defects as a result of smaller cross section and contact areas. Designs in this scale must be defect tolerant, making the test or characterization for usability an essential step in building circuits with nanowires [12] [13].

As the fabricated circuit may have different functional characteristics than the intended, the first step after fabrication must be characterization and test procedures to identify the working devices on the fabricated circuit and identify possible defects in order to program or activate possible spares [14]

N ANO architectures have emerged as an alternative to [15] [5]. This process is very time consuming and represents CMOS technology as one approaches the end of the a production bottleneck.

semiconductor road map and lithography based fabrications This paper focuses on defect tolerance on nanoPLAs by meet physical limitations [1] [2] [3]. Now it is becoming design. The nanoPLAs are used because of their elaboration possible to look beyond lithography and explore how devices and simplicity to be used in nano scale design [13]. A defect can be built without relying on lithography to pattern the tolerance method for nanoPLAs is perposed, where the costly smallest feature sizes [4] [5] [6]. test and characterization of nano wire is transfered to a logic

Bottom up techniques are demonstrated to define key feature design technique called Quadded logic. Thanks to the way sizes [4] [7] [8]. It has been shown that, by using these nanoPLAs are built, it will be shown that proposed approach techniques, it is possible to built nano devices such as carbon allow for reliable circuit operation, high yield and minor area nanotubes and silicon nanowires without relying to lithography overhead. to define smallest feature size. These devices have been rated A nanoPLA is composed of wired ORs followed by in­among the most promising of all the new technologies under verters and buffers allowing the designer to implement NOR investigation [9]. logic on it. Quadded NOR logic methodology [16] is used to

These techniques allow one to build features which are implement defect tolerant functions on nanoPLAs. Quadded just a few atom scales. At this scale programmable logics Logic is applied on logic gates, such as NOR gates, and are necessary to build any logic. Chemically self-assembled provides a high-reliable system [17] [18]. Quadded NOR structures, as the building blocks for molecular scale comput- logics are applied to nanoPLA. This way, design is fault ing, are by their nature very regular. Therefore, they are well tolerant and highly-reliable. suited to be used to implement regular arrays similar to Field [17] has measured the high-reliability of Quadded NOR Programmable Gate Arrays (FPGAs) [10] [5]. logics in circuits in comparison to the non-redundant ones.

Several researchers have begun to explore programmable All failure probabilities can be replaced by defect probabilities logic structures in this scale. [11] introduces a vision for thfs180in nanowires of nanoPLAs. When using the proposed reliable

AOA1 A2A3 Vcommon

Fig. l. Basic structure of nanoPLA with two planes. Broken wires can be distributed overall the PLA. It consists of two ORs (Top-Left and Bottom­Right) and Buffer and Inverter on the other side of every plane. Defects can be seen in wires where there are some spaces in nanowires [13]

design on nanoPLA, the time consuming process of test and characterization is reduced.

The remainder of this paper is organized as follows: Section II gives a background of state of the art nanowires and related nanoPLAs. The preliminary structure of nanoPLAs and possible crosspoint defects are described in this section. This section also refers conventional methodology of test and characterization of nanoPLAs briefly, in order to describe the savings allowed by the proposed method. In section III the basics of Quadded Logics in nanoPLA are presented, which includes features which are used to apply Quadded NOR form on the logic mapped on it. Section IV details our proposed approach while implementing the Quadded NOR logics on ex­tended nanoPLA. Section V shows some experimental results while section VI discuss them. Finally section VII concludes the paper.

II. BACKGROUND

A. nanoPLA

NanoPLAs, like conventional PLAs, consist of two pro­grammable NOR planes (Figure O. Each one of them consists of two arrays: a logic array and a buffer/inverter array.

The logic array is the programmable part of the NOR plane. Its junctions are bistable crosspoints. The logic array implements the OR function of its inputs [12]. Each of the connected junctions behaves like a diode and produces the wired OR logic of its inputs. If any of the inputs is high, it pulls up the OR term output. Figure 2 shows wired OR circuits, which can be constructed by programming the crosspoints.

The NOR plane also consists of a buffer/inverter array. Buffer/inverter arrays, which have nonprogrammable junctions [13] [19], are used to restore/invert the input signals. In order to provide a NOR function, the OR-term signals use these arrays for inversion. The output of the inversion can then be buffered for further usages.

To implement the XOR function on nanoPLA every function must be rewritten in NOR form to be able to program on nanoPLAs. In section III an implementation of XOR on nanoPLA has been described in details.

2

Inputs Inputs

"'-Output

Fig. 2. (a) Wired OR logic in crosspoints. (b) Its corresponding in nanoPLA

programmable crosspoints due to the structure of the junction and defects in nanowires [13].

[20] reported that 95% of the wires measured had good contacts, and [21] reported that 85% of crosspoint junctions measured were also properly usable. [22] mentioned that both of these experiments were early measurements and therefore, the yield is expected to be imrpoved. [12] reported about more than 90% good nanowires and more than 80% defect free crosspoint junctions. In our approach the system will work properly even if only 80% of nanowires and junctions are good.

Even if the defect rates are reduced in the future the methodologies such as the propsed one will be needed to have a reliable design. In nano architectures in general, variation effects on design result in a higher rate of soft errors, due to the intensive structure of carbon nano tubes. Therefore, it is mandatory to implement high-reliable designs [23].

Figure 1 gives an abstract view to the reader about the defect structures in nanoPLA and its defects.

C. Conventional Test and Characterization process in nanoPLAs

[6] introduced nanoPLAs. It presented an exhaustive test procedure for nanoPLAs. The test procedure is done before programming a function (for example XOR) on nanoPLA. Test procedure includes two steps: Discovering Present Addresses and Discovering Polarities. After knowing about the presence and polarity of each address, Programming Diode Crosspoints procedure is performed to configure NOR-NOR planes to implement the corresponding logic function. More details on programming crosspoint junctions can be found in [6].

As [22] also addressed, the test and characterization proce­dures take together about 128 steps for each nanoPLA. This leads to high test cost when considering large scale production.

This process is removed and instead of it, the function structure is modified to make it tolerant against defects on nanowires. It means that instead of doing a process to find suit­able (not defected) nanowires, which consumes time, a defect tolerance function on existing nanowires is programmed.

In order to program a function on nanoPLAs, it has to be reconstruct in NOR gates. This property is suitable for Quadded NOR logics, which use the behavior of NOR gates and wires them together making the function tolerant against faults.

III. QUADDED LOGIC ON NANOPLA B. Crosspoint Arrays and Defects As described in section II the complete characterization

AAs already mentioned, due to atomic scale of nanowires, for each nanoPLA is done in the conventional method to defects are very common in nanoPLAs. Figure 1 shows determine what are the exact programming steps that need to possible defect places in nanoPLA which are used in our be followed to program the intended function. Although this defect model. Two main defects in nanoPLAs are defects inl8lapproach can provide exact function and prevent extra spares

�r--t ... ............ ..

Ill'Iort Buffo.

eutre,RB •••• i

; t , .. '. :::C:::::::::::::::<L"'�""J

BB(O) <= i. BB(l) <=j. RB(O) <= BB(O). RB(l) <= BB(l) ..... 0 <= BB(4)

Fig. 3. XOR implementation on nanoPLA. i and j are invertedlbuffered on bottom plane (left line) and then are ORed together on top plane (left line) while inverting again on top right line and finally ORed again on bottom left and show on output. Bus definition in implementation of XOR on nanoPLA using VHDL

and due to this guarantee a good yield, the huge number of characterization steps may not be suitable for high demand fabrication process.

[22] presents a different paradigm of testing which is based on removing the process of characterization and inserting spare wires to guarantee the correct function in case of defect in original wires. A methodology based on Quadded logics is introduced, which makes not only a defect tolerant design but also reliable even against other kind of transient errors.

Quadded Logic is a technique for the introduction of re­dundancy to digital systems, and it allows a large number of failures to occur in digital systems without disturbing its capacity to perform the function in a proper manner which it is designed for it. It can be applied in designs which include ORIANDINAND and NOR logics.

The idea is to use Quadded NOR logics in nanoPLAs and make the design defect and fault tolerant. NanoPLA is specially suitable for Quadded NOR form because NORs can be provided using nanoPLA.

First, the fundamentals of Quadded NOR logics is shortly described and then the wrapping feature of nanoPLAs, which makes it easy to implement function on it, is introduced and finally using wrapping feature Quadded Logics design is integrated in nanoPLAs.

A. Quadded NOR logics

To introduce the concept of Quadded logics, XOR logic which is rewritten in NOR logics has been shown in figure 5 in

/I0

+I ��II��II�'r(XO�JO'")'XOr(J2'J3» 1

0+/11

/12+13 12+/13

3

Fig. 4. Wrapping feature in nanoPLAs is used here to implement four input XOR on nanoPLA. Two input XORs are generated in the first wrap and four input one in the second wrap. [I3]

ignore any changes in '0' values if there is a '1' in inputs (as already mentioned '1' is the dominant value). This is used in nanoPLA to tolerate against any kind of failures. More details on Quadded logics and their proof can be found in [24] [17] [18] [16].

B. Multilevel logic evaluation in nanoPLA

As described in the previous section, every function must be rewritten to NOR parts to be able to map on nanoPLA. The XOR in NOR form is rewritten and is programmed on nanoPLA. In order to use quadded NOR logics,one must have the entire design in NOR gates. This way, it is implemented as is shown in Figure 5(a).

Figure 3 shows the XOR implementation on nanoPLA. Equation 1 shows the NOR formed XOR logic which is used to map XOR on nanoPLA. Structure of testing nanowires and finding suitable wires to map XOR was described in the previous section. In figure 3 XOR programmed on nanoPLA is shown. This implementation is done after passing test and characterization process. From this figure on just the programming part in addition to buffer and inversion part of nanoPLA will be shown for simplicity reasons.

O = itfJj = i.j + i.j (1)

= (i+j)+(i+j) both its non redundant and Quadded forms. XOR is presented i andj are inverted and buffered in the below plane right and in NOR form due to our nanoPLA usage purpose. are programmed as corresponing OR which is needed in the

Each NOR gate in figure 5(a) is replaced by four NOR gates up plane. Then they are inverted in the top plane and finally in figure 5(b). Each Quadded form NOR has twice as many are ORed again in the bottom plane as the result. inputs as the non redundant gate. Four outputs of each stage Rather than using a separate physical plane for every logic are divided into two sets of two outputs. Each set provides stage of evaluation in a spread PLA mapping, the logic inputs to two gates in the succeeding stage. function can be wrapped around the PLA multiple times [13].

This arrangement of NOR gates and interconnections pro- Consider a 4-input XOR. The XOR is rewritten to some vides error correction capability. Error definition wides from NOR terms. [13] shows that it is possible to wrap the XOR bit flipping to defective wires which result in bit flipping. Both twice through the PLA, computing 4 input XOR as a cascade are probable in nanoPLAs. Any single error and a number of of two level XORs. In figure 4, implementation of the 4-inputs multiple errors introduced in Quadded XOR will not cause XOR on nanoPLA using wrapping feature has been shown failure in the functioning of the system. [13].

To illustrate this capability, in figure 5(b) assume that io Figure 3 illustrates the original implementation of NOR-generates' l' instead of '0' as the result of defect in wire. The NOR form of XOR. The inverting and buffering parts of result of neighbor NORs (82 and 83) is one as should be and nanoPLA is shown. In the bottom row, i and j as inputs are

io will effect 80 and 81 to '0'. Because ' l' is the dominant derived and inverted or buffered as shown. In the top lines value for NOR logic, it will remove this error in the next stage corresponding ORs are generated and finally in the top left line using the correct value of the neighbors. the final inversion is done and the XOR result is generated.

Errors that result in '0' instead of ' l' are corrected in most The multilevel programming ability, which is presented in cases. This is because of the nature of NOR logics whichl82figure 4, for a 4-input XOR logic wraps around the nanoPLA

JO

J'

J2

jJ

(a) IjO

IJ'

IJ2

IjJ

(b)

00 0, 0, 0,

Fig. 5. (a) XOR logic in NOR form. (b) Quadded NOR logic form of XOR

in order to program the sub XORs and the main XOR and the end as follow:

o = io EB il EB i2 EB i3 = (io EB i1) EB (i2 EB i3) (2)

= ((io + i1) + (io + iI)) EB ((i2 + i3) + (i2 + i3))

Every part is mapped on nanoPLA and used in the next wrapping. This feature is used in the next section while the Quadded XOR is mapped on nanoPLA.

C. The proposed approach

the multi level logic map capability in nanoPLA is used to map Quadded logic form on it and make it tolerance against defects.

Po = (io + il +)0 + )1) PI = (il + io +)1 + )0) P2 = (i2 + i3 + 12 + )3) P3 = (i3 + i2 +)3 + )2)

Qo = (io + il +)0 + )1)

Ql = (il +io +)1 +)0)

Q2 = (i2 + i3 + 12 + 33)

Q3 = (i3 + i2 + 33 + )2)

00 = (Po + P3 + Qo + Q3) 01 = (PI + P2 + Ql + Q2) O2 = (P2 + PI + Q2 + Ql) 03 = (P3 + Po + Q3 + Qo)

4

(3)

(4)

(5)

As Figure 6 shows, we only use the programming part of nanoPLA to show the Quadded XOR implementation on nanoPLA using the wrapping feature.

Firstly, the top inverting line buffers the inputs io to i3 and

)0 to 33 twice to be used in the bottom ORed area. Secondly, the bottom plane generates the Quadded OR forms and inverter of bottom plane inverts it. It also inverts the results of SO .. 3 and To .. 3. They are tllen ORed again witll tlle buffered iO .. 3 and )0 .. 3 in a suitable manner for Quadded logics. Finally, the inverter in the bottom plane inverts the result and generates

00 .. 3· Although Quadded logics have shown to be high-reliable

[18], applying them on logics will result in a 4 times bigger size. This area overhead is repaid by using them in nanoPLAs. However, one can define nanoPLAs with up to 100 nanowires [13]. In order to implement tlle XOR function, nanowires in programming part of nanoPLA and invertinglbuffering lines are used and added together in a way to achieve tlle function.

Using Quadded form, new nanowires in parallel are added to tlle original circuit wires. Entire Quadded form is implemented in one nanoPLA by using more nanowires. Therefore, we do not have an area overhead as large as Quadded Logics.

IV. IMPLEMENTATIONS The nanoPLA, illustrated in Figure 1 , is the target archi- In this section, we discuss how we implemented the

tecture for design methodology. In Figure 3 is shown how an nanoPLA in a simulation environment to study allow for fault XOR is programmable on nanoPLA after passing the process injection and reliability evaluation. of test and characterization of nanoPLA. A nanoPLA in VHDL is described by defining four internal

The programming strategy, implements the Quadded form wires: top and bottom buses and inverting and restoring XOR instead of XOR on nanoPLA. Every nanoPLA has two buses in each every right and left parts of the nanoPLA. planes and every plane consists of 6 wires. The number of Inverting/restoring buses are connected to top (bottom) bus nanowires in every plan is increased in order to achieve the and then are ORed together in bottom (top) bus, achieving Quadded form. Based on [25] there is no physical limitation to NOR logic, as shown in figure 3. increase the number of nanowires in every plane. Because of The XOR mapping on nanoPLA in Figure 3 is used to make the nature of Quadded logics, which quadruplicates the input connections between corresponding buses. First, one has to numbers, the number of nanowires in nanoPLA is increased buffer i and j in the top bus, then transfer tllem to tlle bottom to be further used in quadruplicated form. bus. By invertinglbuffering them in the left buses, one obtains

Equation 1 rewrites the XOR in NOR form to be suitable for them ORed together in the top bus, and they are then sent to nanoPLA. The Quadded form XOR in NOR gates is modified tlle right plane to be inverted and form a NOR gate. Assuming based on the figure 5. We still have NOR formed, but the TB, BB, RI, RB, LI and LB respectively as Top Bus, Bottom number of inputs is quadruplicated as a result of Quadded Bus, Right Inverter, Right Buffer, Left Inverter and Left Buffer, modification. Equation 3, 4 and 5 show the rewritten Quadded Figure 3 shows the performed computations to achieve a XOR XOR in Quadded form. - 183gate.

Invert Buffer OR

5

XOR gate. We tested the original XOR circuit, a TMR implementation with single voting, and the Quadded XOR logic. For each of these we conducted our experiments for all four combinations of the input vector and measured the result. In order to influence the circuit we injected one, two or three faults randomly in the design and compared the result

03 of the faulty circuit to the expected result. In our framework

Buffer Invert

Fig. 6. Quadded XOR on nanoPLA

Invert

OR

Buffer

fault injection in all nanowires of the nanoPLA is possible. Each of the faults corresponds to a typical defect in this kind of architecture. In this first experiment we limit ourselves to one single nanoPLA. Defects and faults between differnt tiles will be considered in our future work.

Our fault injector works as follows. For each run on two three random faults are injected in the design by forcing the nanowires to one or zero and running a ModelSim simulation for this special case. This defect defines a stuck at one or

j

2

j

1 zero on wires in the circuit. The fault injector checked the

IIII!III;::::!IIIIIIIII:; jO

golden value of a wire, then flipped the value (stuck-at failure i2 injection) and simulated the faulty circuit again. This is done

1000 times for each circuit and one to three faults. The number of 1000 runs per test case has been shown to be a good number as the results get stable and a significant amount of different

o fault combinations in different wires is tested. Moreover the setup guarantees that each single junction is tested once at least. Finally 1000 runs still give a reasonable runtime for the simulation.

Buffer Invert OR

Fig. 7. TMR implementation on nanoPLA. Gray wires show the voter implementation.

A. Quadded Form

In a similar way to the XOR, one can implement the Quadded XOR form shown in Figure 6.

In order to obtain the Quadded gate, one has to quadrupli­cate inputs in the top bus and buffer them, and then send them to the circle of nanoPLA. As earlier noted, this circle included four position. Top-Left(invertinglbuffering lines), Down­Left(Programming OR lines), Down-Right(inverting/buffering lines) and Top-Left(Programming OR lines).

After buffering inputs in Top-Right position, they are sent to the Down-Right part and are ORed in a proper manner to achieve Quadded Logic properties. Then, in the Down-Right part they are invertedlbuffered and are sent to the Top-Left part, where they are again ORed together to obtain the second level of the design in Figure 5(b). Finally, they are inverted in the Top-Left inverting lines and send them to the outputs.

B. TMR Form

In the saimilar fashion to Quadded form, TMR form of XOR is implemented to be compared to Quadded form concerning defect tolerance. Every XOR logic gate (reconstructed in NOR gates) is triplicated, then a majority voter is inserted to compute the correct result. The voter is rewritten also in NOR form. TMR's implementation on nanoPLA is shown in Figure 7.

Figure 8 shows the experimental results which include availability percentage of an XOR in original circuit, its TMR implementation and the Quadded form for all different input vectors. 3 curves show experiments, which are done respectively for 1, 2, and 3 defects each time.

In the first curve, 1 defect is inserted in every simulation of the circuit. It means that, one nanowire is defective in every simulation and the result is checked for correctness. For Quadded form, correction is done for all single defects as the curve shows and the availability is reported to be 100%. TMR achieves between 80% and 90% depending on the input value which is mainly caused by the voter as it is a single point of failure. The original implementation is correct in 10% to 25% depending on the input vectors.

In the second curve, experiments are repeated for 2 defect injections in every simulation. The correctnes of the original circuit increases to 20% to 40% caused by two compensating faults. The TMR reliability decreases because two copies can be affected at the same time. Quadded logic is still able to correct up to 90% of the defects.

In the third curve, Quadded form still gives a correct result for up to 80% for the test cases. Interestingly TMR gives almost the same result as the simple XOR implementation.

VI. DISCUSSION

By using different input vectors, different availability per­centages were found, reported by our fault injector. It is due to the partial fault correctness feature of XOR logic gate. For example, when two input vectors have a different value, the output value is always one. Now, if both of inputs are faulty and change the value (one to zero and vice versa), the output will still remain the correct value. In our results can also be seen that different input vectors result in different availabilities

V. EXPERIMENTAL RESULTS of the circuit in the existence of defects. To assess the reliability of the Quadded form, our primary As Figure 8 shows, Quadded logics are able to tolerate

study focuses on three different implementations of a simplel84against single defects in all cases based on our experiments

� 100 � 9O t=��==��= � 80

W r----------------------------­oo t----------------------------­� t-----------------------------40r----------------------------­W r-----------------------------20 t==���::--�� ::::::�����== 10

0_' '_0

'00 90 80 70 00 �

-40 W ........ 20 ........... 10

0_0 0_' '_0

90 80 70 00

� .... 40

"., W

20 ... --'0

0_0 0_' '_0

�Original

�TMR

Input 1_1 distributions

6

lOefect 2 Defects 3 Defects

Fig. 8. Availability percentage of an XOR in original circuit, TMRed and Quadded form vs. different input distributions. Experiments are done for I, 2, and 3 defects each time. In different distribution of inputs, different availability percentage was found, reported by our fault injector.

and also the proof in [18]. As shown, TMR is unreliable as the number of defects increases. As already noted, voter in TMR is a single point of failure which hugely effect the reliability.

In large scales, Quadded logics are able to make designs high-reliable. As mentioned before, this paper presents the idea of using Quadded NOR logics in nanoPLA and discusses the benefits of Quadded NOR logics on nanoPLAs. NOR logic gates can be used to implement more complex systems and Quadded logics are more reliable when there are more levels between designed NOR gates. More information on this issue and also on reliability analyses of Quadded NOR logics can be found in [17].

In comparison to the conventional logic mapping on nanoPLA [6], our method allows for faster mapping. It is not needed the process of test and characterization of nanoPLA. Quadded method tolerates all single defects and most of multiple defects in design. This will be discussed and analyzed in our future steps.

VII. CONCLUSION AND FUTURE WORK

In this paper, we detailed designs which use emerging, bottom-up synthesis techniques to map logic designs on nanoPLAs in a reliable manner. In the presented methodology, we used Quadded NOR logics to guarantee system function for all single defects and most of the multiple ones. We used Quadded NOR logics because they are suitable for nanoPLA based on its OR-Inversion-Buffer structure. We also used wrapped mapping feature of nanoPLAs in order to optimize area overhead. Next steps of the work could be analytical evaluation of yield in the presence of Quadded logics on nanoPLA. We implemented Quadded NOR on nanoPLA in VHDL and injected faults and proofed the method.

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