Energy Minimization Feedback Loop for Ripple Carry Adders

Mohammad Fawaz Nader Kobrosli Jessica Rizakallah Mohammad Mansour Ali Chehab Ayman Kayssi Hazem Hajj

Department of Electrical and Computer Engineering American University of Beirut

Beirut 1107 2020, Lebanon {mbf02, nak31, jer01, mm14, chehab, ayman, hh63}@aub.edu.lb

Abstract— We present a technique and related system implementation for minimizing energy consumption in ripple carry adder blocks, and we show simulation results for the various system blocks. The method includes a tracking loop which measures the energy consumed by the load and controls, through a DC-DC converter, the supply voltage of the load. The energy consumption of the adder is calculated for a range of inputs in order to verify the efficiency of the tracking loop. Results corresponding to an 8-bit ripple carry adder show that energy savings of the order of 50%-100% are expected to be obtained when all the blocks of the circuit are running together. The system is simulated using HSPICE and Verilog-A.

I. INTRODUCTION Minimizing energy consumption of battery-powered

digital systems has become a major concern in today’s industry since energy efficiency affects the size, weight, and operation of such systems. It also affects the amount of time the battery lasts between charges. These constraints are critical in many applications. Sub-threshold operation of digital devices promises an order of magnitude reduction in power dissipation over above-threshold approaches. In subthreshold operation, the circuits are operated at a supply voltage level below the threshold voltage of its devices. However, energy efficiency comes at the cost of circuit speed [1–3].

Minimum energy point (MEP) is the operation supply voltage of a certain circuit at which the consumed energy is minimized. This paper presents a method allowing the supply voltage to be at the MEP by tracking the energy consumption of the circuit and adjusting the supply voltage accordingly.

II. THEORY BEHIND MINIMUM ENERGY POINT

The total energy consumed in a digital circuit is the sum of the active energy and the leakage energy. The active energy is proportional to VDD

2, where VDD is the supply voltage. On the other hand, the leakage energy has an exponential form and decreases rapidly with VDD. Therefore, the total energy will present a minimum point (see Fig. 1.) Finding this point allows us to minimize the energy consumption in any digital circuit. However, this minimum

point is not fixed. As explained in [4], the minimum point depends on several factors such as temperature and the effective switched capacitance per operation. This capacitance depends on the workload or activity of the circuit. Hence, by monitoring the consumed energy of a digital circuit (i.e. the workload of the circuit), we can determine the MEP and force the supply voltage to be at that point. Any change in the load implies a new MEP and a new setting for the supply voltage.

III. MINIMUM ENERGY FEEDBACK LOOP

In order to determine the MEP, a feedback system is used. The minimum energy feedback loop has three major blocks: the energy estimation block, the energy minimization algorithm block, and the DC-DC converter, in addition to the load (see Fig. 2.) The load in our case is an 8-bit ripple carry adder surrounded by D-latches at all inputs and outputs. A. Energy Estimation Block

This block takes as input the voltage supplied to the load (voltage across Cload in Fig.2) at two different instants: before and after load operation. These two voltages (V1 and V2 ) are stored using two capacitors (C1 and C2). The energy consumed by the load is the energy lost in Cload during the load operation i.e. E = 0.5Cload (V1

2 −V22 ), which can be

approximated by CloadV1(V1 −V2 ) since V1 and V2 are very close to each other. To find a normalized version of this quantity, C1 is discharged slowly while a counter is operating as long as V1 is still higher than V2. When this condition fails, the counter stops, and we obtain a normalized value for V1 −V2. This result is then multiplied by V1. Since Cload is constant, it is not included in the normalized value of energy. B. Energy Minimization Algorithm

After estimating the energy E consumed by the load for a set of operations, we compare it with Emin, the energy previously computed. If E < Emin the supply voltage is increased by a constant voltage Vstep. Otherwise, it is decreased by Vstep.

C. DC-DC Converter

This block receives the value of the voltage supply that provides minimum energy operation from the energy

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minimization algorithm block and adjusts the value of the voltage across Cload to that obtained from the Energy Minimization Algorithm, by converting the battery voltage.

IV. EXPERIMENTAL SETUP

The circuit was simulated using HSPICE and Verilog-A. Verilog-A is the analog version of Verilog. Verilog-A blocks can be imported into any HSPICE netlist as behavioral sub-circuits for circuit simulation. The Energy Estimation Block is built using circuit elements in HSPICE with one Verilog-A sub-circuit representing the counter. The Energy Minimization Algorithm block is modeled using Verilog -A. The DC-DC converter was also modeled using Verilog-A. The load is modeled at the circuit level in HSPICE; it is a MOSFET 8-bit adder and several D-latches around it to clock the circuit.

V. SIMULATION RESULTS

Each block of the loop is simulated by itself and the results are as follows: The Energy Estimation Block is tested by verifying that the counter is counting as long as the voltage across C1 is higher than the voltage across C2. Two different voltages are first stored in C1 and C2 and then C1 is allowed to discharge through as cascode load while the counter is working. Figure 3 shows the operation of this block: the counter starts incrementing at the instant the load starts operating, and it stops once the voltage across C1 drops below the voltage value across C2. The normalized value of the energy is equal to the last value reached by the counter multiplied by V1.

The Energy Minimization Algorithm is relatively simple and easy to test. The output voltage depends on the old target voltage and on both the currently - and the previously - estimated energy. The DC-DC converter block was also simulated and tested using Verilog-A.

The 8-bit adder is simulated using HSPICE by applying all possible combinations of input test vectors. The process technology used to build the adder is the 65nm PTM model [5], with a nominal supply voltage of 1 V and a threshold voltage of 0.22 V. The output is verified and the energy consumption for different vectors and different supply voltages are computed.

VI. CONCLUSION

In this paper, we presented an implementation in HSPICE and Verilog-A of a technique for minimizing energy consumption in battery-powered systems. The method is based on tracking the consumed energy and changing the load supply voltage accordingly. The feedback loop included several blocks that were tested separately.

VII. ACKNOWLDGMENT This work was supported by Intel’s Middle East Energy Efficiency (MER) Research Program.

REFERENCES [1] Y. Ramadass and A. Chandrakasan, “Minimum energy tracking loop

with embedded DC-DC converter enabling ultra-low-voltage operation down to 250 mV in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 256-264, Jan. 2008.

[2] A. Wang and A. Chandrakasan, “A 180-mV subthreshold FFT processor using a minimum energy design methodology,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310–319, Jan. 2005.

[3] C. Kim, H. Soeleman, and K. Roy, “Ultra-low-power DLMS adaptive filter for hearing aid applications,” IEEE Transactions on VLSI Systems, vol. 11, no. 6, pp. 1058–1067, Dec. 2003.

[4] B. H. Calhoun and A. Chandrakasan, “Characterizing and modeling minimum energy operation for subthreshold circuits,” in Proc. ISLPED, 2004, pp. 90-95.

[5] Predictive Technology Models website: http://www.eas.asu.edu/~ptm/

Fig. 3. Energy per operation for a typical digital circuit

Fig. 1. Minimum energy tracking loop Fig. 2. Energy estimation block simulation

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