2010 International Conference on Enabling Science and Nanotechnology (ESciNano), 1-3 December, 2010, KLCC, MALAYSIA

Student Paper

A New Single Electron Tunneling Cell Based on Linear Threshold Gate

Davoud Bahrepour*a and Mohammad Javad Sharifib

a Science and Research Branch, Islamic Azad University, Tehran, Iran. b Faculty of Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran.

*Email: bahrepour@ieee.org

The continuing scaling down and miniaturization of CMOS devices has led researchers now

to build new devices with very small dimensions (nanotechnology), whose behavior will be

interpreted based on quantum mechanics. Single electron devices (SEDs) [1] promise excellent

potential for future ultra large scale integrated (ULSI) circuits due to their potential for low power

consumption and their small size. Considerable effort has been expended over the past decade, or

so, in the understanding of the physical principles of SED operation and then different structures

and topologies are proposed for implementing logic gates as applications of them. One of these

structures is the linear threshold gate (LTG) which is introduced in [2] and is characterized with

more details in [3] (Fig. 1 (a)). The presented threshold gate, however, does not operate correctly

in a complex network due to the passive nature of the circuit. For solving this problem the output

of the threshold gate should be augmented with a SET buffer/inverter (Fig. l(b)) [4].

The purpose of this paper is to introduce a single electron tunneling (SET) cell based on LTG for applications in complex circuit designs. Fig. 2 shows the proposed LTG cell which

comprises four L TGs along with four SET inverters. The proposed cell accepts three signals as its

inputs and produces three-input NAND, NOR, XOR and Majority function as its output. In this

paper also a new method for implementing a three-input XOR function is introduced. The XOR

function may be achieved by Eq. 1:

aEE>bEE>c= Minority (Nand(a,b,c), Nor(a,b,c), Majority(a,b,c)) (1)

The output of a Minority function is logic 1 when the majority of inputs are logic 0 and the

output is logic 1 when the majority of inputs are logic o. A full adder accepts three input signals and produces a sum and a carry-out output. Hence, the proposed cell can be considered as a full

adder separately due to its embedded three-input XOR function, which implements sum, and

Majority function, which implements carry-out. In addition, this cell presents NAND and NOR

output functions which has the property of functional completeness. That is, any other logic

function (AND, OR, etc.) can be implemented using only NAND or NOR functions. For instance

a three-input OR function may be achieved by Eq. 2:

a+b+c= NAND (NOT(a), NOT(b), NOT(c)) (2)

In the SET based circuits commonly two important issues are not considered or discussed.

First, fan out of a designed gate circuit and second the passive nature of a circuit. Therefore,

cascaded SET based designs may not work properly because the next stage may not be driven by

previous stage. One of the advantages of the proposed cell is that any logic function can be

implemented by cascading appropriate number of cells. In other words, it can be utilized in

complex circuit design implementations as a main block and because each LTG is augmented

with an inverter (buffer) that restores the output signals for applying to the next stage inputs,

hence any cascaded designs are practical and work properly. By the use of SIMON simulator [5]

the correct operation of the proposed cell is illustrated. Fig. 4(a) shows the eight possible

combinations of input signals which are applied to the cell and Fig. 4(b), (c), (d) and (e)

demonstrate the output for NAND, NOR, Majority and XOR output results respectively.

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2010 International Conference on Enabling Science and Nanotechnology (ESciNano), 1-3 December, 2010, KLCC, MALAYSIA

References [1] K. K. Likharev, "Single-Electron Devices and Their Applications," Proceeding o/the IEEE,

vol. 87, No. 4, pp. 606-632, April 1999.

[2] C. Lageweg, S. Cotofana, S. Vassiliadis, "A Linear Threshold Gate Implementation in Single

Electron Technology," IEEE Computer Society Workshop on VLSI, pages 93-98, April 2001.

[3] C. Chen, Y. Mao, "A Statistical Reliability Model for Single-Electron Threshold Logic,"

Electron Devices, IEEE Transactions on, vol. 55, no. 6, pp. 1547-1553, June 2008.

[4] J. R. Tucker, "Complementary digital logic based on the Coulomb blockade," J. Appl. Phys.,

vol. 72, pp. 4399-4413, Nov. 1992.

[5] C. Wasshuber, H. Kosina, S. Selberherr, "SIMON - A Simulator for Single-Electron Tunnel

Devices and Circuits," IEEE Transactions on Computer-Aided Design, Vol. 16, pp. 937-944,

Sep. 1997. Vb ---11------,

Cb V PI ---11--r----I

CPI VPl ---1 : � ;C,,! Vj Vp,�'� (p, Vnl ---11--r--+---oVOUI

C,' v" ---1 : : .Cd

�" ----4� c" r

(a)

v,

f--------,- v"'

(b)

Fig. 1. (a) SET generic linear threshold gate.

(b) SET buffer inverter implementation.

b

b

b

(a)

Programmable Cell

(b)

Nand (a,b,c) Nor (a,b,c) Maj (a,b,c) Xor (a,b,c)

Fig. 2. (a) proposed cell circuit based on

LTG. (b) The block diagram.

� 0.0 15 r::-::---=-�;;;;;;;;;;;;;;;;;;;;;;;;;;;;;��--"""';;;;w;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;ii-;;o.;; .................... �;;m;;��'--�--Oi'P�;;n;; .... 2 0.01 � 0.005 -c: 0 ���---il"---

0 2 3 4 (a)

5 6 7 8

� ��:L-r_---L�_---L; _---L-f _--.J�_--Li _--1-: _�\ =J�-z 0 2 3 4 5 6 7

(b) �002[ a::: 0.01 � 0

o \- - r --

2 T

3

-,

4 (e)

5 6

8

--J 7 8

5'

i ��: f�==,==="====f..I_- �\ �t------L--i -----L-i- ----11 :E 0 5' 0.02i � 0.01 r - --X 0

o

2 I L_ I

2

3

-\ 3

4 (d)

4 (e)

Time (ns)

5 6 7 8

\ I

J __ -����_�_�L�_� __ �Li __ --� 5 6 7 8

Fig. 3. (a) Applied inputs that V1L =OV, VIH=16mV. (b), (c), (d) and (e) The cell output waveforms

for the three-input NAND, NOR, Majority and XOR gates respectively. The LTG characteristics

are: Vb=16mV, Cpl=Cnl= 0.5aF, Co=9aF and CTJ=O.laF. The SET inverter characteristics are:

Cl=C4=0.laF, C2=C3=0.5aF, C5=9aF, Cb=4.23aF, Cg=0.5aF and Vs=16mV.

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