A low power high density double edge triggered flip flop for low voltage systems

Satish Chandra Tiwari, Kunwar Singh and Maneesha Gupta Advanced Electronics Lab, Division of ECE, NSIT,

Sector-3, Dwarka, New Delhi 110075, India satishtiwari01@gmail.com; kunwarprince333@gmail.com; maneeshapub@gmail.com

Abstract— The paper introduces a new low power, high density double edge triggered, (DET) flip-flop. The proposed DET flip-flop is implemented using lesser number of transistors as compared to other state of the art double edge triggered flip-flops designs. Simulation at 250MHz frequency using 180nm/1.8V CMOS technology with BSIM 3v3 parameters, the proposed design shows an improvement of upto 58.63%, 55.7% and 39.9% in terms of power dissipation, power delay product and total transistor width respectively. At scaled voltages, the power consumption of the proposed design reduces by 34% and hence the design is suitable for low power, low voltage and high density applications.

Keywords— Flip-Flops, low voltage, power delay product, VLSI.

I. INTRODUCTION As the demand for portable battery operated computing

devices with longer battery life, low cost and high speed increases, there is a constant need of new circuit designs to fulfil these requirements. Since digital VLSI integrated circuits are considered to be a combination of interconnected logic gates and Flip Flops (FFs), choosing appropriate Flip Flop topology is of fundamental importance [11]. Moreover these systems use clock signals to sample and store the input data through FFs synchronously. Since clock signal is needed for the synchronization of large number of digital components, the clock load increases substantially. The clock network alone dissipates 30-70% of the total system power dissipation [1], hence reduction in power dissipation due to clock load has been a major area of emphasis for digital system designers. In the same context, digital system designers developed double edge triggering (DET) flip-flops, by virtue of which the power dissipation can be reduced to half while maintaining same data rate [2,3]. The double edge triggered flip-flop samples data on both rising and falling edges of clock, hence clock frequency with an efficiency of 50% in single edge triggered (SET) flip-flop now has 100% efficiency in double-edge triggered flip-flops.

In this paper a new DET flip-flop is proposed which is realized with only fifteen transistors which is three transistor less than DET flip-flop proposed by M. Pedram, Q. Wu, and X. Wu [4] and one transistor less than DET flip-flop proposed

by R. Hossain, L. D. Wronski, and A. Albicki [5]. Moreover, total transistor width of the proposed design obtained after optimization is significantly lesser than that of DETFF proposed in [4] and [5], along with a substantial reduction in power delay product.

The remaining paper is organized as follows. Section II states the standard power and performance metrics. Section III outlines the previously proposed flip-flops investigated in this paper along with a description of the proposed design. Section IV describes the simulation test bench, optimization techniques and the parameters used for simulation. Section V illustrates the simulation results. Finally, the discussion and conclusions are summarized in Section VI.

II. STANDARD POWER AND PERFORMANCE METRICES

A. Power characterization The dynamic power consumption in a circuit is determined

by [6] [7]

Pd=C*VDD2*f (1)

C is the load capacitance VDD is the power supply voltage f is the operating frequency. The dynamic power consumption is dependent on switching activities at various nodes of the circuit. It varies with different data rates and circuit topologies. Hence to obtain a fair idea of power dissipation by a circuit, different data patterns have been applied with different activity rates [8]. The data sequences chosen for this purpose were (i) 0000 (x=0); (ii) 1111(x=0); (iii) 1010 (x=1); (iv) 1100 (x=0.5); (v) Pseudorandom sequence (1111010110010000) where x is the activity factor. The results were evaluated for 16 clock cycles long data sequences.

B. Timing characterization The logic level of the data input has to be maintained

constant just before and after the rising (falling) edge of the clock. The time interval for which it has to be maintained constant before the triggering edge clock edge is called set up time (Tsetup). Similarly the time interval for which the data is maintained constant after the triggering edge of clock is called

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DOI 10.1109/ARTCom.2010.64

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hold time (Thold) [7]. Violation of either of these results in metastability. The time difference between the triggering edge of the clock and output logic level transition is called Tclk-q. There is another parameter Td-q delay or (Tsetup+Tclk-q) which determines the minimum clock period in master slave flip-flop structures. Stojanovic and Oklobdizija [8] proposed that it is Td-q and not Tclk-q which determines the real performance of flip flops, because it also takes Tset-up into account, which is positive for master slave flip-flop configurations. For our analysis, we have chosen D-Q delay as performance parameter of flip-flops.

C. Power delay product There is always a tradeoff between power dissipation and

propagation delay of a circuit. If we optimize a circuit for power its delay increases and vice-versa. Hence to achieve an optimum trade off we considered the power, delay and total transistor width values where power delay product (PDP) is minimum. The designs presented in this paper were simulated to achieve minimum power (pseudorandom data sequence power) *delay (Td-q) product.

Moreover transistor count and total width are also included to maintain a fair level of comparisons.

III. PREVIOUS DESIGNS The double edge triggered flip-flop shown in Fig. 1 was

proposed by M. Pedram, Q. Wu, and X. Wu [4]. This flip-flop is basically a Master Slave flip-flop structure. The architecture consists of two data paths, an upper data path and a lower data path. The upper data path consists of a negative edge triggered (SET) flip-flop implemented using transmission gates (TG) as latches. The lower data path consists of a positive edge triggered flip-flop implemented using TG as latches. Moreover both the data paths have feedback loops connected such that, whenever the clock is stopped/grounded, the logic level at the output is retained so as to maintain the static functionality.

Fig. 1. DETFF proposed by M. Pedram, Q Wu, X Wu [4]

The flip flop is implemented using eighteen transistors. The design has a high clock load. Although the design is better in terms of performance, the additional capacitance introduced by feedback loops leads to more area and power consumption. The flip flop shown in Fig. 2 was proposed by R. Hossain, L. D. Wronski, and A. Albicki [5]. This flip-flop is similar to flip-flop in Fig. 1 except the fact that pass transistors (NMOS) are used in upper and lower data path as latches and the

feedback loop consists of an inverter together with a PMOS. This flip-flop configuration uses only 16 transistors, which is

Fig. 2. DETFF proposed by R. Hossain, L. D. Wronski, A.

Albicki [5] two transistors less than the flip-flop proposed by M. Pedram, Q. Wu, and X. Wu[4]. Although the design uses less transistors, the driving capability is less because of the use of pass transistors as latches instead of TG, which results in increased Td-q latency.

Fig. 3. Proposed design

The proposed design is shown in Fig. 3. The structure is

based on master slave configuration. It has two data paths, the upper data path consisting of TG1, INV1 and TG2; the lower data path consisting of TG3, INV2 and TG4. The input data is connected to TG1 and TG3 and the output is taken from INV3 whose input is in turn connected with TG2 and TG4. A feedback transistor NM1 (NMOS) is employed as a switch such that its one end is connected with output ‘Q’ and other to an intermediate node ‘X’ in upper data path. The transmission gates (TG) in both the data path are clocked such that upper data path works as negative edge triggered flip flop and lower data path works as positive edge triggered flip flop. The novelty of the proposed lies in the feedback strategy used to make the design static using a single pass transistor as a switch through loop L1. When the clock is grounded, the logic level at the output is maintained by the regenerative action of the loop L1 which has two inverters INV1 and INV3 in the forward path and a switch NM1 in the feedback path.[12] The

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main advantages of the proposed design are reduced transistor count, increased performance and low power consumption.

IV. SIMULATION Simulation parameters used for comparison are shown in

Table 1 below:-

TABLE I

CMOS SIMULATION PARAMETERS 0.18 um CMOS Technology Min. Gate Width 2um Max. Gate Width 22um MOSFET Model : BSIM 3v3 Level 53 Nominal Conditions : Vdd =1.8V T=25° C Capacitive Load Cl (FO14) = 21fF

Clock Data

(1) Duty Cycle 50 % N/A (2) Risetime 100ps 100ps (3) Falltime 100ps 100ps (4) Frequency 250MHz N/A (5) Sequence Length N/A 16 clock cycles

Fig. 4. The simulation test bench

Test bench for this analysis is shown in Fig. 4. In actual practical scenario, the flip-flop is connected between two logic blocks such that the input to it comes from output of a preceding block, and the output is connected to input of another succeeding block. Hence the driving capability of the flip-flop as a whole is optimized such that it can drive the next stage efficiently without any performance degradation. In order to obtain accurate results, buffering inverters are used to provide realistic clock and data signals at the clock and data inputs of the flip flop respectively. A fan out of fourteen minimum sized inverters (FO14) is used as capacitance load at the output node Q. This capacitance is estimated to be 21fF [9] [10]. A sequence of 16 clock cycle long pseudorandom

data signals with an activity factor of 18.75% [8] is applied at input for average power measurements.

A. Optimization For optimization, first the critical path is identified. The

widths of the transistors on the critical path are optimized with in the specified range (2um to 22um) for minimum clk-Q delay and total power using Levenberg-Marquardt optimization algorithm embedded in SPICE. Widths of the transistors which are connected in feedback paths are kept minimum. In the next step, optimum Td-q is obtained by sweeping the data edge towards the clock edge. In next step, minimum Td-q is replaced as delay parameter, and flip flops are optimized for minimum PDPd-q using an iterative procedure.

V. RESULTS

The optimal power results are summarized in Fig. 6. The proposed design dissipates 20% and 58.63% lesser power when compared with DETFF[5] and DETFF[4] respectively. At maximum switching activity again the proposed flip-flop dissipates 34% and 47% lesser power as compared to DETFF[5] and DETFF[4] respectively. The simulation results indicate that the proposed flip flop has least power dissipation among all the designs for any data pattern.

Fig. 6. Power results

Table III (A)

CELL Transistor

Count Total width

(um) Power (uw)

DETFF[4] 18 104.12 1690 DETFF[5] 16 126 877 Proposed Design

15 75.72 877

Table III (A) and Table III (B) illustrate that the proposed design has minimum transistor count. Moreover when compared in terms of total transistor width the proposed

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design has an improvement of 39.9% and 27.27% as compared to DETFF[5] and DETFF[4] respectively. The tables also indicate that the proposed design has an improvement of 21% and 57% in terms of PDPd-q as compared to DETFF[5] and DETFF[4] respectively making this design suitable for

Table III (B)

CELL Td-q

[ps] PDP d-q [fJ]

Improve-ment % in PDPd-q

Improve- ment % in Total Width

DETFF [4]

356 640 55.7% 27.27%

DETFF [5]

410 359.57 21% 39.9%

Proposed Design

405 283.09

systems where both power dissipation and performance are critical. The power supply voltage is considerably reduced for low power battery operated systems. Although the nominal power supply voltage used for simulation is 1.8 at 180nm technology, comparisons are carried out even at scaled power supply voltages (VDD is scaled from 1.8V down to 1V). Same simulation test bench is used and the results are shown in Table IV. It is observed that power consumption decreases as we scale supply voltage. DETFF[5] fails at 1.2V whereas the proposed flip flop functions up to 1V and has improvement of 34% for scaled power supply voltages.

Table IV

TOTAL POWER Vs SUPPLY VOLTAGE

CELL 1.8V

1.6V

1.4V

1.2V

1V

Improve- ment % at 1V

DETFF[4]

1690 (uW)

1230 (uW)

836 (uW)

532 (uW)

297 (uW)

34%

DETFF[5]

877 (uW)

670 (uW)

493 (uW)

fail-ed

fail-ed

NA

Propos-ed

Design

699 (uW)

542 (uW)

403 (uW)

291 (uW)

196 (uW)

VI. DISCUSSION AND CONCLUSION

The paper proposes a new design of static master slave double edge triggered flip-flop. Comparisons were made with other state of the art double edge triggered flip-flop designs. The flip flops were investigated using standard parameters, optimization techniques and extensive simulation procedures. Power results depict that proposed flip-flop has improvement of 20% and 58.63% in terms of total power dissipation when

compared with DETFF[5] and DETFF[4] respectively. The proposed design also shows appreciable results with 21% and 55.7% percent improvement in terms of power delay product as compared to DETFF[5] and DETFF[4] respectively. More over the proposed design has an improvement of 39.9% and 27.27% in terms of total transistor width over DETFF[5] and DETFF[4] respectively, which makes the proposed design suitable for low power, high density applications. The designs were also simulated at scaled voltages and the results indicate that the proposed design in ideally suited for low power, high density systems operating at low voltages.

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