Ieee 2009 Vlsi Projects

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IEEE 2009 VLSI Projects

A Fully Pipelined Architecture for the LOCO-I Compression Algorithm for images_Sim

A Low-Complexity Hybrid LDPC Code Encoder for IEEE 802.3an (10GBase-T) Ethernet

A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise in images_Sim

A Multibank Memory-Based VLSI Architecture of DVB

A Parallel Pruned Bit-Reversal Interleaver

Adaptive Frequency-Domain Channel Estimator in 4X4 MIMO-OFDM Modems

Adaptive IIR Filtering of Noncircular Complex Signals

An Efficient 4-D 8PSK TCM Decoder Architecture

Design of Voltage Over scaled Low-Power Trellis Decoders in Presence of Process Variations

Injecting Intermittent Faults for the Dependability Validation of Commercial Microcontrollers

Joint Optimization of Run-Length Coding, Huffman Coding, and Quantization Table With

Complete Baseline JPEG Decoder Compatibility_simUnspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test

Generation





A New VLSI Architecture of Parallel Multiplier±Accumulator Based on Radix-2 Modified Booth Algorithm

IEEE 2010

An Efficient Implementation of Flip±Flops With EmbeddedLogic

IEEE 2010

Hazard-Based Detection Conditions for Improved Transition

Fault Coverage of Scan-Based Tests IEEE 2010

Design Space Exploration of Hard-Decision Viterbi Decoding:Algorithm and VLSI Implementation

IEEE 2010

Accurate Predictive Interconnect Modeling for System-Level

DesignIEEE 2010

A Fast Heuristic Algorithm for Multidomain Clock SkewScheduling

IEEE 2010

A Reverse-Encoding-Based On-Chip Bus Tracer for EfficientCircular-Buffer Utilization

IEEE 2010

A Low-Area Multi-Link Interconnect Architecture for GALS

Chip Multiprocessors IEEE 2010

A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies

IEEE 2010

Self-Repairing SRAM Using On-Chip Detection and

CompensationIEEE 2010

A Novel Architecture for Block Interleaving Algorithm in MB-OFDM Using Mixed Radix System IEEE 2010

A SCALABLE SDH/SONET FRAMER ARCHITECTURE ON

VLSI TECHNOLOGYIEEE/Application

BLIND SOURCE SEPARATION BASED ON DUETALGORITHGM IEEE/Application

COMBINATION OF FPGA AND ZINBEE IN WIRELESSDATA TRANSMISSION IEEE/Application

A Fully Pipelined Architecture for the LOCO-I CompressionAlgorithm for images_Sim

IEEE 2009

A Low-Complexity Hybrid LDPC Code Encoder for IEEE

802.3an (10GBase-T) EthernetIEEE 2009

A Low-Cost VLSI Implementation for Efficient Removal of

Impulse Noise in images_SimIEEE 2009

A Low-Jitter Open-Loop All-Digital Clock Generator WithTwo-Cycle Lock-Time

IEEE 2009

A Multibank Memory-Based VLSI Architecture of DVB IEEE 2009

A Parallel Pruned Bit-Reversal Interleaver IEEE 2009

Adaptive Frequency-Domain Channel Estimator in 4X4 MIMO-OFDM Modems

IEEE 2009



Adaptive IIR Filtering of Noncircular Complex Signals IEEE 2009

An Efficient 4-D 8PSK TCM Decoder Architecture IEEE 2009

Asynchronous Current Mode Serial Communication IEEE 2009

Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication

IEEE 2009

CMOS Driver-Receiver Pair for Low-Swing Signaling for LowEnergy On-Chip Interconnects

IEEE 2009

Design and Implementation of a Field Programmable CRC

Circuit ArchitectureIEEE 2009

Design of Network-on-Chip Architectures With a Genetic

Algorithm-Based TechniqueIEEE 2009

Design of Voltage Over scaled Low-Power Trellis Decoders inPresence of Process Variations

IEEE 2009

Design Space Exploration of Hard-Decision Viterbi Decoding:Algorithm and VLSI Implementation

IEEE 2009

Energy-Efficient Sub threshold Processor Design IEEE 2009

Fast Scaling in the Residue Number System IEEE 2009

Integrated Solar Energy Harvesting and Storage IEEE 2009

Multi-Gbps LDPC Code Design and Implementation IEEE 2009

Noisy FIR identification as a quadratic eigenvalue problem IEEE 2009

Novel Area-Efficient FPGA Architectures for FIR FilteringWith Symmetric Signal Extension

IEEE 2009

On the Relay Channel With Receiver±Transmitter Feedback IEEE 2009

Optimized Analog flat filter design IEEE 2009

Scalable Multi-Input±Multi-Output Queues With Application to

Variation-Tolerant ArchitecturesIEEE 2009

Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters IEEE 2009

Spectrally Shaped Generalized MC-DS-CDMA with Dual BandCombining for Increased Diversity

IEEE 2008

Single Chip Encryptor Decryptor Core Implementation of AESAlgorithm

IEEE 2008



Serial Search Code Acquisition Using Smart Antennas with

Single Correlator or Matched Filter IEEE 2008

Practical Asynchronous Interconnect Network Design IEEE 2008

Fast Elliptic Curve Cryptography on FPGA IEEE 2008

A Novel Approach to Design BCD Adder and Carry Skip BCDAdder

IEEE 2008

A Novel Carry-look ahead approach to an Unified BCD andBinary Adder_Subtractor

IEEE 2008

Injecting Intermittent Faults for the Dependability Validation of

Commercial MicrocontrollersIEEE 2008

Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation

IEEE 2008

IEEE 2009 VLSI Projects

Spectrally Shaped Generalized MC-DS-CDMA with Dual Band Combining for Increased

Diversity

Single Chip Encryptor Decryptor Core Implementation of AES Algorithm

Serial Search Code Acquisition Using Smart Antennas with Single Correlator or Matched Filter

Practical Asynchronous Interconnect Network Design

Fast Elliptic Curve Cryptography on FPGA

A Novel Approach to Design BCD Adder and Carry Skip BCD Adder

A Novel Carry-look ahead approach to an Unified BCD and Binary Adder_Subtractor

Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores

Cost-Effective Triple-Mode Reconfigurable Pipeline FFT_IFFT_2-D DCT Processor

General Design Issues of Sliding-Mode Controllers in DC±DC Converters

Multilevel Multiphase Space Vector PWM Algorithm

A Space Vector PWM Scheme for Multi frequency Output Voltage Generation With MultiphaseVoltage-Source Inverters



sion

System-On-Chip based Projects

Architecture, Design and Implementation of Speaker recognition system

Architecture, Design and Implementation of FPGA based Video gaming system

Architecture, Design and Implementation of FPGA based Paint brush hardware system

Architecture, Design and Implementation of UDP protocol in hardware

Architecture, Design and Implementation of Motion tracking system

Architecture, Design and Implementation of Audio spetialization system

Architecture, Design and Implementation of Internet based Music player

Architecture, Design and Implementation of Digital Picture Framer

Architecture, Design and Implementation of Picture Viewer

Architecture, Design and Implementation of Digital Voice record player

Architecture, Design and Implementation of Digital camera system

Architecture, Design and Implementation of Internet based camera system

Architecture, Design and Implementation of Speech synthesizer

Architecture, Design and Implementation of mp3 player

Architecture, Design and Implementation of Webserver

Architectural design and Implementation of iPod

IEEE VLSI Projects

Efficient FPGA Implementation of Modified DWT for JPEG2000 (IEEE - 2008)

Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime

An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors

System-Level Specification Testing Of Wireless Transceivers



Hardware Implementation of 1D Wavelet Transform on an FPGA for Infrasound Signal

Classification (IEEE - 2008)

FPGA Design of Fast Lifting Wavelet Transform ( IEEE - 2008)

A New Fast Architecture for HD H.264 CAVLC multi-syntax Decoder and its FPGA Implementation

( IEEE - 2007)

The Architecture of Fast H.264 CAVLC Decoder and its FPGA Implementation (IEEE - 2007)

Efficient Wavelet Transform on FPGA Using Advanced Distributed Arithmetic (IEEE - 2007)

FPGA Prototyping Strategy for a H.264/AVC Video Decoder ( IEEE - 2007)

An Efficient Wavelet Image Encoder for FPGA-based designs (IEEE - 2005)

FPGA Implementation of High Speed Parallel Architecture for Block Motion Estimation ( IEEE -

2004)

Design and FPGA Implementation of Non-separable 2D Biorthorgonal wavelet tranforms for

Image/Video Coding ( IEEE - 2004)

Rapid FPGA Prototyping of Gabor- Wavelet Transform for Applications in Motion Detection ( IEEE -

2002)

Xilinx FPGA Implementation of Image Classifier for Object detection applications ( IEEE - 2001)

An FPGA based Wavelet transform coprocessor ( IEEE - 2001)

An Efficient FPGA Implementation of a Wavelet Coder/Decoder (IEEE - 2000)

FPGA Implementation of 2D Wavelet Transform ( IEEE - 1999)

Video compression on FPGA based custom computers ( IEEE - 1997)

An efficient FPGA implementation of the OS-CFAR processor

FPGA implementation of fully parallel fast MDCT algorithm

Design and FPGA implementation of finite Ridgelet transform [image processing applications]

Image analysis and partitioning for FPGA implementation of image restoration

Research on Image Median Filtering Algorithm and Its FPGA Implementation

Design of 600Mbps 4×2 MIMO-OFDM Wireless LAN System and Its FPGA Implementation

FPGA Implementation of an Efficient 3D-WT Temporal Decomposition Algorithm for Video

Compression

FPGA implementation of a re-configurable fft for multi-standard systems in software radio context



Novel FPGA implementations of Walsh-Hadamard transforms for signal processing

An FPGA implementation of an all digital phase locked loop for control applications

FPGA implementation for an optimized CORDIC module for OFDM system

FPGA Implementation of Real-Time Edge-Preserving Filter for Video Noise Reduction

FPGA Implementation of a Fast MDCT Algorithm

FPGA Implementation of Viterbi Decoders for MIMO-BICM

Advanced VLSI Projects

Architecture, Design and Implementation of edge detection algorithm

Architecture, Design and Implementation of basic Graphics Processor

Design and Implementation of Audio Spectrogram system

Design and Implementation of 3-D mesh generator

Design and Implementation of Image tracer

Architecture, Design and Implementation of Digital camera

Implementation of real-time Color detection using CCD image sensor

Implementation of real-time Sound detection

Implementation of real-time Audio Effects

Real-time generation of audio based Disco Ball

Real-time generation of audio based Discolights

Implementation of Real-time video effects

Remote controlled Karaoke machine

Implementation of encryption and deencryption

Implementation of AMBA Bus protocol

Standard VLSI Projects

Intruder detection using Image sensors

Design and Implementation of Stereogram generation



Implementation of Audio (WAV) Player

Implementation of Audio (WAV) Recorder

Architecture, Design and Implementation of Image smoothing algorithm

Architecture, Design and Implementation of Image convolution algorithm

Architecture, Design and Implementation of lossless image compression algorithm

Design and Implementation of Discrete Cosine Transform

Design and Implementation of Variable Length Coding (VLC)

Architecture, Design and Implementation of pipelined simple 8-bit processor

Architecture, Design and Implementation of simple 8-bit processor

High-performance and High-efficiency DDR3 SDRAM controller

High-performance and High-efficiency DDR2 SDRAM controller

High-performance and High-efficiency DDR SDRAM controller

High-performance and High-efficiency SDR SDRAM controller

SDCard memory controller

Basic VLSI Projects

FPGA interfacing to CCD image sensor

FPGA interfacing to Ethernet

FPGA interfacing to SDR SDRAM

FPGA interfacing to AudioCODEC

FPGA interfacing to PC through RS-232

Implementation of PS/2 protocol (Mouse)

Implementation of code converters

Implementation of Keyboard controller

Implementation of VGA Controller

Implementation of DMA protocol

Implementation of SPI protocol

Implementation of I2C protocol



Implementation of Bus arbiter

Implementation of Quadport RAM

Implementation of Dualport RAM

Implementation of Content-Addressable-Memory (CAM)

Implementation of Asynchronous FIFO

Implementation of Synchronous FIFO

IEEE VLSI PROJECTS e-soft academy

SI.No Project Title Year

1.Joint Optimization of Run-Length Coding, Huffman Coding, and QuantizationTable With Complete Baseline JPEG Decoder Compatibility_sim

IEEE 2009

2.

A Fully Pipelined Architecture for the LOCO-I Compression Algorithm for

images_Sim IEEE 2009

3.A Low-Complexity Hybrid LDPC Code Encoder for IEEE 802.3an (10GBase-T)Ethernet

IEEE 2009

4.A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise inimages_Sim

IEEE 2009

5.A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time

IEEE 2009

6. A Multibank Memory-Based VLSI Architecture of DVB IEEE 2009

7. A Parallel Pruned Bit-Reversal Interleaver IEEE 2009

8. Adaptive Frequency-Domain Channel Estimator in 4X4 MIMO-OFDM Modems IEEE 2009

9. Adaptive IIR Filtering of Noncircular Complex Signals IEEE 2009

10. An Efficient 4-D 8PSK TCM Decoder Architecture IEEE 2009

11. Asynchronous Current Mode Serial Communication IEEE 2009

12. Asynchronous Protocol Converters for Two-Phase Delay-Insensitive GlobalCommunication

IEEE 2009

13.CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-ChipInterconnects

IEEE 2009

14. Design and Implementation of a Field Programmable CRC Circuit Architecture IEEE 2009

15.Design of Network-on-Chip Architectures With a Genetic Algorithm-BasedTechnique

IEEE 2009

16.Design of Voltage Over scaled Low-Power Trellis Decoders in Presence of Process Variations

IEEE 2009

17. Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and IEEE 2009



VLSI Implementation

18. Energy-Efficient Sub threshold Processor Design IEEE 2009

19. Fast Scaling in the Residue Number System IEEE 2009

20. Integrated Solar Energy Harvesting and Storage IEEE 2009

21. Multi-Gbps LDPC Code Design and Implementation IEEE 2009

22. Noisy FIR identification as a quadratic eigenvalue problem IEEE 2009

23. Novel Area-Efficient FPGA Architectures for FIR Filtering With SymmetricSignal Extension

IEEE 2009

24. On the Relay Channel With Receiver±Transmitter Feedback IEEE 2009

25. Optimized Analog flat filter design IEEE 2009

26.Scalable Multi-Input±Multi-Output Queues With Application to Variation-Tolerant Architectures

IEEE 2009

27. Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters IEEE 2009

28.Spectrally Shaped Generalized MC-DS-CDMA with Dual Band Combining for

Increased DiversityIEEE 2008

30. Single Chip Encryptor Decryptor Core Implementation of AES Algorithm IEEE 2008

31.Serial Search Code Acquisition Using Smart Antennas with Single Correlatoror Matched Filter

IEEE 2008

32. Practical Asynchronous Interconnect Network Design IEEE 2008

33. Fast Elliptic Curve Cryptography on FPGA IEEE 2008

34. A Novel Approach to Design BCD Adder and Carry Skip BCD Adder IEEE 2008

35.A Novel Carry-look ahead approach to an Unified BCD and BinaryAdder_Subtractor

IEEE 2008

36.Injecting Intermittent Faults for the Dependability Validation of CommercialMicrocontrollers

IEEE 2008

37.Unspecified Transition Faults: A Transition Fault Model for At-Speed FaultSimulation and Test Generation

IEEE 2008

Documents

Ieee 2009 Vlsi Projects