Low-Voltage Cascode Current Mirror based on Bulk-Driven MOSFET and FGMOS

techniques

Abstract—In this paper, low voltage cascode current mirror based on bulk-driven MOSFET (operating in linear region) and floating-gate MOSFET are presented. The proposed circuits are simulated using SPICE for 0.25 µm CMOS technology and their results are compared with that of conventional cascode current mirror.

Keywords—low voltage, cascode current mirror, bulk-driven

MOSFET, FGMOS

I. INTRODUCTION

Nowadays, need for reducing power supply to IC circuits

has assumed great importance with the shrinking dimension in VLSI technology along with new fabrication trends. This presents a great challenge to CMOS Analog /Mixed signal circuit design. Also, the lowering of threshold voltage (VT) is not directly proportional with reduction in the feature size of modern CMOS circuit design [1].

In conventional analog circuit design, the fundamental limitation for reduction of supply voltage is given by (1). Equation (1) infers that the power supply must be at least equal to the sum of magnitudes of p-type and n-type threshold voltages [1]. |VDD-VSS| ≥VtN+|Vtp| (1)

Where, VDD and VSS are positive and negative supply voltages and VtN and Vtp are threshold voltages of NMOS and PMOS respectively.

Many new techniques have been developed to overcome this limitation and achieve low voltage CMOS analog circuits, viz; MOSFETs operating in Sub- Threshold region, Bulk-Driven MOSFETs, Self-Cascode Structure, Floating-Gate MOSFET (FGMOS) Approach and Level Shifter techniques [2].

A Bulk-Driven Cascode Current Mirror working in saturation region is presented in [4]. Here in this paper, low-voltage modified Cascode Current Mirror has been proposed

based on Bulk-Driven MOSFET approach (operating in linear region) and based on FGMOS approach.

The paper is organized as follows: In section II, the operation of Bulk Driven MOSFET is described. Section III, deals with the working of FGMOS. In Section IV, Cascode Current Mirror (CCM) is explained. In section V, low voltage CCMs based on bulk-driven MOSFET and FGMOS are proposed. Finally, the simulation results and comparison of these techniques is given in section VI.

Fig. 1. Cross-section of a PMOS transistor and terminal voltages for bulk driven operation

Vb Vin

VDD

VSS

Fig. 2. Bulk-driven MOSFET structure

Bhawna Aggarwal Electronics and Communication Engg. Department, Maharaja Agrasen Institute of Technology, Rohini Sec.22, New Delhi-110086. Email : kbhawnagarg@yahoo.co.in, ph: +91-9911565959

Maneesha Gupta Electronics and Communication Engg. Department, Netaji Subhash Institute of Technology, sector-3, Dwarka New Delhi-110078 Email : maneesha_gupta60@yahoo.co.in, ph: +91-9873333861

2009 International Conference on Advances in Recent Technologies in Communication and Computing

978-0-7695-3845-7/09 $25.00 © 2009 IEEE

DOI 10.1109/ARTCom.2009.83

473

2009 International Conference on Advances in Recent Technologies in Communication and Computing

978-0-7695-3845-7/09 $26.00 © 2009 IEEE

DOI 10.1109/ARTCom.2009.83

473

2009 International Conference on Advances in Recent Technologies in Communication and Computing

978-0-7695-3845-7/09 $26.00 © 2009 IEEE

DOI 10.1109/ARTCom.2009.83

473

II. BULK-DRIVEN TRANSISTOR

In bulk-driven MOSFET, wells are required to isolate the bulk terminals and if both NMOS and PMOS are required, then a twin-well technology has to be used [3]. A Cross-section of P-Channel MOSFET in N-well CMOS technology is shown in Fig 1. The current in a conventional gate-driven MOSFET is obtained when the applied gate bias overcomes the threshold voltage [2].However, in a bulk-driven MOSFET, VGS (gate to source voltage) is kept constant [1], by applying a biasing voltage at the gate terminal, as shown in Fig 2, and the input is applied at the bulk terminal. Functionally seen, a bulk-driven MOSFET behaves like a JFET [2]. Thus, a bulk-driven MOSFET operates as a depletion type device where the bulk terminal functions as the gate terminal of the virtual JFET and modifies the width of the channel according to the applied voltage. Being a depletion type device, it can work under negative, zero or even slightly positive biasing conditions.

Generally the substrate potential in a MOSFET is equal to the source potential, i.e., VSB (source to substrate voltage) = 0. But in some cases, the source potential of an NMOS can be larger than the substrate potential. This results in a positive source-to-substrate voltage, i.e., VSB > 0. In such a case, threshold voltage VT includes the substrate bias terms and can be defined as [6]:

( )FSBFTT VVV φφγ 220 −++= (2)

Where, VT0 is the threshold voltage when VSB=0, γ is the bulk threshold parameter and ФF is the strong inversion surface potential.

Substituting this value of VT in the conventional drain current equation of the n-channel MOSFET in saturation region, we get [5]:

20 )22(

2)( FBSFTGSD VVVsatI φγφγβ +−−−= , (3)

VDS > VGS - VT

Where, β is the transconductance parameter given as:

LWCoxnμ

β = (4)

Where µn is the electron mobility, Cox is the gate-oxide

capacitance per unit area, W is the effective channel width and the L is the effective channel length.

The channel conductance of the bulk-to-source junctions gmbs is defined as: \

BSF

D

BSF

m

BS

Dmbs

V

I

V

gVI

g−

=−

=∂∂

=φ

βγ

φ

γ

22

2

22 (5)

Where, gm is the channel transconductance of the gate-to-

source junctions.

III. FLOATING GATE MOSFET (FGMOS)

The structure of a typical n-channel, N-input FGMOS is shown in Fig. 3. Its structure is similar to that of a conventional MOSFET except that there is an additional floating gate in FGMOS, which is electrically isolated within the oxide layer. The additional floating gate offers almost infinite input impedance. Threshold voltage of FGMOS can be suitably altered and hence it can be used to realize low-voltage circuits. The voltage on its floating gate (VFG) can be written as [7]:

T

N

iFGBSfbSSfsDSfdGSi

FG C

QVCVCVCVCV

∑=

++++= 1 (6)

Where, ∑=

++++=N

iNi CCCCC

1321 ....... are the input

capacitances between control gates and floating gate, Cfd, Cfs and Cfb denotes the capacitances from floating-gate to drain, source and bulk respectively, VDS is the drain-to-source voltage, CT is the total capacitance of the floating-gate and QFG is the residual charge. The total capacitance is given as:

Fig. 3. Stucture of an n-input FGMOS MOSFET

(a) (b) Fig. 4. FGMOS (a) Symbol (b) Equivalent circuit

model

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∑=

+++=N

ifbfsfdiT CCCCC

1 (7)

The residual charge may be trapped at the floating gate

during the fabrication process and can be neglected using method suggested in [8]. Therefore (6) reduces to:

T

N

iBSfbSSfsDSfdGSi

FG C

VCVCVCVCV

∑=

+++= 1 (8)

⎪⎪

⎭

⎪⎪

⎬

⎫

⎪⎪

⎩

⎪⎪

⎨

⎧

⎟⎠⎞

⎜⎝⎛−

⎟⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜⎜

⎝

⎛

−⎟⎟⎠

⎞⎜⎜⎝

⎛+⎟

⎟⎠

⎞⎜⎜⎝

⎛+⎟

⎟⎠

⎞⎜⎜⎝

⎛+

⎟⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜⎜

⎝

⎛

=∑= 21

21

DSDSTBST

fbSS

T

fsDS

T

fdGS

T

N

ii

ODS VVVV

C

CV

C

CV

C

CV

C

CI β

(9)

2

12

⎪⎪

⎭

⎪⎪

⎬

⎫

⎪⎪

⎩

⎪⎪

⎨

⎧

−⎟⎟⎠

⎞⎜⎜⎝

⎛+⎟

⎟⎠

⎞⎜⎜⎝

⎛+⎟

⎟⎠

⎞⎜⎜⎝

⎛+

⎟⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜⎜

⎝

⎛

=∑=

TBST

fbSS

T

fsDS

T

fdGS

T

N

ii

SDS VV

C

CV

C

CV

C

CV

C

CI β

(10)

The drain current equations in the ohmic and saturation region for the n-channel FGMOS are given in (9) and (10). These equations have been obtained by modifying the conventional n-channel MOSFET equations.

Assuming, ∑=

>>N

ifbfsfdi CCCC

1,, , (9) & (10) can be

approximated as:

⎪⎪

⎭

⎪⎪

⎬

⎫

⎪⎪

⎩

⎪⎪

⎨

⎧

⎟⎠⎞

⎜⎝⎛−

⎟⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜⎜

⎝

⎛

−

⎟⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜⎜

⎝

⎛

=∑= 21

21

DSDSTGST

N

ii

ODS VVVV

C

CI β (11)

2

12

⎪⎪

⎭

⎪⎪

⎬

⎫

⎪⎪

⎩

⎪⎪

⎨

⎧

−

⎟⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜⎜

⎝

⎛

=∑=

TGST

N

ii

SDS VV

C

CI β (12)

The symbol and equivalent circuit for an N-input, FGMOS are shown in Figs. 4(a) and (b) respectively, where Gi (for i=1, 2… N) are the control inputs and D, S and B are the drain, source and substrate, respectively.

IV. CASCODE CURRENT MIRROR A conventional gate-driven cascode current mirror is shown in Fig. 5. Here if (W/L)2/(W/L)1 = (W/L)4/(W/L)3 then, VGS2 = VGS1 and hence VX = VY. Where W/L represents the aspect ratio of the MOSFET and VX and VY are the voltages at node X and Y respectively. This relation holds even if M1 and M2 suffer from body effect. Though cascode current mirror consumes substantial voltage headroom as compared to a simple current mirror, it gives higher accuracy with high output impedance [9].

V. LOW VOLTAGE CASCODE CURRENT MIRROR A. Bulk-driven PMOS CCM in linear region: A low voltage Bulk-driven PMOS, CCM working in linear region is proposed in Fig. 6. Here the gate terminals of all the PMOS transistors are connected to a fixed voltage Vb1 (usually

IOUT

M6

M4

VY

M2

VX

M3

M1

M5

VDD

VSS

Fig. 5. Gate-Driven Cascode Current Mirror

Fig.6. Bulk-Driven Cascode Current Mirror

M3

M1 M2

M4

M6 M5

Vb1 Vb1

Vb1

Vb2

Vb1

IOUT IIN

VDD

VSS

475475475

VSS). This voltage must be greater than or equal to |VT| to form the conduction channel between source and drain terminals. Here, N-well (the bulk of PMOS) terminal is used to apply the input instead of gate terminal, as is done in case of gate-driven MOSFET. In Bulk-driven PMOS VSB has to be kept below the switch-on voltage of diode (formed between bulk and source terminals) else a large amount of the MOSFET drain current will be lost in bulk terminal as leakage current. Bulk currents of M1 and M3 can be reduced if they are operated in linear region as their bulk-to-source junctions are already forward-biased.

For a bulk-driven MOSFET the dependence of drain current ID in linear region is given as:

SDVSDVFBSVFTOVSGVDI ⎥⎦⎤

⎢⎣⎡ −+−−−=

2122 φγφγβ

(13)

Now from Fig. 6, we can get, VSB1 = VSD1, VSB3 = VSD3, VSB3 = VSB4, and VSD4 = VSD3+ VSB1- VSB2 or VSD4+ VSB2 = VSD3+ VSB1. Since M1 and M3 are operating in linear region and due to above mentioned conditions M2 and M4 will also operate in linear region due to which IOUT is forced to match with IIN.

B. FGMOS based Cascode Current Mirror:

A low voltage CCM based on FGMOS is shown in Fig. 7. Here M1, M2, M3 and M4 are two input FGMOS. In these MOSFET’s, one gate terminal is used as normal input terminal and a biasing voltage is applied at the second gate terminal to form the conduction channel between source and drain terminals. Here also like a simple gate-driven CCM if (W/L)2/(W/L)1 = (W/L)4/(W/L)3, then, VGS2 = VGS1 and hence VX = VY. This forces same current in both the branches and IOUT becomes equal to IIN. Also, in this circuit all the MOSFET’s are working in saturation region.

Thus, in FGMOS based CCM same current equation is obtained at low voltage, as compared to gate-driven CCM, but

it occupies more silicon area due to multiple polysilicon layers required for the fabrication.

TABLE I COMPARISON OF CASCODE CURRENT MIRRORS BASED ON THREE

TECHNIQUES Parameters Simple

CCM Bulk-Driven

CCM FGMOS

CCM Voltage ±1.5V ±0.6V ±0.45V Power 2.33X10-3 5.58X10-4 9.65X10-5

Input Resistance 7.67X102 7.66X103 1.99X103 Output Resistance 8.1X104 5.72X103 1.53X105

Range 0-350µA 20-90µA 0-150µA Region of operation of

MOSFET Saturation Linear Saturation

iin

0A 20uA 40uA 60uA 80uA 100uA 120uA 140uA 160uA 180uAI(vout) I(iin)

-100uA

0A

100uA

200uA

iin

0A

50uA 100uA 150uA 200uA 250uA 300uA 350uA

400uA 450uA 500uAI(vout) I(iin)

-200uA

0A

200uA

400uA

600uA

iin

0A 20uA 40uA 60uA 80uA 100uA 120uAI(vout) I(iin)

0A

40uA

80uA

120uA

Fig. 9. Simulation of Bulk-Driven CCM

Fig. 7. FGMOS Cascode Current Mirror

IOUT IIN

VY VX

VSS

M6 M5

M3

M1 M2

Vb1

Vb1

VDD

M4

Fig. 8. Simulation of Simple CCM

Fig. 10. Simulation of FGMOS CCM

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VI. SIMULATION RESULTS The proposed low voltage CCMs are simulated using SPICE of 0.25um CMOS technology. The simulation results of all the three techniques are shown in Figs. 8, 9 and 10. The comparison of all the three CCMs is tabulated in Table I. As can be seen from the table, conventional CCM works at higher supply voltage of ±1.5V. Bulk-driven CCM is one of the good alternatives as the required supply voltage here is ±0.6V. But here the range of operation is limited to 20-90uA. In this regard FGMOS based CCM is better than bulk-driven CCM as the supply voltage required is even lesser approx. ±0.45V and range of operation is 150uA. However, the silicon area occupied is greater than that of bulk-driven CCM.

V. CONCLUSIONS

Two different approaches of achieving low voltage CCM using bulk-driven MOSFET and FGMOS have been presented. The simulations for the proposed circuits were carried out using SPICE of 0.25um technology and their results were compared with that of conventional CCM and suitability of low voltage CCM based on FGMOS was found.

VI. REFERENCES

[1] B. J. Blalock, and P.E. Allen. “Low-Voltage, Bulk-Driven MOSFET Current Mirror for CMOS Technology,” IEEE ISCAS I995, vol. 3, pp. 1972-1975, 1995.

[2] S. S. Rajput, and S. S. Jamuar, “Low Voltage Analog Circuit Design Techniques,” IEEE CAS Mag., vol. 3, no. 1, pp. 24-42, 2002.

[3] Y. Haga, H. Zare-Hoseini, L. Berkovi, and I. Kale, “Design of a 0.8 Volt fully differential CMOS OTA using the bulk- driven technique,” Proc. ISCAS 2005, IEEE International Symposium, vol. 1, pp. 220–223, May 2005.

[4] Z. Zhu, J. Mo, and Y. Yang, “A Low voltage Bulk-driving PMOS Cascode Current Mirror,” 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008, pp. 2008-2011, Oct. 2008.

[5] P. E. Allen, and D. R. Holberg, CMOS Analog Circuit Design, 2nd ed., New York: Oxford University Press, 2004, pp.73-89.

[6] S. Kang, and Y. Leblibici, CMOS Digital Integrated Circuits, 3rd ed., New Delhi: TataMcGraw-Hill, 2003, pp. 94-114.

[7] S. T. Wang, “On the I-V characteristics of Floating Gate MOS transistors,” IEEE Trans. Electron Devices, ED-26, pp. 346 – 348, 1974.

[8] E. Rodriguez-Villegas, and H. Barnes, “Solution to trapped charge in FGMOS transistors,” IEE Electronic Letters, vol. 39, no.19, pp. 1416 –1417, September 2003.

[9] Behzad Razavi, Design of Analog CMOS Integrated Circuits, New Delhi, Tata McGraw-Hill, 2002, pp. 139-145.

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