A Wide Bandwidth SiGe Broadband Amplifier for 100 Gb/s Ethernet Applications

Tonmoy S. Mukherjee, Duane C. Howard, John D. Cressler and Kevin T. Kornegay

School of Electrical and Computer Engineering, 777 Atlantic Drive N.W., Georgia Institute of Technology, Atlanta, GA 30332-0250 USA

Abstract — We present a low-voltage, low-power

SiGe broadband amplifier with a bandwidth of 62 GHz, which is intended for use in 100 Gb/s Ethernet applications. The amplifier consumes only 125 mW from a 2.5 V supply. To the authors’ knowledge this is the lowest reported power for a non-distributed amplifier with more than 60 GHz bandwidth in a SiGe process technology.

Index Terms — CDR, Cherry-Hooper, low-power,

low-voltage, SiGe, 100 Gb/s, wireline.

I. INTRODUCTION

Broadband amplifiers are an important circuit block in wireline systems. Lumped element based designs are generally favored for these applications since the same topology can be used as either a limiting amplifier or as low gain broadband amplifier to buffer internal data, with both applications then only requiring changes of component values [1]-[8]. With the constantly increasing demand for higher internet bandwidth, 100 Gb/s optical communication systems (100 Gb/s Ethernet) are the next big push in the wireline community. Since performing the front-end tasks in the optical domain is both expensive and cumbersome, an all-electrical front-end would be a more economical solution. To make the system robust as well to reduce power consumption and complexity, we are targeting an injection-locked Clock and Data Recovery (CDR) system for 100 Gb/s Ethernet. With this aim in mind, a library of individual circuit components all implemented in a commercially-available 130 nm, 200 GHz fT SiGe process, is under development. These SiGe 100 Gb/s digital blocks are based upon a Low Voltage Logic (LVL) family specifically designed to reduce power consumption [9], and for compatibility, these SiGe amplifiers have been designed to operate with a supply voltage of 2.0-2.5V. In this paper we present a 62 GHz bandwidth lumped element SiGe broadband amplifier, a key block in this 100 Gb/s component library. The amplifier is intended to be used as a data buffer for critical internal nodes in the CDR, as well as function as the requisite Limiting Amplifier, after a few minor modifications.

II. CIRCUIT IMPLEMENTATION

The block level diagram of the amplifier is shown in Fig. 1, and consists of three stages with emitter-follower (EF) buffers placed in between each stage. Each amplifier stage is implemented as a modified Cherry-Hooper (C-H) architecture. The amplifier is intended for true differential operation, with a differential input and output. The chip requires a 2.5 V supply and on-chip resistors are used to provide 50 Ω input matching.

Fig. 1. Broadband amplifier block diagram showing the Cherry-Hooper and emitter-follower stages.

A. Design Techniques

The target application as an internal buffer relaxes the gain requirement, which has been traded off with power consumption while trying to maintain a high bandwidth. Low power consumption is achieved by reducing the supply voltage from 3.3V to 2.5V. However, this reduces the headroom of the C-H tail current source. To alleviate this problem, the HBT tail current source is replaced by a high aspect ratio MOSFET which has a lower headroom requirement. Additionally, cascaded emitter-followers, which are typically used to decouple amplifier stages at high frequencies was replaced by single emitter-followers for reduced power consumption. To achieve the maximum possible bandwidth, the principle of maximum impedance mismatch has been utilized, along with true differential operation and on-chip matching [10]. This mismatch is achieved by alternating transadmittance (TAS) and trans-impedance (TIS) stages to form the C-H amplifiers. Shunt peaking is used to extend the bandwidth [11]. The peaking inductances were chosen to be greater than that

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Fig. 2. Amplifier Circuit Diagram

required for maintaining maximally flat bandwidth.

B. Amplifier Architecture

The three-stage amplifier is shown in Fig.2 displaying each C-H stage along with associated single emitter follower stages. A modified differential Cherry-Hooper architecture [2] was used to implement the amplifier stages, as shown in Fig. 3. The C-H amplifier consists of a TAS and a transimpedance TIS stage. The cascading of the TAS-TIS stages allows for the maximum mismatch between them and hence enhances the bandwidth.

Fig. 3. Modified Cherry-Hooper amplifier stage. The purely resistive feedback of a traditional C-H

amplifier has been modified here by the inclusion of an emitter-follower in the feedback path. The emitter-follower serves to minimize feed-forward effects and also provides inductive peaking, both of which help to increase the overall amplifier bandwidth. In addition, this architecture mitigates the voltage headroom problem in the TAS stage.

The collector resistance has been split into R1 and R2, and boosts the gain by (1+R1/R2) without affecting the circuit bandwidth significantly, provided that 0<R2/R1<2.5 [2]. Shunt peaking is utilized in all stages of the amplifier to further enhance the bandwidth [11]. Peaking inductors were implemented with transmission lines, with the signal line as the 7th (top) metal layer and the 1st metal layer as the bottom plane.

We deliberately decided to not include a dedicated output buffer to drive 50 Ω loads, in spite of the resulting low gain. This decision was influenced by the fact that it might be impossible to accurately de-embed the response of the output buffer and to subsequently be able to accurately characterize the performance of the amplifier itself.

C. Layout

The chip micrograph is shown in Fig. 4. The layout has been made perfectly symmetrical, with very short interconnects. All interconnects, including via stacks, have been modeled with Ansoft HFSS. To minimize parasitics and keep the signal paths as short as possible, the overlap of the RF and the DC paths have been largely avoided. Although this leads to an extremely compact layout, the tradeoff is that the DC supply must be provided from both sides of the chip.

III. MEASUREMENT AND RESULTS

Good agreement between simulated and measured DC operating conditions was achieved. The total chip draws 50 mA of current from a 2.5 V supply.

A. S-Parameter Measurements

Single-ended two-port scattering parameter measurements were performed using an Agilent 8510C Network Analyzer with frequency extension modules to increase the measurement range up to 110 GHz.

R2 R2

R1 R1

QfQf

Q3

Q4Q1

Q2

Rf Rf

VCC

EFEF

R2 R2

R1 R1

QfQf

Q3

Q4Q1

Q2

Rf Rf

VCC

EFEF

R2 R2

R1 R1

QfQf

Q3

Q4Q1

Q2

Rf Rf

VCC

EF

EF

50

IPPIPN

50

OPP OPN

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Fig. 4. Micrograph of the SiGe broadband amplifier.

The measured S-parameters from 1-100 GHz, with an input power of -18 dBm, are shown in Fig. 5. This figure shows a mid-band gain of 5 dB with a bandwidth in excess of 60 GHz. Fig. 6 shows that S11 is below -14 dB for the entire band of interest.

Fig. 5. Measured S21 data.

Fig. 6. Measured S11 data.

Since single-ended measurements were performed, 6 dB was added to S21 to obtain a mid-band differential gain of approximately 5 dB. This is about 3dB lower than the post-layout extraction simulated gain. There are two possible reasons for this observed difference:

1) to reduce parasitics, the layout was made symmetric and compact by avoiding the crossing of DC and RF paths. Hence to properly bias the chip, the same supply must be provided to both sides of the chip. Because of equipment limitations, the measurement setup provided bias to only one side of the chip, resulting in an asymmetric biasing to the two arms of each differential pair; and 2) large MOSFETs were used as tail current sources for the differential pairs to enable low voltage operation. This leads, however, to a degradation of CMRR, which has a lower impact on circuit performance in true differential operation but degrades performance for single-ended operation (S-parameter measurements) which is compounded with the asymmetric biasing condition

B. Time Domain

Due to the unavailability of a pattern generator operating above 12.5 Gb/s, we were unable to measure the chip at 100 Gb/s speeds. Hence, shown in Fig. 8 is the post layout extraction simulated eye diagram of the chip operating at 100 Gb/s. This post layout simulation result is validated by the measured S21 result, which shows a bandwidth in excess of 60 GHz, adequate for a data rate of 100 Gb/s.

Fig. 8. Simulated eye diagram for a data rate of 100 Gb/s.

IV. SUMMARY

A broadband SiGe amplifier designed in a 130 nm, 200 GHz fT SiGe process is presented for application to 100 Gb/s Ethernet. The amplifier achieves a mid-band differential gain of 5 dB across a bandwidth in excess of 60 GHz, with a power consumption of 50 mA from a 2.5 V supply. To our knowledge, this is the lowest reported power consumption for a 60 GHz broadband amplifier. Table I compares this amplifier with some notable work. It can be noted that the present work significantly improves the power and bandwidth performance compared with previously reported results.

50mV/div 5ps/div

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TABLE I

COMPARISONS WITH OTHER BROADBAND DESIGNS Author Results BW

[GHZ] Gain [dB]

Supply [V]

PWR [mW]

[1] R. Krithivasan, 2005

24 42 -5 550

[3] W. Perndl, 2004

62 16 -5 770

[4] K. Ohhata, 1999

32.7 19 -7.5 725

This work 62 5 2.5 125

ACKNOWLEDGEMENTS

The authors wish to thank Akil K. Sutton, Dr. W. M. Lance Kuo, and T. Thrivikraman. for their contributions.

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Lu, J. D. Cressler, A. J. Joseph, “A 24 GHz Broadband SiGe HBT Limiting Amplifier,” IEEE BCTM, pp. 208-211, Oct. 2005.

[2] Y. M. Greshishchev and P. Schvan, “A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBTlimiting amplifier,” IEEE BCTM, pp. 293-296, Sept. 2004.

[3] W. Perndl, W. Wilhelm, H. Knapp, M. Wurzer, K. Aufinger, T. F. Meister, J. Bock, W. Simburger, A L. Scholtz, “A 60 GHz broadband amplifier in SiGe bipolar technology,” IEEE BCTM, pp. 293-296, Sept. 2004.

[4] K. Ohhata, T. Masuda, E. Ohue, and K. Washio, “Design of a 32.7-GHz bandwidth AGC amplifier IC with wide dynamic range implemented in SiGe HBT,” IEEE JSSC, vol. 34, pp 1290-1297, Sept. 1999.

[5] N. Ishihara, O. Nakajima, H. Ichino, Y. Yamauchi, “9 GHz bandwidth, 8-20 dB controllable-gain monolithic amplifierusing AlGaAs/GaAs HBT technology,” Electron Lett., pp. 1317, Sept. 1989.

[6] A. Maxim, “A 3.3V 10Gb/s SiGe limiting transimpedance amplifier using a pseudo-differential input and a limiting Cherry-Hooper stage,” IEEE RFIC. Dig., pp. 313-316, June 2005.

[7] E.M. Cherry and D. E. Hooper, “The design of wide-band transistor feedback amplifiers,” IEEE Proc., vol. 110, pp 375-389, Feb. 1963.

[8] C. D. Holdenried, J. W. Haslett, M. W. Lynch, “Analysis and design of HBT Cherry-Hooper amplifiers with emitter-follower feedback for optical communications”, IEEE JSSC, vol. 39, no. 11, pp 1959-1967, Nov. 2004.

[9] D. Kucharski and K. T. Kornegay, “2.5 V 43–45 Gb/s CDR Circuit and 55 Gb/s PRBS Generator in SiGe Using a Low-Voltage Logic Family,” IEEE JSSC, vol. 41, no. 9, pp 2154-2165, Sept. 2006.

[10] H. M. Rein, M. Moller, “Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s”, IEEE JSSC, vol. 31, no. 8, pp 1070-1090, Aug. 1996.

[11] T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998.

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