A High Dynamic Range ASK Demodulator for Passive UHF RFID with Automatic Over-Voltage Protection and Detection Threshold Adjustment

Ganesh K. Balachandran and Raymond E. Barnett

Texas Instruments, Inc., 12500 TI Boulevard, Dallas, TX 75287, USA

Abstract- This paper presents a passive UHF RFID ASK demodulator that operates over a +24dBm to -14dBm RF input power range. The demodulator automatically adjusts between high sensitivity mode for weak RF signal power and over-voltage protection mode for high RF power. The input over-voltage protection circuit is designed to protect the IC from high input power while not impacting the sensitivity at weak input power. The demodulator is comprised of a RF rectifier, a variable gain attenuator with automatic threshold adjustment and a nano-power data slicer. The demodulator handles demodulating signals with a minimum to maximum envelope ratio of 0.8 over the entire input power range, and the data slicer consumes only 160nA from a 0.9 to 1.25V rectified supply. The RFID chip is fabricated in a 0.13μm analog-CMOS technology and the entire chip occupies an area of 0.55 mm2.

I. INTRODUCTION

Passive UHF RFID Tags have no battery and operate by receiving both power and data through the RF interface. An integrated RF rectifier converts the incoming RF power to DC power to operate the IC [1] [2] [3]. When the incoming RF signal is weak, in the range of -14dBm, the tag is in high sensitivity mode. In this mode limited power is available and the processing circuits must consume very low power, on the order of a few μW for the entire tag. On the other hand, the tag must also be able to operate and demodulate data during high incoming RF power, as high as +24dBm. During high power, the large open circuit antenna voltage, up to 40V, must be limited at the IC terminals to protect the sensitive deep sub-micron IC that only tolerates 1.5V, in 0.13μm CMOS technology. Therefore, an over-voltage protection circuit is required to limit, but not clip, the RF signal. Since the data is encoded via Amplitude Shift Keying (ASK) modulation, clipping would remove the data modulation and the demodulator would not function. Another critical component in the RFID tag is the data demodulator, which extracts the ASK data from the RF signal. A fixed threshold demodulator, such as given in [2] and [4], is not capable of handling a wide dynamic range and accurately extracting the data information in deep submicron low voltage technology. This work proposes a negative feedback based automatic over-voltage protection circuit to protect the IC during high RF fields but still allow extraction of the amplitude data. Also proposed, is a demodulator with a variable gain attenuator and automatic threshold adjustment, critical to correctly centering the data detector threshold, over the large +24dBm to -14dBm RF input power range.

II. FRONT END ARCHITECTURE

Figure 1 shows the Ultra-High Frequency (UHF) RFID front end used in this work. Unlike a typical RF system where the input RF signal contains only the data, the passive RFID system uses the input RF signal to derive the DC power supply, decipher the incoming data and transmit data using backscatter modulation [1].

Fig. 1 The RFID front-end system architecture

There are two primary receive circuits connected to the

antenna. One derives the supply voltage VDD, called the Power Harvester, and the other deciphers the input data, the Demodulator. For the Power Harvester, the antenna is connected to a Multi-stage Rectifier that converts the incoming RF power to DC and limits and regulates the DC power to produce the on chip DC power supply, VDD. Details of the Power Harvester are given in [5] [6] [7]. This work focuses on the Demodulator and Over-voltage Protection as shown in Fig. 1. The Over-voltage Protection is used to reduce the voltage swing at the chip input and is required in order to protect the deep submicron IC from damaging over-voltages. A single stage rectifier doubler is used to obtain the envelope of the input signal. Following the rectifier is a variable gain attenuator that provides attenuation at high RF power levels. Finally, the data slicer compares the data envelope with respect to a weighted average of the data envelope to determine if the data is a “1” or a “0”. The two main challenges in data detection are the ability to handle RF levels that vary from +24dBm to -14dBm and the ability to handle a wide variety of modulation signals. These will be described in the next two sections, along with how this work solves these problems.

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III. CHALLENGES IN DATA DETECTION OVER WIDE INPUT RF SIGNAL LEVELS AND SOLUTION

Fig. 2 shows the equivalent circuit model at the IC input. The antenna is modeled as a sinusoidal voltage source, VANT, with a resistance, RANT, and capacitance, CANT. A printed shunt inductor is used to resonate out the shunt capacitance at the chip input. The IC input model is represented by a shunt capacitance, CIC, and shunt resistance, RIC.

Fig. 2 Equivalent circuit showing antenna and IC input models

VANT level varies due to several factors including the reader power level, distance between reader and tag, and transmit/receive antenna characteristics. VANT typically varies from 0.5V to 40V. At low levels, a conjugate match is desired between the chip and the antenna for maximum power transfer, this is achieved via rectifier and antenna design. At high levels of RF power, good matching is not desired. A bypass path is required to reflect and/or drain the excess RF energy and protect the IC from damage due to high voltages. This is achieved by an Over-voltage Protection circuit at the chip input, to prevent the voltage from exceeding device ratings. Fig. 3 shows a typical circuit that achieves this function.

Fig. 3 Typical RF limiter circuit that has a fast-attack slow-decay response The Body Diode between the drain and the bulk limits

negative excursions of the RF signal to about 0.7V. For positive RF voltage excursions, the NMOS device is the shunting device that protects the input RF voltage level by providing a low impedance path to GND at high RF input power. The diode connected between the drain and gate of the NMOS transistor provides a fast attack turn on of the NMOS, when the RF pad voltage exceeds the NMOS threshold voltage plus the diode turn on voltage, VTNMOS+VD~0.7+0.7=1.4V. The RC time constant of the slow decay circuit is chosen to be larger than the time for which the modulation pulse is “low” so the circuit does not respond to the data modulation drop out. The slow-decay circuit serves an important function because the demodulation transfer function, the ratio of the peak voltage of the demodulated RF signal to the peak value

of VANT, is very highly non-linear as shown in Fig. 4. For small RF signals, the gain is large and the demodulated voltage difference is large enough to be detected by the data-slicer. Whereas for large RF signals the demodulated voltage is more or less constant to protect the IC from over-voltages, however, the detection voltage is very small and the slicer is required to detect this small voltage.

Fig. 4 The non-linear nature of the demodulator transfer function

Figure 5 illustrates the effect of the fast attack slow decay circuit when modulating between 40V and 8V peak antenna voltage. Without a slow decay time, the demodulated low level is shown in the dashed curve and the difference between the low and high levels is small. By using a slow decay circuit, the difference becomes larger but droops to a smaller difference as time progresses during the low period. This effect is exaggerated in Fig. 5. Therefore, Fig. 5 illustrates that the use of a fast-attack and slow-decay circuit increases differences between the low and high demodulated voltages at the slicer input and thus it is easier to detect data.

Fig. 5 Capturing the RF envelope for a 80% modulation depth with and

without a large (or slow) Limiter decay time For 0.13μm CMOS, the circuit of Fig. 3 is not suitable, because the devices connected to the RF pin are rated for a maximum of 1.8V. The NMOS plus diode requires 1.4V to turn on and an additional 0.5V to turn on to limit the maximum voltage. Therefore this circuit is marginal in terms of its voltage limiting capability, especially with process and temperature variations. The use of a Schottky diode instead of a regular p-n junction diode is also not feasible due to the high reverse bias leakage of the Schottky diode, which causes a faster decay time. An improved version of the Over-voltage Protection is shown in Fig. 6, which shows the entire RF demodulator front end.

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Fig. 6 Proposed automatic over-voltage protection and threshold adjustment circuit

A single-stage Schottky diode rectifier, or doubler, is used along with a MOS diode, MLS, and the limiter device MRF to provide controlled limiting of the antenna voltage. This is shown in the circuit to the left of node B in Fig. 6. The RF peak voltage at the input pad where limiting transistor MRF turns on is obtained from equation (1) by substituting 0.2V (Schottky diode ON state voltage) for Vd, VGS,MRF=0.7V and VGS,MLS =0.9V

MLSGSMRFGSdpeakin VVVV ,,, )(2 +=− (1)

Therefore the value of the peak RF voltage for the clamping action to start is 1V. Similarly, the value of the peak RF voltage at which the clamping action is very strong is obtained by substituting, 1.2V for VGS,MRF. The Vin value thus obtained is 1.25V. The voltage limiting from start of clamping to strong clamping is more controlled, taking place over a range of just 0.25V.

IV. CHALLENGES IN DATA DETECTION WITH VARIOUS

MODULATION SIGNALS AND PROPOSED WEIGHTED AVERAGE DETECTION

In this section the circuits to the right of node B of Fig. 6 are described. This consists of a Variable Gain Attenuator, weighted average circuit consisting of Rb, Rav and Cav, and the data slicer (A2D), shown in both block and schematic form. The input to the variable attenuator is the demodulated signal at node B. The wide dynamic range of the RF is limited by the previously described RF limiter loop. The attenuator further deals with the dynamic range by reducing the common mode input voltage to the data slicer. This is required because the architecture chosen uses a DC coupled input and the comparator, operating from the supply 0.9V<Vdd<1.25, cannot tolerate a high common mode voltage. Also in this work, a weighted average circuit is proposed in place of a typical averaging filter. For a typical averaging filter Rav is removed from Fig. 6, and only a low pass filter consisting of Rb and Cav is used to estimate the threshold. This method works fine for DC free codes, where the high and low values of the demodulated waveform are equally likely. Since the modulation used in the EPC Gen 2 protocol is not DC free, a weighted average is used estimate threshold voltage.

In the simplest ASK RF communication, the presence of RF represents a data-1 and the absence of RF, or reduced level of RF, represents a data-0. However, to ensure that there is always RF energy available to the chip, even when a stream of

data-0’s are transmitted, the pulses representing both data-1 and data-0 are coded to have a certain percentage of their pulse width for which there is RF energy present. In the EPC Gen 2 protocol, the pulses representing a data-1 and a data-0 are pulse interval encoded, as illustrated in Fig. 7.

Fig. 7 Pulse Interval Encoded Data-1 and Data-0

This encoding scheme is attractive because more RF signal is available to power the IC. The RF power is maximized when the PW width is made as short as possible, however, the shorter the pulse width, the harder it is to detect the pulses. Data is encoded by having the data-1 bit longer than the data-0 bit, but shorter than twice the data-0 bit. Even though pulse interval encoding is best for capturing the most RF power for tag operation, generating the proper threshold for data detection in the presence of varying data streams and data rates is challenging when using the pulse interval encoding scheme, as opposed to DC free encoding such as Manchester. Thus pulse interval encoding complicates both the data-slicer design as well as the threshold generation circuit.

Referring back to Fig. 6, the data-slicer compares the demodulated envelope, node C, to its weighted average, node D, formed by Rb, Rav and Cav. The purpose of Rav, is to weight the average towards zero. The reason for this is explained next, first by viewing top waveform of Fig. 8

Fig. 8 Weighted average threshold adjustment

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The top waveform shows the case where the envelope has a long period of high followed by a short pulse low. A normal non-weighted average of this waveform is indicated by the dashed line and is very close to the high level of the waveform. The slicer detecting this level must have a very low offset which is difficult to achieve with only hundreds of nano-Watts of DC power available for the slicer. The bottom two waveforms in Fig. 8 show the results of using a weighted average. The ideal slicer level is half way between the high and low level. The low level is shown as 0V just for reference but is normally higher by several hundred mV. When a stream of all 0’s is sent the slicer threshold shifts down, and when a string of 1’s is sent the threshold shifts up. Since the coding favors the threshold shifting up, the weighted average will shift the threshold down, even if the data coming in is always high. The protocol allows data to be sent at various data rates, lengths of data-0 and data-1, and the pulse width of the low level can be as short as a few μs. This modulation format is the PR-ASK modulation as defined by EPC Gen 2. This is the most problematic modulation for setting the proper slicer threshold, because the signal is high most of the time, and at the same time, the device should be able to operate with normal ASK, with a 50% high to low ratio. This work proposes to use the information contained in the preamble for digitally setting the weighted average filter resistor Rav. The EPC Gen 2 protocol uses a preamble that contains information on the length of a data-1 plus a data-0, and the device can detect whether PR-ASK or normal ASK is used. By choosing the weighted average through information in the preamble, the optimal threshold is chosen for each new data packet by digitally adjusting Rav, as shown in Fig. 6. A final note is the data-slicer is a typical low power dynamic latch as illustrated in Fig. 6. The challenge of optimizing this design is to have low offset of 10’s of mV, while consuming only a few hundred nano-Watts of power.

V. MEASUREMENT RESULTS A scope capture of the internal signals during demodulation is shown in Fig. 9.

Fig.9 Measured demodulator output, average, and CMOS slicer output

The bottom trace shows the chip ground potential, GND. The next two traces from the bottom show the actual Demodulated Data and the Average value, which is centered about the data,

even though the data heavily weighted towards logic high. Next, is the resolution of the data to full CMOS level, or the slicer output. The top traces are the data sent to the RF generator and the trigger signal, shown for reference. The IC was extensively tested to meet the EPC Gen 2 standard as previously reported in [7]. Finally, the chip micro-photograph is shown in Fig. 10, with various blocks noted.

Fig. 10 Chip micro-photograph

VI. CONCLUSION Presented is a passive UHF RFID ASK demodulator

operating over a +24dBm to -14dBm input power range. The demodulator uses automatic over-voltage protection and detection threshold adjustment to operate over the large input power range. It is embedded in a complete RFID chip in 0.13μm CMOS that occupies an area of 0.55 mm2.

ACKNOWLEDGMENTS The authors wish to thank Texas Instruments, Inc. for the

processing, wafers and test equipment for the evaluation of the RFID test chip.

REFERENCES

[1] K. Finkenzelle, RFID Handbook: Radio Frequency Identification Fundamentals and Applications, John Wiley and Sons, 1999.

[2] U. Karthaus and M. Fischer, "Fully integrated passive UHF RFID transponder IC with 16.7 μW minimum RF input power”, IEEE Journal of Solid-State Circuits, vol. 38, pp. 1602-1608, October 2003.

[3] T. Umeda, H. Yoshida, S. Sekine, Y. Fujita, T. Suzuki, and S. Otaka, “A 950-MHz Rectifier Circuit for Sensor Network Tags With 10-m Distance”, IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 35-41, Jan. 2006.

[4] J-P Curty, N. Joehl, C. Dehollain, M. Declercq, “Remotely Powered Addressable UHF RFID Integrated System,” IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 1602-1608, Nov. 2005.

[5] R. Barnett, S. Lazar and J. Liu, “Design of Multistage Rectifiers with Low-Cost Impedance Matching for Passive RFID Tags,” in Dig. IEEE Radio Frequency Integrated Circuits, June 11-13 2006, pp. 291-294.

[6] Ganesh Balachandran and Ray Barnett; “A 110 nA Voltage Regulator System With Dynamic Bandwidth Boosting for RFID Systems”, IEEE Journal of Solid-State Circuits, Volume 41, Issue 9, Sept. 2006 Page(s):2019 - 2028

[7] Ray Barnett, Ganesh Balachandran, Steve Lazar, Brad Kramer, George Konnail, Suribhotla Rajasekhar and Vladimir Drobny, “A Passive UHF RFID Transponder for EPC Gen 2 with -14dB sensitivity in 130nm CMOS”, International solid state circuits conference, 11-15 Feb. 2007, pages 582-583

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