Head in Pillow (HIP) and Yield Study on SIP and PoP Assembly

Dongji Xie, Dongkai Shangguan and David Geiger, Flextronics

2090 Fortune Drive, San Jose, CA 95131, USA

Dinesh Gill, Varatharajan Vellppan, and Karuna Chinniah Flextronics

2736, MUKIM 1, LORONG PERUSAHAAN BARU 2, Penang, MALAYSIA Contact E-mail: Dongji.xie@flextronics.com; Tel: +408 576 7597; Fax: +408 576 7989

Abstract This paper uses a statistical approach to simulate the yield

loss due to HIP (head-in-pillow) based on experimental work including production data. Detailed analyses on the HIP formation and mechanism were performed using Surface Evolver and optical measurement. Stackup analysis using statistical modeling and Monte Carlo simulation is performed to assess the magnitude of yield loss. From this study, it is learned that the warpage of package and PCB, solder paste printing, flux type and solder alloy, all play important roles in HIP formation. Both shadow moiré measurement and finite element analysis (FEA) were conducted to characterize BGA and PCB warpage and offer guidance for effective control of the warpage. Finally, various effective options will be discussed to reduce the HIP defects. Interestingly enough, it is found that BGA warpage need to be controlled but the impact of PCB warpage is more complex. Introduction

System in package (SIP) and Package on Package (PoP) are two innovative array interconnection methods of BGA which enable multiple functional chips and memory modules into one package to meet miniaturization requirements. SIP allows stacked die and integration of different types of devices such as passive and active components which gives more flexibility and testability over System on Chip (SoC). More importantly, the attempts being made by several manufacturers to integrate baseband functions of cell phones such as the baseband engine and memory with numerous passives are likely to shift the routing complexity from the motherboard to the SIP substrate. This move is expected to significantly reduce motherboard complexity and cost [1].

PoP assembly is a key enabler for the never ending drive for smaller, lighter and more advanced features on handheld products [2~5]. Steadily over the past few years, all of the major handset makers and telecommunication system have adopted the PoP configuration. The implementation of SIP and PoP in volume production today is challenging. A SIP package is a giant BGA with a footprint normally more than 50x50mm2 and over 2000 I/O counts. Moreover, the solder joints inside SIP will experience a second reflow. For inline PoP assembly, two thin and large BGAs need to be stacked up and reflowed simultaneously onto the PCB. As compared with a traditional SMT process, the top BGA assembly is not paste printable and usually done by fluxing only. Therefore,

the process control for SIP and PoP is more challenging and the yield may be adversely impacted.

HIP is one of the most common failure modes in BGA board assembly including system-in-package (SIP) and package on package (POP). It is getting more prominent when using leadfree soldering for large form factor BGA and SIP as shown in Fig. 1. HIP is formed because the solder ball could not be melted uniformly with the solder on the PCB pad during reflow. Two main reasons have been proposed: there is an air gap or a contamination surface in-between [5~8]. For either case, the root cause is that the solder ball is not in contact all the time with the soldering pads throughout the reflow processes. One of the critical parameters to govern the gap or contact is the deformation or warpage of component and PCB during reflow.

HIP is a latent defect. Once formed in the solder joints, HIP defects often escape inspection and tests on the factory floor as there may still be mechanical and electrical contact; however, electrical continuity will be lost leading to intermittent failures in the field. If the gap is big enough, HIP can become a solder joint open.

The warpage of BGA is inherent from the molding process for packaging [4-6]. Many studies have been performed to reduce the warpage, including selection of molding materials for BGA, die sizes and substrate thicknesses, etc. There is great interest in the industry to investigate how the warpage of BGA impacts the assembly yield.

This work is aimed at developing models to correlate the BGA warpage and board reject rate due to HIP defects. A gap analysis was performed which takes all elements of SIP and PoP assembly into accounts. Both experimental work and statistical tools are utilized in the work.

Fig. 1 HIP solder joint in SIP assembly.

PoP and SIP Packages The PoP package has two parts: top and bottom BGA.

Details of the components used in this study are listed in

978-1-4244-4476-2/09/$25.00 ©2009 IEEE 752 2009 Electronic Components and Technology Conference

Table 1. BGAs are selected from two suppliers: #1 and #2. The only difference is that the number of I/O for the bottom BGA is slightly different between them. It is believed that these differences will not impact the yield. The detailed assembly processes are described in reference [9]. A typical PoP package is shown in Fig. 2a. The top BGA usually has one or two large dies. The epoxy molding compound is over-molded to the whole length of the body. The bottom BGA usually has a smaller die and two to four rows of solder pads on the top side for interconnections between the top and bottom BGA (Fig. 2b). The corner solder joints are most critical as the package warpage is the highest at these locations. The SIP package is usually a full area array BGA as shown in Fig. 2b. It includes several ICs in BGA format. HIP Yield Model for PoP and SIP It is assumed in this work that open solder defects are formed when a gap exists between the BGA ball and the pad during melting of the solder. A gap exists when the BGA and/or PCB warp to a certain extent. There are typically four cases for warpage as shown in Fig. 3. Case 1 (Fig. 3a) and Case 2 (Fig. 3b) show that the top and bottom BGAs are warped in the same direction. In other words, the warpage of the top and bottom BGAs are compensated by each other. Case 3 (Fig. 3c) and Case 4 (Fig. 3d) show that the top and bottom BGAs are warped in the opposite directions. Obviously, Cases 3 could create a wider gap and therefore has a greater likelihood to produce an HIP defect. Case 4 could create HIP for inner solder joints in some cases but much less for the outer row as the magnitude of warpage is constrained there. Therefore, Case 3 will be the focus of this study. It is also known from the volume production that Case 3 is the worst case. For SIP and a full array BGA, the equivalent case to Case 3 is shown in Fig. 4. The center warpage of the BGA is constrained by collapse of the center ball. The collapse height is controlled primarily by the solder volume and component weight if the pad diameters have been fixed. The surface tension did not impact the height significantly as learnt from the Surface Evolver analysis. The collapse height of the solder in the liquid form can be determined from Surface Evolver [10]. Two cases are studied here: 1) free ball, i.e. the solder ball hangs from the top pad; and 2) solder joint, i.e. the liquid solder is sandwiched by top and bottom pads. Parameters used in the Surface Evolver are listed in Table 2. The solder ball height from the SIP component is shown in Fig. 5. The volume was measured to be 0.1038mm3. The solder volume of the solder joints is the sum of solder ball and the solder from the solder paste. The simulated results of the solder height are illustrated in Fig. 6. It is learnt from Fig. 6 that the solder height from “free ball” is 0.4-0.522mm, which is in line with the nominal value from the measurement (0.528mm) in Fig. 5. The minimum nominal solder joint height is 0.390-0.42mm, which is lower than the “free ball” height. The solder joint height varies with the component weight as shown in Fig. 6. The center solder joints have much higher weight load when the BGA warped in “smiling” surface. On the other hand, the corner joints have no weight

load as they hang in the air. This indicates that the solder joint could reach the lowest height of 0.4mm in the center region and 0.522mm at the corner. These height numbers are important to determine the HIP and shall be discussed again later in this paper. The height of solder contributed from solder paste portion is simulated using Surface Evolver as well. It is determined that the height is about 0.15mm for a solder paste volume of 0.0172mm3 on assumption that the solder metal ratio is 50% by volume (see Fig. 4). The gap of solder joint in a PoP or SIP in Fig. 4 is dependent to the SIP warpage, ball height, PCB warpage as shown in Equation 1:

e=A+H+C-B-S (1) where, e is the gap distance; A is the substrate warpage of top BGA for PoP or SIP;

H is the molding height of the bottom package in the center region for PoP. For a SIP, it is the solder collapse height in the center area.

C is the warpage from bottom BGA (for PoP) or PCB (for SIP);

B is the ball height and S is the solder height from the contribution of solder paste.

For PoP, S=0 if using fluxing only process. It is noted that all items on the right hand side of Equation 1 have variations. The variation of each item can be modeled by random or normal distribution. The gap, e, is then simulated using the Monte Carlo method.

To obtain a good solder joint, e0 is required during the entire reflow processes. A HIP may occur if a gap exists during the peak reflow even though the gap may disappear at the solidification temperature. The reason is that the solder ball does not wet the bottom solder and/or pad completely due to (a) the timing and/or (b) the contaminated interface which is not removable by flux. In some other cases, a HIP may not occur if the gap generated between the melting temperature and the peak reflow temperature may be dissolved completely if the flux is activated sufficiently. Studies by Cho et al [11] have demonstrated that a small gap may be allowed to obtain a good solder joint. It is defined to be about 15um or 0.59mil for fluxing only process in tin-lead alloy application. In this paper, we defined the maximum allowable gap as emax to get a solder joint without open circuit and/or HIP. The yield has been calculated with emax changing from 0 to 2mils. This value is dependent to flux selection, alloy type and reflow condition. If we also define em, ep as gap value at the melting temperature and the maximum gap between the melting and peak temperatures, respectively, we can define the failures as follows:

If ememax, open circuit or HIP (2) If em emax, ep emax good solder joints (3) If em emax, ep emax P(em>emax)PP(ep>emax) (4)

where, P is the probability of forming HIP solder joints. P(em>emax) and P(ep> emax) represent the probability at em>

Table 1 BGA details used in PoP

753 2009 Electronic Components and Technology Conference

BGA Bottom Top

Size 14x14mm 14x14mm

Pitch 0.5mm 0.65mm

Die size 8.9x8.9mm

Total thickness 1,5

Number I/O 353 152

Bump size 0.3mm 0.45mm

Surface finish on component pads

ENIG on top and OSP on bottom

ENIG

Bump material SnAgCu SnAgCu

(a)

(b)

Fig. 2 Schematic drawing of PoP and SIP. (a) A quarter model and (b) SIP warpage model during reflow.

emax and ep> emax, respectively. The probability of forming HIP is dependent on the gap value. Flux selection, solder alloy and reflow profile may also impact the probability through impacting emax. It is noted that ep is usually the gap at the peak temperature and in most SIPs using eutectic tin-lead solder, it is found that ep>em. For some BGAs, the warpage at the melting temperature could be similar or even slightly higher than that at the peak temperature. In that case, em shall be the dominant HIP contributor. Therefore, Equations 1 and 4 can be used to determine whether there is a risk for forming HIP. Fig. 7 illustrates the HIP process when the gap requirement for em and ep may not be met. That is a typical process when the gap during the reflow is widened at the peak temperature. It is noted that HIP could be formed

even though em<emax at the solidification but the probability shall be P P(ep>emax). This means that P(em>emax) represents the best case and P(ep>emax) represents the worst case. In this paper, yield prediction using Equation 4 shall be compared with the production data for validation purposes.

Fig. 3 Schematic chart of typical warpage pattern of top and bottom BGAs for PoP (a~d).

Table 2 Parameter using in Surface Evolver

Parameter in SIP Free Ball Solder Joint

Ball dia, mm 0.64 Ball pad, mm 0.5 0.5 PCB Pad, mm N/A 0.5 Ball volume, mm3 0.1038 0.121 Component Weight, dyn/pad 5.1 Surface Tension, N/m 0.57 0.57

Fig. 4 Surface evolver modeling of the solder ball height at the center (solder joint) and edge (free ball).

754 2009 Electronic Components and Technology Conference

0.5640.5520.5400.5280.5160.5040.492

20

15

10

5

0

Ball H,mm

Frequency

Mean 0.5264StDev 0.01724N 40

Histogram of Ball H,mmNormal

Fig. 5 Solder ball height from SIP component.

Solder joint vs. Component Pad Weight

0.40.420.440.460.48

0.50.520.54

0 2 4 6 8 10 12

Component Weight, dyn/pad

He

igh

t o

f s

old

er

join

t P

red

icti

on

Solder joint

FreeBall

Fig. 6 Solder collapse height in SIP at different component

weight.

Fig. 7 Typical gap changes during reflow from melting

temperature (A) to the peak reflow temperature (B) and solidification (C). Warpage Measurement by Shadow Moiré Technique

The warpage of BGA and PCB have to be measured at the reflow temperature. It is usually measured by Shadow Moiré method [4~6].

For PoP packages, several top and bottom BGAs are selected from two suppliers. Both BGAs were measured from the bottom side (bottom view) with balls removed. Detailed setup info is shown in an earlier paper [7]. Typical 3D Moiré contour images are shown in Fig. 8. It is shown from those figures that the top BGA may have an initial warpage at the room temperature. The warpage is not uniform. It becomes larger when the temperature increases to about 170C, and stays at high warpage from 220C to 250C. It is noted that 220C is close to the melting point and 250C is close to the peak reflow temperature for the SAC alloy. The BGA is warping as a “smiling” face so that the edge and corners of the top BGA are moving away from the bottom BGA, which creates a gap between the solder ball and the copper pad.

Fig. 9 shows the warpage contour of top PoP BGA measured at 220C and 250C in 2D format. It shows that the center region of top BGA warped towards bottom BGA and the highest warpage is about 2mils at 220C and is reduced to about 0.8mil at 250C. In Fig. 10, the warpage of bottom BGA changes from 2.2mils at 220C to 0.8mil at 250C. Since the measurement is done on the bottom side for both top and bottom BGAs, the warpage value of bottom BGA should be in the opposite direction of top BGA. Thereby it partially compensates for the gap contribution from top BGA.

A summary of moiré measurement is shown in Table 3. Two BGA suppliers are listed. As shown in Table 3, there is a large difference of the warpage value in top BGA. Supplier #2 has much lower warpage value as compared to that of Supplier #1. This can create a significant difference in the yield as can be seen later in this paper.

Fig. 8 Typical warpage contours for top BGA (unit

Top#2). Temperature and the total warpage are marked in the chart.

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(a) 220C

(b) 250C

Fig. 9 2D plots of the typical warpage for top BGA in PoP BGA.

(a) 220C

(b) 250C

Fig. 10 2D plots of the typical warpage for PoP--Bottom BGA.

For SIP warpage, both finite element analysis (FEA) and

moiré measurement are performed. A typical value is shown in Fig. 11. It shows that the warpage could be from -6 to

+10 mils as the package is relatively large. It also shows that the FEA value is lower than that from the measurement but it is close to the nominal value of the measurement.

Table 3 Summary of Moire measurements from two PoP BGA suppliers. Unit in mils

PoP Supplier

Temperature 220C 250C 220C 250C

Unit#1 (0~2.2) (0~2.7) (-2.4~0) (-2.4~0)Unit#2 (0~2.4) (0~3.2) (-2.3~0) (-0.8~0)Unit#3 (0~1.2) (0~1.5) (-2.4~0) (-3.0~0)Unit#4 (0~2.8) (0~4.1) (-2.4~0) (-3.0~0)Overall (0~2.8) (0~3.2) (-2.4~0) (-3.0~0)

Unit#1 (-0.5~0) (0~0.2) (-3~2.0) (-2.0~-1.8)

Unit#2 (-2.5~0.5) (-1.9~0.8) (-2.5~1.5) (-2.5~-1.0)Unit#3 (-0.5~0.2) (-0.6~0.6) (-2.0~1.2) (-2.3~-1.9)Overall (-2.5~0.5) (-1.9~0.8) (-2.0~1.2) (-2.5~-1.0)

Supplier#2

Warpage, Top BGA Warpage, Bottom BGA

Supplier#1

-10

-5

0

5

10

15

0 50 100 150 200 250

Temperature, C

War

pag

e, m

ils

FEA, mils

Testing, mils

Fig. 11 Warpage measurement by Moire and FEA

simulation for SIP.

HIP Probability Prediction Results and Discussion In Equation 1, A and B are measured by the Shadow

Moiré measurement as shown in Table 3, while H and B are taken from the supplier’s data sheet as shown in Table 1. Those two parameters are normally under tight control from the packaging house so that normal distribution shall be observed. The output from the Monte Carlo simulation using Equation 1 is shown in Fig. 12, where 5000 data points are simulated. It is clearly shown that the gap distribution for Supplier #1 is from -5 to +2mils, and the reject rate is about 17.7 to 19.8% if using emax0. For Supplier #2, the reject rate is only about 0.02 to 1.56% using emax0. It is noted that the probability difference becomes very small comparing 250C and 220C when using Supplier #2. The yield prediction using emax0 is conservative and represents the worst case. That means that no gap exists from melting through peak to the solidification temperature, resulting in good solder joints without HIP and/or open circuit.

To further investigate the impact of other assembly process variables, different fluxes were studied. This would affect the wettability of the solder ball so that it may change the maximum allowable gap (emax). Table 3 shows the production results using 3 different fluxes. The reject rate is taken from statistical calculation from a large quantity of assemblies. It is known from Table 4 that the reject rate is negligible for PoP BGAs from Supplier#2 for all three types

756 2009 Electronic Components and Technology Conference

of fluxes. For Supplier #1, the reject rate depends heavily on the selection of flux, ranging from 1.14% to 14.7%. The prediction by this work is agreeable well with the worst case scenario among the three fluxes used in this study. This does indicate that the selection of flux is critical if there is a gap between the solder ball of top BGA and the pad on the top side of bottom BGA during reflow. On the other hand, the flux would be less critical if the gap is kept to the minimum or none.

The flux activity during reflow can significantly influence the value for the maximum allowable gap, emax. By re-arranging the results from these three types of fluxes, it can be seen that Flux #3 did poorly with the wetting of the solder ball so that the value emax needs to be very large to maintain a good yield. This can be illustrated by Fig. 12. In Fig. 12, the reject rate for PoP from Supplier #1 can be much smaller if the value for emax increases. To get zero defects for Supplier #1, the maximum allowable gap emax, which is determined by the activity of the flux, needs to be about 2mils depending for any of the three fluxes. This shows clearly that flux selection is very critical when using BGAs from Supplier #1. Similarly, reflow under nitrogen or any other assistance to wetting can also help to bridge this gap. On the other hand, the flux does not impact the HIP probability much if the emax is close to zero. Table 4 Reject rate from Production as a comparison to the prediction for both Suppliers.

Supplier #1 Supplier #2

Bottom BGA

Top BGA

Bottom BGA

Top BGA

Flux #1 0.0% 1.14% 0.0% 0.0%

Flux #2 0.0% 6.25% 0.0% 0.0%

Flux#3 0.0% 14.7% 0.0% 0.0%

Predicted from this work*

N/A

7.28~ 9.98% if emax=0.56mil

N/A 0.02%

Note: * prediction using emax0.

For SIP, the input parameters are listed in Table 5. Normal distributions are assumed for all parameters. The predicted results are shown in Fig. 13. It is shown that the simulated probability of forming HIP is between 0.3 to 11.3% using emax=0 and 0.3 to 7.6% using emax=0.56mil. It is noted that the difference between P(ememax) and P(epemax) is large, which means that the chance to form a HIP in SIP is much higher than that in PoP. The standoff distribution of the SIP solder joints is shown in Fig. 14. The lowest standoff is about 0.392mm observed at the center and the highest is about 0.539mm observed at the corner, which are in line with the standoff prediction by Surface Evolver. The corner solder joint meets one of the conditions for forming a HIP:

Hsj > Hb+HSP (5) where, Hsj is the solder joint standoff, Hb is the height of free solder ball, and Hsp is the solder height contributed by solder paste. Fig. 12 Probability of forming HIP vs. maximum allowable gap (emax.) for PoP showing the impact region of fluxes. Table 5 Parameter used in SIP yield simulation (reading at 220C for tin-lead solder)

Item SymbolMinimal, mils

Nominal (mils)

Maximum, mils

Standard deviation, mils

BGA warp A 7 8 11 1.2Collapse H, center

H 14 15.7 18 1

PCB warp C -3.00 1.00 3.00 0.38

Paste height P 5.9 0.3

Ball height B 20.76 0.14em -1.96ep -4.46

P(em>0) 0.3%P(ep>0) 11.3%

Propability calculation

0.0%

2.0%

4.0%

6.0%

8.0%

10.0%

12.0%

0 0.5 1 1.5 2 2.5

emax, mils

Pro

ba

bili

ty

P(em>emax)

P(ep>emax)

Fig. 13 Probability of forming HIP vs. maximum allowable gap (emax.) for SIP.

0.00%

5.00%

10.00%

15.00%

20.00%

25.00%

0 1 2 3

Maximum Allowable Gap (emax), mils

Pro

ba

bili

ty

P(em>emax), Supplier #1 P(ep>emax), Supplier#1

P(em>emax), Supplier #2 P(ep>emax), Supplier #2

Impact area of Flux

Supplier#1Supplier #2

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Fig. 14 Solder joint standoff of SIP along the outer edge and center. The corner ball has HIP. Conclusions

The gap between the solder ball and the soldering pad on PCB is created mainly due to the BGA warpage during the reflow. The gap may change from the melting to the peak reflow temperature and to the solidification point. The HIP is usually formed under the following circumstances:

a. the gap exists all the way up to solidification; or b. the gap exists only at the peak temperature but the

solder ball does not wet completely with the solder on the PCB pad during solidification.

There exists a maximum allowable gap for a solder joint with no HIP. The gap is usually very small (less than 1 mil) which should be determined by experiemnts. The maximum allowable gap value depends on the flux, solder alloy and reflow profile etc. The critical gap is created mainly due to the warpage of the BGAs, which can be significantly different from different suppliers. On the other hand, the effectiveness of the flux during reflow directly affects the maximum allowable gap.

The prediction on the reject rate from the simulation in this study agrees reasonably well with the production data. Based on the study, the following measures are recommended to reduce HIP defects:

1) Minimize BGA warpage during reflow; 2) Use robust flux; 3) Increase solder paste volume for SIP; 4) Increase BGA ball size and coplanarity. 5) Control the warpage profile of PCB (for SIP) and

bottom BGA (for PoP) Acknowledgments

A lot of peoples have contributed to this work. The authors would like to give special thanks to Syed Ahmadshar from Flextronics Penang, Malaysia and Clay Hallmark from Flextronics Austin for the optical and Moire measurement testing and valuable inputs. FEA analysis provided by Billy Hu from Flextronics Shenzhen, China is also greatly appreciated.

Reference

1 Frost & Sullivan, Analysis of World Markets and Trends for System-in-Package (SiP) Technology, 2007.

2. D. Geiger, D. Shangguan, S. Tam, and D. Rooney, “Package Stacking in SMT for 3D PCB Assembly”, Proceedings of IEEE IEMT 2003 (Paper S207P6), San Jose, CA, July 2003.

3 Flynn Carson, “Package-on-Package Variations On the Horizon”. Semiconductor International, 5/1/2008.

4, Wei Lin, Akito Yoshida, and Moody Dreiza, “CONTROL OF THE WARPAGE FOR PACKAGE-ON-PACKAGE (PoP) DESIGN”, SMTAI ’07, pp. 320~327.

5 Peng SUN, Vincent Chi-Kuen LEUNG, Bin XIE, Vivian Wei MA, Daniel Xun-Qing SHI and Tom Chang-Hwa, “Warpage Reduction of Package on Package (PoP) Module by Materials’ Selection & Process Optimization”, ICEPT-HDP 2008, Shanghai China.

6. Dongji Xie, David Geiger and Dongkai Shangguan, Billy Hu and Jonas Sjöberg, Yield Study of Inline Package on Package (PoP) Assembly, Electronic Packaging Technology Conference 2008, Singapore.

7. Kazuo Ishibashi, PoP (Package-on-Package) Stacking Yield Loss Study, Proceedings of ECTC 2007, pp. 1043-1048.

8 Niranjan Vijayaragavan, Flynn Carson, and Addi Mistry, “Package on Package Warpage - Impact on Surface Mount Yields and Board Level Reliability”, Proceedings of ECTC 2008, Lake Beuna Vista, FL, May 2008, pp. 389-396.

9. Jonas Sjoberg, David Geiger and Dongkai Shangguan, “Package on Package Process Development and Reliability Evaluation”, Proceedings of ECTC 2008, Lake Beuna Vista, FL, May 2008, pp. 2005-2010.

10. Ken Brakke, Surface Evolver, http://www.susqu.edu/brakke/.

11. Steve Cho, Dudi Amir and Aaron Reichman, “Validation of Warpage Limit for Successful Component Surface Mount (SMT)”, 2008 Electronic Components and Technology Conference, pp899~906.

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