Design and Implementation of Semi-Quadratic Slope Compensation Circuit for PWM Peak Current Mode

Boost Regulator

1 Khondker Zakir Ahmed, 2 Syed Mustafa Khelat Bari, 3 Mohiuddin Hafiz and 4 Didar Islam 1, 2, 4 Power IC Ltd., Dhaka, Bangladesh., 3 Bangladesh University of Engineering and Technology, Dhaka, Bangladesh

E-mail: zakir.ak@gmail.com

Abstract – This paper presents a circuit implementation to fulfill the demand of the non-linear slope compensation to improve stability in a switching peak current mode DC-DC boost converter. The circuit is implemented by regular threshold voltage NMOS and PMOS and standard on-chip pico-Farad range capacitor biased by a PTAT current. Using the quadratic nature of the drain current of a MOS device in saturation the circuit generates a compensating slope signal on a cycle by cycle basis and this compensating slope signal is added with the current sense signal to compensate the disturbance that might arise. Along with the quadratic nature current another fixed current is added to compensate the noise that creates instability at lower duty cycle where the sense signal is weak. A chip is fabricated in 0.5μm technology using the proposed circuit. Simulation and test data has been presented.

I. Introduction Peak Current Mode (PCM) Pulse Width Modulation (PWM) boost regulator is considered as an important integrated circuit for many low power mobile applications. Although current mode design offers many advantages over voltage mode design like built-in over-current protection, robust dynamic responses, simplified voltage-loop compensator design, rejection of input voltage disturbances, relatively simple current sharing for power modules operating in parallel and so on, one of the major problems of the design scheme is the inherent sensitivity to current disturbance while operating in continuous conduction mode (CCM) at a duty cycle greater than 50% [1], [2]. This sort of oscillation is also called as sub-harmonic oscillation, as this occurs at half the switching frequency when the converter runs above the maximum allowable duty cycle, without being compensated [2]-[5].The current disturbance which grows cycle by cycle if not compensated and makes the IC unstable. To enable the converter, operating in CCM, run at higher duty cycle, theoretically above 50%, a compensating ramp is added to current sense signal. Moreover to reduce the sensitivity to noise, the compensation ramp is commonly added in practical CPM (current programmed mode) designs, even when operating the converter at duty cycles less than 0.5 [6]. The compensation, commonly known as slope compensation, is theoretically expected to be non-linear

with respect to duty cycle. Some work has already been published concerning the non-linear slope compensation method. One method proposes a output voltage independent second-order slope compensation technique for a buck converter [7]. Another work emphasised on piece wise linear slope compensation [8]. This paper specifically focuses on a PCM mode PWM technique boost converter stability. A semi-quadratic slope compensation signal generating circuit is proposed using which a chip is fabricated in 0.5μm technology and the stability is analyzed.

II. The Phenomenon of Instability Basic ideas of the instability in the current loop in the absence of compensation and the remedy to it have been illustrated in this section. One of the ways the instability due to the sub-harmonic oscillation occurs, when a current disturbance gets induced in a converter running at high duty cycle, for a fixed input, as shown in Fig.1. For a fixed DC input voltage, if for some reasons there is an initial current disturbance ΔI1, after a first down-slope the current will be displaced by an amount ΔI2 .If the duty cycle is above 50% (m2>m1 in Fig. 1), the output disturbance after one cycle ΔI4 is greater than the input disturbance ΔI3. This can be further explained from Fig 1. For a small current displacement ΔI1, the current reaches the original peak value earlier in time by an amount dt, where dt=ΔI1/m1. ON the inductor down-slope, at the end of the ON time, the current is lower than its original value by an amount ΔI2 which is defined by Eqn. (1),

-----------------------(1)

Now with m2>m1, the disturbances will continue to grow but eventually decay, giving rise to an oscillation. As mentioned earlier, this sort of oscillation is also called as sub-harmonic oscillation. This PCM (Peak Current Mode, as the peak current is regulated) control, however, is a widely used topology in industrial purposes and the above mentioned type of oscillation is eliminated by the addition of a compensating signal with slope Mc >0. The way in

2

1122 m

mIdtmI Δ==Δ

5th International Conference on Electrical and Computer EngineeringICECE 2008, 20-22 December 2008, Dhaka, Bangladesh

978-1-4244-2015-5/08/$25.00 (c)2008 IEEE 512

which such compensating technique works, has been illustrated in Fig 2.

From a simple geometrical argument, the condition to prevent subharmonic oscillation is expressed in Eqn. (2):

11

2

1

2 <+−=

ΔΔ

c

c

MmMm

II

-----------------------------(2)

where, m1 =Vin/L>0 is the inductor current slope in the charge phase. Hence from the above equation, it is evident that, by selecting Mc>m2/2, stable operation of the current loop under all steady-state conditions is possible to achieve.

Besides, in [3],[9],[10] modulator model for the current programmed converters was derived, experimented and modified. A model for current-mode converter consists of two parts: 1) the model for the power stage, and 2) the model for the modulator [3]. The model of power stage in [11], [12] is now widely accepted, hence the actual task is reduced to the establishment of a modulator model. A modulator is expected to be expressed in terms of the average inductor current il, the average control current ic

and an effective voltage veff, which determines the slopes of the inductor current. Satisfying the conditions, a unified modulator model has been developed in [3] and the modulator gain Fm is expressed in Eqn. (3):

⎥⎥⎦

⎤

⎢⎢⎣

⎡−⎟

⎟⎠

⎞⎜⎜⎝

⎛+

=

122

2

// D

DLMT

LF

eff

ceffS

m

νν

-----------------(3)

From the above equation it’s evident that Fm approaches infinity for Eqn. (4)

⎟⎟⎠

⎞⎜⎜⎝

⎛+

=22

1

/

/

eff

c

DLM

D

ν

-----------(4)

The above equation indicates the minimum value of D' to maintain a finite positive value for Fm , expressed in Eqn. (5),

⎟⎟⎠

⎞⎜⎜⎝

⎛+

≡

⎟⎟⎠

⎞⎜⎜⎝

⎛+

≡

1/

min/

1

5.0

/1

5.0

mM

LDM

Dc

eff

c

ν

---------(5)

Hence, from the above equation, the current loop becomes unstable for min D′ =0.5, if Mc=0, which implies that in the absence of Mc, the loop oscillates for Dmax = 1-D/ = 0.5. [3]

III. Design and Analysis of Circuit The circuit is implemented using standard NMOS and PMOS devices. Fig. 3 shows the schematic view of the proposed slope compensation circuit.

Fig. 3. Schematic of the proposed slope compensation circuit

The circuit is biased form an external PTAT current source. Inside the circuit, the current is mirrored and supplied to other nodes to bias different elements. The core of the circuit is the charging capacitor (C1) which is charge by two types of current. One is quadratic in nature

Fig. 1. Current loop oscillation for duty cycle > 50%

Fig. 2. Correction of oscillation by compensation ramp.

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and the other is a constant one. The quadratic current is generated by moving the gate voltage of a MOSFET linearly. The diode connected p-MOSFET (PM3) shown at the upper portion of the circuit ensures that the quadratic current generating MOSFET is always in saturation. At the beginning of each oscillator cycle, the charging initiation switch (PM2) turned off and the upper capacitor (C2) is linearly charge up by the constant current sink (NM3). As the source of PM3 drops linearly so does the gate of the PM4 which is connected to the drain of PM3. Linear variation of gate voltage produces quadratic current at the drain of PM4 which is used to charge capacitor C1. in addition another fixed current is also added at the same node of C1. with the two charging currents the capacitor charges up in a semi-quadratic fashion voltage which is used as the slope compensating signal.

At the end of the ON-time, the oscillator signal goes low which turns ON the reset MOSFET (NM4). The reset switch discharges the charged up capacitor C1 and get it ready for the next cycle. Also the initiation switch PM2 remains turned ON during oscillator OFF time and ensures the discharging of capacitor C2. The reason for adding a fixed current to the quadratic one is to provide a fixed amount of slope compensation at lower duty cycle. Without the additional fixed current compensation at lower duty cycle when the quadratic slope generating current might be too low to provide minimum amount of compensation at lower duty cycle and the chip might go unstable. The slope compensation which is added by the fixed current provides a shield against noise at lower duty and remains the chip in stable region.

IV. Results and Discussion Simulation result of the proposed block is shown in Fig. 4. The slope compensating signal is shown increasing non-linearly over the full TON-period. A linear slope compensation signal is shown in

Fig. 4. simulation curve showing semi-quadratic slope compensating signal. Y-axis unit in Volts and X-axis unit in Seconds.

Fig. 5. simulation curve showing linear slope compensating signal. Y-axis unit in Volts and X-axis unit in Seconds.

The test data from the fabricated chip is presented below. The stability improvement due to the use of semi-quadratic slope compensation circuit is emphasised in the test data. First a chip that uses linear slope compensation is presented. The instability due to poor compensation at lower duty is shown in Fig. 6(a) and instability due to poor compensation at higher duty is shown in Fig. 6(b). This unstable version of chip employs linear slope compensation technique as shown in Fig. 5. As can be seen, the chip was unstable both in low duty and high duty cycle range. Instability was created due to the poor slope compensation signal strength. For linear increment the signal didn’t get enough time to increase to provide necessary magnitude. In contrast to the unstable figures, we present test data from another chip fabricated using the proposed slope compensation circuit. The booster is found to be stable from duty cycle as low as 15% to as high as 85%. Corresponding oscilloscope snaps are shown in Fig. 7(a) and Fig. 7(b). The wide stable operating range is a significant evidence of better performance of the pseudo quadratic slope compensation circuit.

(a)

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(b) Fig. 6. Oscilloscope snaps of the poorly slope compensated booster operating at (a) low (below 50%) duty cycle and (b) high (above 50%) duty cycle. In both low and high duty cycle the booster is unstable which is obvious from the inductor current shape. Channel – SWITCH pin, Channel 2- VOUT, Channel 3 – FB, Channel 4 – inductor current

(a)

(b) Fig. 7. Oscilloscope snaps of the rightly slope compensated booster implemented by proposed circuit operating at (a) 15% duty cycle and (b) 85% duty cycle . In both low and high duty cycle the booster is stable. Channel – SWITCH pin, Channel 2- VOUT, Channel 3 – FB, Channel 4 – inductor current

V. Conclusion Submission in this paper we have presented a new proposal for a semi-quadratic slope compensation circuit for PCM – PWM DC-DC boost regulator. This proposed circuit is fabricated in 0.5μm technology. The test data of the fabricated chip shows very good result regarding the overall stability. The Chip fabricated with the proposed semi-quadratic slope compensation circuit operates in stable condition from very low duty cycle (15%) range to a very high duty cycle (85%) which was previously unstable when fabricated with linear slope compensation circuit.

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