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An Analysis of Paralleled SiC Bipolar Devices E. Johnson, O.S. Saadeh, H.A. Mantooth, J.C. Balda, S.S. Ang, A.K. Agarwal*

National Center for Reliable Electric Power Transmission Department of Electrical Engineering

University of Arkansas Fayetteville, Arkansas 72701 USA

* Cree, Inc., 4600 Silicon Drive, Durham, NC 27703 USA

Abstract— SiC semiconductor devices are becoming more common in high power applications. This is largely due to higher blocking voltages and faster switching speeds. The development of SiC devices, specifically thyristors and GTOs, is still an evolving process [1]. There is not yet a single device capable of handling the magnitude of current typically seen in transmission and distribution systems and as a result these devices must be paralleled into a single switching position. SiC thyristors were used to carry out a study on paralleled SiC bipolar devices. Si bipolar devices are much better matched than SiC devices, but they exhibit much slower turn-on times [2]. Thus, the most suitable method of inducing current sharing in these devices is through gate control. However, SiC devices exhibit fast turn-on times while being poorly matched. Using various methods of gate control for SiC bipolar devices in parallel does not significantly affect the current sharing. The best way to improve current sharing is obtained using series resistors. These resistors should be chosen so that the voltage drop and power losses are minimized. The effects of thermal runaway are observed as well. As a device rises in temperature relative to the other devices, it conducts more current due to its negative temperature coefficient of on-state resistance. In order to maintain proper heat sharing, a design for a package is presented that includes three thyristors in parallel on a common substrate.

I. INTRODUCTION

The advantages of SiC power devices can be utilized in many high power systems such as fault current limiters and static VAR compensators. Though these are not high temperature applications typically associated with SiC devices, the fast turn-on and turn-off times (as well as the high voltage capability) make SiC thyristors and GTOs suitable for these utility applications [3][4]. At the present time, there is not a single SiC device capable of handling the type of currents required by these systems. The currents in applications such as these are usually upwards of several kiloamperes, and thus the devices need to be paralleled. In this paper, SiC thyristors are used to examine the effects of SiC bipolar devices operating in parallel. Several methods will be explored in order to find a suitable solution for current sharing. The results obtained could be applied to other SiC bipolar devices such as GTOs and BJTs.

II. COMPARISON OF SI AND SIC PARALLELED BIPOLAR DEVICES

The analysis of SiC bipolar devices in parallel first began with an examination of Si bipolar devices. In Si devices, the major factor that led to current imbalance in parallel branches was the turn-on time of the device [5]-[9]. Si thyristors exhibit significant differences in turn-on time from device to device. When they are paralleled, the device with the fastest turn-on time takes a larger share of the current [6]. As a result, its temperature rises with respect to the rest of the devices in the parallel configuration and it continues to conduct more current, due to its negative temperature coefficient of on-resistance [7][8]. As a result, Si bipolar devices are often balanced by slowing the turn-on time of one or more devices in the parallel configuration relative to the others. This is typically achieved by series inductors at the gate of the devices or by using different gate drive outputs to deliver an appropriate di/dt at the gate of each device. Another method is to simply use a single gate drive board with a high di/dt to overcome any discrepancies in turn-on time. Thus, various methods of gate control are sufficient to balance paralleled Si bipolar devices. SiC bipolar devices require different methods of current balance, due to their differences with Si bipolar devices. SiC bipolar devices are capable of achieving turn-on times that may be several times faster than those of similar Si devices, meaning that even if there are differences in turn-on times among devices in paralleled branches, it is relatively small and does not influence current sharing in a major way.

III. EXPERIMENTAL METHODS OF CURRENT SHARING

A number of experiments were carried out using three 1 kV, 100 A SiC thyristors in a parallel configuration. These devices were tested under different gate conditions and different system currents and the effects were observed. Fig. 1 shows the currents through each of the branches while the system is uncompensated. Device 5 carries about 15.6 A, Device 1 carries about 13.4 A, and Device 3 only conducts about 4.2 A. Initially, various gate control methods were explored in order to determine whether or not the current through each branch could be altered to promote sharing. For a constant load current

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the gate current was increased and held constant during the duration of the conduction cycle. There were minor improvements of current sharing at higher values of gate current. However, in order for this effect to be observed, the gate current must be applied continuously and must be proportionally large compared to the total system current. Even when the gate current was 5 A for an approximately 12 A system, the device conducting the highest current carried about 60% of the total current compared to about 11% for the device conducting the smallest amount. This was compared to values of 63% and 12% for a gate current of 1 A. This approach was deemed to not be highly effective. It may be possible to use a voltage controlled gate driver in a low power application utilizing bipolar SiC devices in parallel. Since the voltage across each branch is equal due to the parallel configuration, the constant voltage will force the anode to gate voltage of each device to be the same. As a result, the gate to cathode voltage will be equal as well, and each device will forced into a similar operating condition, balancing the current. Each device would draw the current it needs through its gate to sustain this conduction. However, the gate current would need to be high as well. Thus, this solution may not be suitable for high power applications.

Si devices in parallel often require the use of a single gate driver board in order to deliver a high di/dt to all devices simultaneously and minimize any differences in turn-on time that may occur. Gate inductors are used to alter the di/dt to each device in the event that the di/dt ofthe gate driver is not sufficient to overcome the variations. This approach was taken with the SiC devices. Inductance values of 0.5 mH and 19.5 mH were used in series with the fastest device in the parallel configuration in order to evaluate the effects of this technique. Even though the turn-on time of the device was delayed relative to the others, ultimately the series gate inductance did little to impact the current balance. The turn-on time of SiC devices is much faster with respect to the turn-on times of Si devices, and even if each device has a different turn-on time this does not extensively impact the manner in which the devices share current. The major factor in determining how SiC bipolar devices share current in a parallel setup was found to be the on-resistance of each device. Thus, the on-resistance of each device was determined at the system operating

point and series resistors were used to equalize the total resistance in each parallel branch to promote current sharing. Fig. 2 shows the on-state curves of the devices used in the parallel configuration. From this figure, the on-resistance of Devices 1, 3, and 5 were determined to be about 22.7 m , 22.3 m , and 18.4 m , respectively. At a load current of approximately 30 A, resistance values of 0.15 , 0.1 , and 0.15 were used with Devices 1, 3, and 5 to balance the current. In an optimized system, these values would be on the same order of magnitude as the on-resistance to minimize the effect on system current. An ideal condition would be to leave Device 1 unaltered while adding series resistances of 0.4 m and 4.3 m to Devices 3 and 5 to equalize the resistance of each branch. The actual values used differ from what was determined theoretically and this is due to differences between the actual on-resistance and those values obtained from Fig. 2. Fig. 3 shows the system using the series resistances to balance the currents through each branch. From this figure it can be seen that there is only a 0.3% mismatch in current among the thyristors. Devices 1 conducts 10.15 A, Device 3 conducts 10.05 A, and Device 5 conducts 10.03 A. Even though the current is shared evenly, there are some drawbacks to using series resistors to balance the current. The most significant of these is that there is a significant voltage drop and power loss across each resistor, especially for systems requiring large currents. Table 1 contains the voltage drop and power losses associated with each device in the 30 A system. While the voltage drop and power losses seem reasonable, they could

Fig. 3. Current balance using series resistors

Fig.2. On-state curves for paralleled thyristors

Fig. 1. Current of SiC thyristors in uncompensated system

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become detrimental at high current and the benefits of balanced current could be negated. Also, the thermal management system would likely become unreasonably large for a high current system. It is important to optimize the system by using small resistors. This will minimize the voltage drop, the power losses, and the effect that the resistors have on the system current.

IV. THERMAL CONSIDERATIONS FOR PARALLELED DEVICES

The effects of thermal runaway were examined for SiC thyristors in a parallel configuration. SiC bipolar devices have a negative temperature coefficient of their on-state resistance, meaning that if one device conducts more current than the others in the parallel configuration, its temperature will be higher relative to the others. As a result, its on-resistance will decrease and it will draw more current. This cycle will continue until ultimately one device is carrying a highly disproportionate amount of the total current. Carrying such a high current could cause the device to exceed its rated value and become damaged, which would in turn lead to the failure of the other devices in the system. It is important that the devices share current initially and have sufficient thermal management in order to prevent thermal runaway. An experiment was conducted wherein the system was initially imbalanced. To illustrate the impact of thermal runaway in a controlled manner, the device with the lowest current was intentionally heated and the effects analyzed. Fig. 4 shows the current being conducted by each of the devices for many different temperatures. The temperatures of the devices at each time are indicated. Device #3, which initially had the lowest conduction current among all the devices at room temperature, was heated and over time it ended up being the device with the largest amount of current flow due to the negative temperature coefficient of bipolar devices. At a temperature difference of approximately 21 °C, the device current increased by approximately 37%.

V. PACKAGE DESIGN FOR PARALLELED SICTHYRISTORS

A package design was developed for the SiC thyristors. Figs. 5(a) and 5(b) show photographs of the partially and completely assembled package. As can be seen, the SiC die was bonded to the DBC substrates using 12 mil (0.3048mm) aluminum bond wires. Scanning acoustic microscopy of the package shows a void-free die attach using the Sn96.5-Ag3.5 solder. Electrical tests were conducted and demonstrated that this packaged device is capable of handling 100 A of current. To increase the current-handling capability of the thyristor module and to provide a better thermal matching, three thyristors will be packaged on a common nickel-plated direct-bond copper (DBC) substrate. The three thyristor dice are arranged in a row and are rotated 45° from the common axis to facilitate wire bonding from the bonding pads on the dices to the connectors on the package as shown in Fig. 6. A lead-tin solder pre-form, cut to the size of the dice, is placed between the dice and the DBC substrate. Die attachment is achieved using a reflow process in an annealing furnace. Die to substrate interconnection is provided by 0.012" diameter aluminum wires using an ultrasonic wire bonder. Copper power lugs and flexible copper braids serve as the internal power connection.The copper power lugs are soldered to the substrate using a lower temperature solder than the die attach solder. Silicone gel is used to provide mechanical support to the bond wires, protect the metals underneath from oxidation, and offer sufficient dielectric strength to suppress arcing at the edges of each device.

TABLE 1. BALANCED SYSTEM CALCULATIONS

Current (A)

Series Resistance

( )

Resistor Voltage

Drop (V)

Resistor Power Losses

(W)

Thyristor Voltage

Drop (V)

Thyristor Power Losses

(W)

Total Power Losses (W)

Resistor Power Losses

(%)

Thyristor Power Losses

(%) Device #1 10.15 0.15 1.52 15.45 3.48 35.32 50.78 30.43 69.57 Device #3 10.05 0.10 1.01 10.10 3.99 40.10 50.20 20.12 79.82 Device #5 10.03 0.15 1.50 15.09 3.50 35.11 50.20 30.06 69.94

Fig. 4. Thermal characteristics of paralleled devices

Fig. 5. Photographs of (a) partially assembled package (b) completed package.

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To house the protective gel, an enclosure of electronic grade Teflon which consists of four sidewalls and a lid is used. The Teflon sidewalls are held together by screws and are bolted down to the copper base plate. Similar to the single-die package, power lugs for external power connection are mounted through the side walls.

VI. CONCLUSIONS

SiC thyristors were paralleled and tested in order to determine the best approach for balancing current. These devices can be forced to share current by the use of series resistors, which should be optimized in order to minimize unreasonable voltage drops and power losses. A common package can prevent thermal runaway by promoting heat sharing among the devices. Ultimately, the packaged module can be used in high power applications to take advantage of the many benefits provided by SiC semiconductor devices.

ACKNOWLEDGMENTS

Special thanks to Cree, Inc. (Durham, NC) for providing the SiC devices used to conduct the analysis and to Dr. Victor Wang for performing the packaging of the devices.

REFERENCES

[1] A. Agarwal, B. Damsky, J. Richmond, S. Krishnaswami, C. Capell, S. H. Ryu, and J. W. Palmour , “The first demonstration of the 1 cm x 1 cm SiC Thyristor chip,” in Proc. of 17th International Symposium on Power Semiconductor Devices and IC’s, pp. 195-198, 2005.

[2] T. R. McNutt, Compact Modeling and Characterization of Silicon Carbide Power Devices,Ph.D. Dissertation, Department of Electrical Engineering, University of Arkansas, Fayetteville (AR), 2004.

[3] W. J. Choyke and G. Pencel. “Physical properties of SiC”, MRS Bulletin, March 1997.

[4] K. Jarrendahl, and R. Davis, “Material Properties and Characterization of SiC, Semiconductors and Semimetals,” SiC Materials and Devices, Vol. 52, Y.S. Park, (ed.), 1998.

[5] J. Wu, Z. Wang, P. R. Palmer, A. T. Bryant, D. Remy, E. Santi, and J. Hudgins, “Experiment and simulation studies of current distribution in paralleled thyristors,” 41st Industry Applications Conference, pp. 2276-2283, 2006.

[6] Dynex Semiconductor, “Turn-on performance of thyristors in parallel,” Application notes, July 2002.

[7] S. B. Dewan, Power Semiconductor Circuits, New York: John Wiley & Sons, 1975.

[8] J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics, Prentice Hall, 1992.

[9] A. R. Mulica, “How to use silicon controlled rectifiers in series or parallel,” Control Engineering,May 1964.

Fig 6. Package design for paralleled thyristors