Unique ESD Failure Mechanism of High Voltage LDMOS Transistors For Very Fast Transients

Abhijat Goyal*#, Jim Whitfield#, Changsoo Hong#, Chai Gill#, Carol Rouying Zhan#, Vadim Kushner#, Amaury Gendron#, and Shiraz Contractor†.

#Technology Solution Organization, †Transportation and Standard Products Group, Freescale Semiconductor Inc., Tempe, Arizona, USA - 85284 *Telephone: (480) 413 3501, email: abhijatgoyal@freescale.com

Introduction: LDMOS (Laterally Doped Metal Oxide Semiconductor) devices, first introduced in 1969 are widely used as switches, for base station applications, etc. because of their high linearity, gain, grounded substrate and reliability [1]. Recently, the operating voltage of these devices has been extended to 80V and higher without significant loss of performance metrics [1]. Protecting these high voltage devices against ESD (Electro Static Discharge) has become a challenge particularly for very fast transients as observed during a CDM (Charged Device Model) event. In this paper we discuss for the first time the unique ESD failure mechanisms of LDMOS structures for very fast transients observed during CDM events. Experimental Details: We characterized the LDMOS transistor thoroughly with respect to both TLP (Transmission Line Pulsing which mimics ESD transients based on Human Body Model (HBM)), and VFTLP (Very Fast TLP which mimics ESD transients based on CDM). While rise time and pulse width of transients generated using TLP were 10 ns and 100 ns respectively, the rise time and pulse width for VFTLP were 100 ps and 1 ns respectively. We found that the Vt1 of the LDMOS structure was 95 V for TLP and 98 V for the VFTLP as shown in Figure 1. The device failed immediately at snapback after Vt1 with negligible It2 for TLP. The device was not found to be self protecting thus necessitating the use of a clamp (note that it is self protecting for VFTLP with It2 greater than 16 A indicating at least 1000V CDM hardness). We also tested the device under DC gate bias both against TLP and VFTLP waveforms and found that the device failed at greater than 7 V DC gate bias for TLP and less than 6.5 V DC gate bias for VFTLP. Table I shows the Vt1 of the device at different gate voltages. The device can withstand a maximum DC gate voltage of 22 V with a maximum source to gate voltage of 14 V during normal operation in absence of ESD transients. The device breakdown at much lower gate bias voltages during ESD transients was attributed to the high total field created due to superposition of vertical field created by the gate bias and mostly horizontal field created by the ESD voltage at the drain. The device, fully characterized, was used in a commercial chip with a clamp in parallel for protection against ESD transients. The clamp

was implemented using a zener triggered npn structure as reported earlier [2, 3]. The clamp was characterized using both TLP and VFTLP with reasonable clamp performance suggesting at least 4kV HBM (~2.6 amps of TLP current) and 1000 V of CDM performance (corresponding to VFTLP current of ~14 amps). However, during ESD testing of the chip, irreversible melting of the gate source junction of the LDMOS protected by the clamp was observed at 125V CDM as shown in Figure 2. HBM testing of the chip passed full JEDEC/AEC compliance to +/- 2kV. The on chip TLP of the clamp in parallel with the 80V LDMOS device showed pre-turn-on leakage (before Vt1 of the clamp) suggesting that the ESD transient is leaking into the chip thereby damaging the LDMOS device. It is important to note that the damage (Figure 2) was observed only during CDM testing and not during HBM testing. We present a comprehensive study of this unique failure mechanism observed at the gate source junction of the novel 80V LDMOS transistor. TLP waveforms: TLP and VFTLP setups used for characterization allow for monitoring of the DUT current and voltage waveforms as a function of time. These are shown in Figure 3. For both of these waveforms, the applied DUT voltage was 100V. As can be seen from the figures, there is a voltage spike of at least 128V both for TLP and VFTLP before the clamp turns on and starts conducting the current. Hence, the drain of our LDMOS device is

Figure 1: (a) TLP and (b) VFTLP test result of 80V LDMOS device showing immediate failure after snapback thus necessitating the use of a clamp for ESD protection.

(a) (b)

Table I: Table depicting the roll off of Vt1 of the 80 V LDMOS structure with break at applied DC gate bias of 8 V for TLP and 7 V for VFTLP. The tests were repeated several times.

Figure 2: SEM image of ESD damage on 80V_LDMOS after the metal layer and inter layer dielectric were removed. The source and gate junction has melted indicating a voltage build up and current flow at that junction. Since the ESD transient if any is incident on the gate, the failure of source gate junction is unique and novel.

673978-1-4244-2050-6/08/$25.00 ©2008 IEEE IEEE CFP08RPS-CDR 46th Annual International Reliability

Physics Symposium, Phoenix, 2008

subjected to 128 V for a brief time period (less than 1 ns) before the clamp triggers on and starts conducting the current. We believe that this instantaneous voltage spike causes the observed damage at source gate junction as explained below. SPICE Simulation of the Circuit: During our circuit simulation, we monitored the gate, source and drain voltage of the circuit as a function of time. Due to the parasitic gate to source and gate to drain capacitance, for an applied ESD voltage of 100V, a spike in the gate voltage was observed both for TLP and VFTLP as shown in Figure 5. It is important to note here that the gate voltage overshoot is higher by 2.1 V for VFTLP as compared to TLP. During our device characterization (results summarized in Table I), we saw failure for VFTLP at a gate voltage of 1 V higher for TLP as compared to VFTLP. Hence, in this case we suspect that the observed higher gate voltage for VFTLP as compared to TLP is causing the irreversible failure during CDM and not during HBM. This subtle difference in gate voltage spike is due to lower impedance of parasitic capacitors for VFTLP as compared to TLP.

TCAD simulations: We set up TCAD simulations where the gate was biased to DC voltage and we applied ESD transient to the drain. We observed high impact ionization due to higher electric field near the gate source junction (Figure 4) for VFTLP as compared to TLP. Such subtle differences cause device failure for CDM as compared to HBM testing. The bias are the same for the two cases, Vgs of 8V and the snapshots are at 4 ns for TLP and 40 ps for VFTLP assuring same voltages at the electrodes. Hence the only difference is the slew rate of the ESD pulse. Conclusion: We have identified and explained a unique ESD breakdown mechanism of high voltage 80V LDMOS structures for very fast CDM transients. The device was protected against observed damage by placing a zener across the gate and source which prevents the observed voltage build up at the gate of the LDMOS. References: [1] Zhu, R., Parthasarathy, V., Khemka, V., Bose, A., Roggenbauer, T., SPSD [2] S. Joshi, R. Ida, P. Givelin, E. Rosenbaum, IRPS 2001, pp. 240. [3] D. Coffing, R. Ida, Bipolar/BiCMOS Circuits and Technology Meeting, 1998, pp. 31.

-40

-20

0

20

40

60

80

100

120

140

0.E+00 2.E-08 4.E-08 6.E-08 8.E-08 1.E-07 1.E-07

Time (s)

Volta

ge a

cros

s D

evic

e U

nder

Tes

t (V)

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Cur

rent

thro

ugh

Dev

ice

Und

er T

est (

A)

DUT voltageDUT current

(a)

-60

-40

-20

0

20

40

60

80

100

120

140

160

0.E+00 2.E-10 4.E-10 6.E-10 8.E-10 1.E-09 1.E-09

Time (s)

Vol

tage

acr

oss

Dev

ice

Und

er T

est (

V)

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Cur

rent

thro

ugh

Dev

ice

Und

er T

est (

A)

DUT voltage

DUT current

(b)

Figure 3: (a) TLP and (b) VFTLP waveforms showing voltage spike before clamp can turn on and shunt the ESD stress away from the core circuit components being protected.

Figure 4: Comparison of electric field at the source gate junction for (a) TLP and (b) VFTLP transients. The applied gate bias is 8V. A higher electricfield is observed for VFTLP as compared to TLP. Comparison of impactionization at the source gate junction for (c) TLP and (d) VFTLP transientshowing higher impact ionization (~5%) for VFTLP as compared to TLP.

(a) (b)

(c) (d)

Figure 5: Results of SPICE simulations showing gate, drain and source voltages of the 80V LDMOS structure with ESD clamp connected in parallel to it. A 100V input signal is applied which is clamped to 72.5V. During (a) TLP the gate voltage rises to 6.1 V, much below the threshold breakdown voltage of 8 V. During (b) VFTLP the gate voltage rises to 8.2 V, much larger than threshold breakdown voltage of 6.5 V. These threshold breakdown voltages were obtained empirically and are tabulated in Table I.

2.6 V

72.4 V

6.1 V

2.8 V

72.6 V

8.2 V

drain

gate

source source

gate

drain

(a) (b)

674