4
PID Control Implementation using FPGA Technology Abdesselem TRIMECHE(l), Anis SAKLy(I,2), AbdelatifMTIBAA(2,3), Mohamed BENREJEB (1) [email protected] , [email protected] , [email protected] , mohamed. benrejeb@enit. rn u. tn (1)Unite de recherche LARA Automatique de l'Ecole Nationale d'Ingenieurs de Tunis (2)Ecole Nationale d'Ingenieurs de Monastir-Departement de Genie Electrique- (3)CSR Groupe du laboratoire EflE de la FSM de Monastir Abstract-Proportional-Integral-Derivative (PID) controllers are widely used in automation systems. They are usually implemented either in hardware using analog components or in software using computer-based systems. They may also be implemented using Application Specific Integrated Circuits (ASICs). This paper outlines a methodology for building PID controllers on Field Programmable Gate Arrays (FPGAs) which improve speed, accuracy, power, compactness, and cost effectiveness. I. INTRODUCTION The modern digital control systems require more and more strong and fastest calculation components. This type of elements becomes yet indispensable with the utilization of some new control algorithms like the fuzzy control, the adaptive control, the sliding mode control, ... [1]. Although the PID controllers are the oldest they represent the most used controllers in the industrial control systems. The PID algorithm consists of three basic modes, the Proportional mode, the Integral and the Derivative modes. When utilizing this algorithm it is necessary to decide which modes are to be used (P, I or D) and then specify the parameters (or settings) for each mode used. Generally, three basic algorithms are used P, PI or PID. The implementation of PID controllers using microprocessors and DSP chips is old and well known [2][3], whereas very little works can be found in the literature on how to implement PID controllers using FPGAs [4]. Field Programmable Gate Arrays (FPGA) have become an alternative solution for the realization of digital control systems, previously dominated by the general purpose microprocessor systems. In our work, we introduce a simple method for implementing PID controllers. Some other contributions focused on proposing algorithms for tuning the coefficients of PID controllers using FPGAs while the controller itself is still implemented in software. In [5] the authors describe the architecture of a data acquisition system for a gamma ray imaging camera. In the past two years, Spartan II and III FPGA families from Xilinx have been successfully utilized in a variety of applications which include inverters [6][7], communications [8][9], embedded processors [10], and image processing [11]. In our work, data acquisition for the PID controller, which is implemented using Xilinx Spartan-3 Starter Kit Board, is based on 8-bitserial AID converters extensible from Digilent board AO 1. Similar converters are utilized in [12] to implement an adaptable strain gage conditioner using FPGAs. The organization of this paper is as follows. In section II, an improved PID equation is considered and in section III we present the PID discrete architecture, we introduce the operating mode of serial analog to digital (AD7823) and serial digital to analog (AD7303) converters. Finally, we present the FPGA Based PID Controller Implementation results. Finally, in Sections IV we describe the implementation results. II. EQUATION OF DISCRETE PID The application of a PID controller in a feedback control system is shown in Fig. I, where ref is the setpoint signal, y is the feedback signal, e is the error signal, and u is the control input. Figure I. A PID-based feedback control system The simplest form of the PID control algorithm is given by: 1

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Page 1: [IEEE 2008 3rd International Design and Test Workshop (IDT) - Monastir, Tunisia (2008.12.20-2008.12.22)] 2008 3rd International Design and Test Workshop - PID control implementation

PID Control Implementation using FPGA TechnologyAbdesselem TRIMECHE(l), Anis SAKLy(I,2), AbdelatifMTIBAA(2,3),

Mohamed BENREJEB (1)

[email protected] , [email protected] , [email protected] ,

mohamed. benrejeb@enit. rnu. tn

(1)Unite de recherche LARA Automatique de l'Ecole Nationale d'Ingenieurs de Tunis

(2)Ecole Nationale d'Ingenieurs de Monastir-Departement de Genie Electrique­

(3)CSR Groupe du laboratoire EflE de la FSM de Monastir

Abstract-Proportional-Integral-Derivative (PID)controllers are widely used in automation systems.They are usually implemented either in hardwareusing analog components or in software usingcomputer-based systems. They may also beimplemented using Application Specific IntegratedCircuits (ASICs). This paper outlines a methodologyfor building PID controllers on Field ProgrammableGate Arrays (FPGAs) which improve speed, accuracy,power, compactness, and cost effectiveness.

I. INTRODUCTION

The modern digital control systems require moreand more strong and fastest calculationcomponents. This type of elements becomes yetindispensable with the utilization of some newcontrol algorithms like the fuzzy control, theadaptive control, the sliding mode control, ... [1].Although the PID controllers are the oldest theyrepresent the most used controllers in the industrialcontrol systems.The PID algorithm consists of three basic modes,

the Proportional mode, the Integral and theDerivative modes. When utilizing this algorithm itis necessary to decide which modes are to be used(P, I or D) and then specify the parameters (orsettings) for each mode used. Generally, three basicalgorithms are used P, PI or PID.

The implementation of PID controllers usingmicroprocessors and DSP chips is old and wellknown [2][3], whereas very little works can befound in the literature on how to implement PIDcontrollers using FPGAs [4].

Field Programmable Gate Arrays (FPGA) havebecome an alternative solution for the realization ofdigital control systems, previously dominated bythe general purpose microprocessor systems.In our work, we introduce a simple method forimplementing PID controllers. Some othercontributions focused on proposing algorithms fortuning the coefficients of PID controllers usingFPGAs while the controller itself is stillimplemented in software.

In [5] the authors describe the architecture of adata acquisition system for a gamma ray imagingcamera.In the past two years, Spartan II and III FPGAfamilies from Xilinx have been successfully utilizedin a variety of applications which include inverters[6][7], communications [8][9], embeddedprocessors [10], and image processing [11].In our work, data acquisition for the PID controller,which is implemented using Xilinx Spartan-3Starter Kit Board, is based on 8-bitserial AIDconverters extensible from Digilent board AO1.Similar converters are utilized in [12] to implementan adaptable strain gage conditioner using FPGAs.

The organization of this paper is as follows. Insection II, an improved PID equation is consideredand in section III we present the PID discretearchitecture, we introduce the operating mode ofserial analog to digital (AD7823) and serial digitalto analog (AD7303) converters. Finally, we presentthe FPGA Based PID Controller Implementationresults. Finally, in Sections IV we describe theimplementation results.

II. EQUATION OF DISCRETE PID

The application of a PID controller in a feedbackcontrol system is shown in Fig. I, where ref is thesetpoint signal, y is the feedback signal, e is theerror signal, and u is the control input.

Figure I. A PID-based feedback control system

The simplest form of the PID control algorithm isgiven by:

1

Page 2: [IEEE 2008 3rd International Design and Test Workshop (IDT) - Monastir, Tunisia (2008.12.20-2008.12.22)] 2008 3rd International Design and Test Workshop - PID control implementation

(1)

(3)

u(t) = k (e(l)+...!..- fe(l)dl +Td

de(l))P T dt

i

According to the study done in [13] the digitizedPID equation is brought back to:

uk =U k - 1 +bo ·ek +b1 ·e(k -1)+b2 ·e(k -2) (2)

Where the coefficients bo, bI, and b2 are evaluatedby the expressions:

b = k . (1 + Td).

OPT '

(T Td )b =k . -1+--2·- ;

I P T Ti

use an on-board 5VDC voltage source. All unusedI/O signals are passed through the AID 1 board sothat it can be used between a system board andother peripheral boards.

The AIOI uses a 8-bit, 200Ks analog to digitalconverter (the AD7823), and a 8-bit, 1 MHz digitalto analog converter (the AD7303), both fromAnalog Devices. The AD8534 op amps (also fromAnalog Devices) can drive 250mA outputs rail-to­rail with a 3 MHz bandwidth, so many usefuldevices can be driven directly.

B. Analog input interface

~r=r.: ~.rading : :.1

: ~ .

eLK I FPGA ~d30nv~ AD7823

---:-:-i~~ ~ Convst

FPGAs are well suited for serial Analog to Digital(AID) converters. This is mainly because serialinterface consumes less communication lines whilethe FPGA is fast enough to accommodate the highspeed serial data. The AD7823 is a high speed, lowpower, 8-bit AID converter. The part contains a 4Jl s typical successive approximation AID converterand a high speed serial interface that interfaceseasily to FPGAs. The AID interface adapter(ADIA) is implemented within the FPGA (Fig. 3).Inside the FPGA, this adapter facilitates paralleldata acquisition. Sampling is initiated at the risingedge of a clock applied at the line sample. Thetiming diagram of the communication protocol isillustrated in Fig. 4. The whole conversion andacquisition period is 5.4 JlS allowing sampling up toa rate of 185 Kilo Sample per second. This rate ismore than sufficient for most PID controlapplications.

Vin+

Sclk

~d_sclk 1 .......ADIA

To improve the speed and minimize the cost whileoffering clearly good performances, the adoptedarchitecture used includes essentially threecombinational logic multiplier, one substractor,three adders and three registers. The Fig. 2 givesthe adopted architecture.Indeed, this architecture requires the availability ofall calculation operators in each phase.

III. DIGITAL PID ARCHITECTURE

Tdb =k .-

2 P T

The kp , Ti and Td, are PID parameters for tuning,and T is the sampling period in seconds.

Figure 2. Pill ArchitectureFigure 3. AID interface converter

A. Conversions blocks

The AID1 board is a peripheral board designed towork with Digilent's family of system boards. TheAID1 contains analog to digital and digital toanalog converters from Analog Devices, two dualop amps, a variety of analog signal I/O connectors,and a solderless breadboard. All analog components

II,.01010101'

NOI¥ mIlns

Figure 4. Timing diagram of AD7823

2

Page 3: [IEEE 2008 3rd International Design and Test Workshop (IDT) - Monastir, Tunisia (2008.12.20-2008.12.22)] 2008 3rd International Design and Test Workshop - PID control implementation

The output coding of the AD7823 is straightbinary. The designed code transitions occur atsuccessive integer LSB values (i.e., 1 LSB, 2 LSBs,etc.). The LSB size is = VREF/256.

c. Analog output interface

The AD7303 is a dual, 8-bit voltage out Digital toAnalog (DfA) converter. This device uses aversatile 3-wire serial interface that operates at aclock up to 30 MHz. The serial input register is 16bits wide; 8 bits act as data bits for the DfAconverter, and the remaining 8 bits make up acontrol register. It is interfaced to an FPGA asillustrated in Fig. 5. The DfA interface adapter(DAIA), which is implemented within the FPGA,facilitates parallel data input for the dual DfAconverters. The timing diagram of thecommunication protocol is illustrated in Fig. 6. Thetransmission period of a sample is 680 ns allowingDfA conversion at an excellent rate of 1.47 MHZ.

IV. IMPLEMENTATION RESULTS

The proposed based PID controller is implementedusing the Xilinx Inc FPGA technology and can beused as a general purpose controller for differentapplications. The simulation results obtained withthe generated VHDL, in this work, the ModelSim®simulator was used. The circuits for the PIDcontrollers have been obtained by logic synthesisand place and route using Xilinx ISE 7.1 i, from theVHDL representation generated by the staticanalyzer. We use a Xilinx Spartan-3 xc3s200-ft256-4 FPGA (fig. 7). The results presented herein areestimations directly obtained from Xilinx ISE 7.1 i.

AD7303

~ SYNCVin+ "'~I-+---

Figure 5. ND interface converter

TABLE I. Number of arithmetic operations for PID control

Table I shows the mInImum number ofmultiplications, additions and registers required forthe PID controller without conversions block.

Figure 7. Design properties

Multiplication 3

Addition 3subtraction 1register 3

total 10

Vin- I"'~"""""'--

~ Sdk

l····················;;~~····················l

CLK I..... 4tc_SYNC

I~ DAIA $c_sclk

! ~ac_dinSampl~ .......----........~.. DIN

(reset) I , 1...-.----.......

- .,j':"'J~_,~ '_"~': :;;1._ :i ;(

./~Jestmlld5:-'ill!o

The PID controller block, into a complete controlsystem consisting of analog and digital I/O, isillustrated in Fig. 8.

ref(70)

Figure 6. Timing diagram of AD7303

Any DAC output voltage can ideally be expressedas:VOUT = 2 x VREF x (Nf256) where: N is thedecimal equivalent of the binary input code. An Nrange from 0 to 255xVREF is the voltage applied tothe external REF pin when the external reference isselected and is VDDf2 if the internal reference isused.

Inputs ofVHDLalgorithm

dac_sclk

reading(70)

reset u(70)

Figure 8. PID Controller Block

Outputs ofVHDLalgorithm

The simulation results adapted to this block areshown in Fig. 9.

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Page 4: [IEEE 2008 3rd International Design and Test Workshop (IDT) - Monastir, Tunisia (2008.12.20-2008.12.22)] 2008 3rd International Design and Test Workshop - PID control implementation

VI. REFERENCES

Figure 9. Simulation diagram ofPID controller block

[1] L. Samet, N. Masmoudi, M.W. Kharrat, L. Kamoun, "ADigital PID Controller for Real Time and Multi LoopControl", 5eme Colloque d'Informatique Industrielle CIr988,9 et 10 fevrier I998,Djerba Tunisie

[2] H. D. Maheshappa, R. D. Samuel, A. Prakashan, "DigitalPID controller for speed control of DC motors", IETETechnical Review Journal, V6, N3, PPI71-176, India 1989

[3] J. Tang, "PID controller using the TMS320C31 DSK withon-line parameter adjustment for real-time DC motor speedand position control", IEEE International Symposium onIndustrial Electronics, V2, PP 786-791, Pusan 2001.

[4] Mohamed Abdelati, the Islamic University of Gaza, Gaza,Palestine "FPGA-Based PID Controller Implementation".

[5] K. Nurdan, T. Conka-Nurdana, H. J. Beschc, B.Freislebenb, N. A. Pavelc, A. H.Walentac, "FPGA-baseddata acquisition system for a Compton camera",Proceedings of the 2nd International Symposium onApplications of Particle Detectors in Medicine, Biologyand Astrophysics, V510, Nl, PP. 122-125, Sep 2003.

[6] R. Jastrzebski, A. Napieralski,0. Pyrhonen, H. Saren,"Implementation and simulation of fast inverter controlalgorithms with the use of FPGA circuit", 2003Nanotechnology Conference and Trade Show, pp 238-241,Nanotech 2003.

[7] Lin, F.S.; Chen, J.F.; Liang, T.J.; Lin, R.L.; Kuo, Y.C."Design and implementation of FPGA-based single stagephotovoltaic energy conversion system", Proceedings ofIEEE Asia Pacific Conference on Circuits and Systems, pp745-748, Taiwan, Dec. 2004.

[8] Bouzid Aliane and Aladin Sabanovic, "Design andimplementation of digital band pass FIR filter in FPGA",Computers in Education Journal, v14, p 76-81, 2004.

[9] M. Canet, F. Vicedo,V. Almenar, J. Valls, "FPGAimplementation of an IF transceiver for OFDM­basedWLAN", IEEEWorkshop on Signal ProcessingSystems, SiPS: Design and Implementation, PP 227-232,USA 2004.

[10] Xizhi Li, Tiecai Li, "ECOMIPS: An economic MIPS CPUdesign on FPGA", Proceedings - 4th IEEE InternationalWorkshop on System-on-Chip for Real-Time Applications,PP 291-294, Canada 2004.

[11] R. Gao, D. Xu,J. P. Bentley, "Reconfigurable hardwareimplementation of an improved parallel architecture forMPEG-4 motion estimation in mobile applications", IEEETransactions on Consumer Electronics, V49, N4,November 2003.

[12] S. Poussier, H. Rabah, S. Weber, "Smart Adaptable StrainGage Conditioner: Hard- ware/Software Implementation",IEEE Sensors Journal, V4, N2, Apri12004.

[13] L. Samet, "Etude de l'integration electronique entechnologie FPGA d'un algorithme de contrOle deprocessus: Ie PID" These Docteur Ingenieur, ENIS­TUNISIE, decembre 1996

173-"8-tUnber of GClKs:

IPUdJer used as logic:

Figure 10. Devices utilizations summary for the PID controllerImplementation

V. CONCLUSION

'tUnber of SIces~ onty reIad*tUnber of Slices~wnIIUd logic:

iTGUlIIun1ber .....LUI.

A design which is efficient in terms of powerconsumption and chip area means that the FPGAchip can be used to accommodate more controllerswith adequate speed and low power consumption,resulting in a cost reduction of the controllerhardware.

IIUftber of 4qu lUTs:I"'"of Slice FIp flaps:

Device Utization Sll1llnarYf["~--"------' --'-~--"'--

The synthesis of PID controller block using aXilinx Spartan-3 xc3s200-ft256 -4 FPGA gives thefollowing results (Fig. 10).

A digital PID controller implemented in FPGAtechnology is a configurable controller in terms oflatency, resolution, and parallelism.

The speed or execution or latency of the controllercan be precisely controlled with the amount ofreuse of arithmetic elements such as the speed ofexecution of FPGA based PID controller can be lessthen 100 ns if desired for high throughputrequirements.

Implementing PID controllers on FPGAs featuresspeed, accuracy, power, compactness, and costimprovement over other digital implementationtechniques.

In a future work, we plan to investigateimplementation of fuzzy logic controllers onFPGAs. Also we plan to explore embedded softprocessors, such as MicroBlaze, and study someapplications in which design partitioning betweensoftware and hardware provides betterimplementations.

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