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A Switched Gain Low Noise Amplifier for

Ultrawideband Wireless ApplicationsChang-Ching Wu', Albert Yen2, Yu Cheng', and Jen-Chung Chang'

'UMC, Hsinchu, Taiwan.

Abstract-A low-power switched gain low noise amplifier(LNA) is presented for ultrawideband (UWB) wirelessapplications. The proposed topology is co-designed withtransmit/receive (T/R) switch for Mode 1 OFDMapplications and the integrated circuit is implemented ina 0.13jm CMOS technology. The measurement resultsshow a gain-switch of 10dB where s21 in the frequencyband of interest is 17.4-19.2dB at high gain mode (HG)and 8.8-9.1dB at low gain mode (LG). The sll is lowerthan -17dB for both modes. The circuit gives noise figuresof 3.3-3.9dB at HG and 4.8-7.9dB at LG. The input ldBcompression points (PldB) are -28dBm at HG and-2OdBm at LG. Biased by an internal gm bias circuit, thepower consumptions of the core circuit are 5.7mW and5.2mW for HG and LG, respectively.

Keywords-CMOS, low noise amplifier, LNA, switchedgain, transmit/receive switch, T/R switch, ultrawideband,UWB.

I. INTRODUCTION

As ultrawideband (UWB) technology is emerging inhigh-speed wireless applications, full integration and hencelow cost as well as low power consumption are among themain topics in developing the commercial products. CMOStechnology is obviously a superior candidate forimplementing UWB applications.

As a main function block in the RF receiver front-end, alow noise amplifier (LNA) plays a critical role of amplifyingthe weak signal received at antenna while adding less noise.Input impedance match is usually critical in reducing RFsignal loss and considering the preceding discrete bandpassfilter. For UVvB wireless applications, an LNA needs tomeets all these requirements while operating in ultra-widebandwidth.

In the transceivers of MB-OFDM system [1], the LNAneeds to provide high gain and low noise to raise the receivedsignal which is close to noise floor. On the other hand, such ahigh gain may cause sever nonlinearity in the succeedingfunction blocks when the maximum signal power is fed.Normally operating in high gain mode (HG), an UWB LNAneeds to switch to low gain mode (LG) in the extremesituation.

This paper proposes a gain switch topology for two-stagestacked stagger tuning UWB LNA [2]. A co-design ofUWBLNA and UWB transmit/receive (T/R) switch [3] for Mode 1OFDM applications is adopted to implement the proposed

2UMC, Sunnyvale, CA, USA

IH(X)l (dB)ynthesized high gainain of lst stage (fixed)ain of 2nd stage @HGynthesized low gainain of 2nd stage @LG

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L.T. system H(j)=Hlo1j)H2(j X)

Fig. 1. Concept ofthe proposed gain switch function.

topology. The experimental results verify the gain switchfunction while keeping good gain curve flatness and inputimpedance match over the 3.1-4.8GHz frequency band.

II. DESIGN CONCEPT

In a two-stage stagger tuning LNA, UWB gain is achievedby passing RF signal serially through two amplificationstages whose resonant frequencies are designed close tolower and upper edges of the band, respectively. Assumesuch an LNA is a linear time-invariant (LTI) system. Givenimpulse responses of 1St and 2nd stages are hl(t) and h2(t),respectively, the system impulse response is h(t)=hl(t)*h2(t).In frequency domain, the system frequency response isH(jcw)=Hl(jco)H2(jco). Depicted in Fig. 1, an intuitive idea toswitch the system gain 1H11cU)l is to adjust either Hlco) orH2(1c0); that is, to adjust frequency response of either I'tstage or 2nd stage. For a LNA, the input stage dominatescircuit noise figure (NF) and is part of the input impedancematching network. Thus the 2nd stage may be the right onefor implementing gain switch function.As illustrated in Fig. 2, the transistors MI is in the I't stage

to amplify the RF signal and both the transistors M2 and M3work for 2nd stage of amplification at high gain mode (HG).To move the gain curve of the 2nd stage 1H2(j0c)l downwardwithout shifting peak frequency at low gain mode (LG), weturn off the transistor M3 and turn on the transistor M4.There are two purposes for M4 on at LG. One is to providesupplemental bias current for the transistor MI that ispositioned at bottom of the current-reuse structure so that1H1(jwc)l and input impedance match are not be impacted bythe change in 2nd stage. The other is to offer parasitic

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capacitance for the resonance tank of the 2nd stage to makesure 1H2(j0c)l move downward due to reduced transconductor(gm2) and no lateral frequency shift. The capacitors Ci andC3 couple the RF signal from I't stage to 2nd stage. Thecapacitor C2 ties the transistor sources of M2 and M3 to acground so that I't and 2nd stages can be individualamplification stages. An inverter is adopted to have controlpin "HG" to handle gain switch.

III. CIRCUIT IMPLEMENTATION

A co-design of UWB LNA and UWB transmit/receive(T/R) switch for Mode 1 OFDM applications is adopted toimplement the proposed switched gain LNA. The UnitedMicroelectronics Corporation (UMC) 0.13m MMRF CMOSmodels and Process Design Kit (PDK) are applied to thisdesign. As shown in Fig. 3, the circuit consists of a LNAcore, a set of T/R switch (transistors M6 and M7) integratedwith the input match network, and an output buffer (transistorM5) for RF measurement. An internal gm bias circuit, notshown on the schematic, provides bias for transistor MI andthe current source of the output buffer.NMOS with minimum channel length (0. 12m) is adopted

for all the main transistors (MI-M7) and the multi-fingertransistor is built in the PDK. The input transistor MI hastotal width of 64ptm. With fine tuning by simulation, thetransistors M2, M3, and M4 are sized in total width of 7.8ptm,

Fig. 4. Chip photograph.

18.2pm, and 7.2pm, respectively, to meet the different gainrequirements.

The capacitors C6 and C7 are added in the tanks of 1St and2nd stages, respectively, to tune the resonant frequencies. Thecapacitance of C6 is 165fF and that of C7 is 52fF. The loadinductor LI is 1OnH and L2 is 4.7nH.

Each of the transistors M6 and M7 of the T/R switch has atotal width of 115.2 j m. The passive components L3=0.5nH,L4=3.4nH, L5=2.5nH and C4=220fF together with theparasitic capacitance of the T/R switch transistor are adoptedfor noise and impedance matching to the 50-Ohm source.The dc blocking capacitor C5=7.4pF is chosen to minimizethe signal loss. The shunt inductor L5 also serves as an RFESD protection device.

IV. EXPERIMENTAL RESULTS

Fig. 4 shows a photograph of the chip whose total area is1.35 mm2. The measurements were performed on wafer.Fig. 5 plots the measured input return losses of the circuit.sIt for both HG and LG is below -17dB through the entirefrequency band of interest. With all on-chip components andinternal bias, this excellent impedance match performanceencourages less off-chip components and more confidence onsimulation and the RF device model. The output return lossis shown in Fig. 6. Both HG and LG has s22 lower than-12dB. Fig. 7 shows the gain switch of 10dB where s2I in thefrequency band of interest is 17.4-19.2dB at HG and

Fig. 3. Schematic of the implemented circuit.

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Fig. 8. Measured reverse isolation.

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Fig. 12. Measured Input P1dB at HG.

208.8-9.1dB at LG. The good gain curve flatness proves theproposed gain switch topology. The isolation higher than 40dB as shown in Fig. 8 is helpful to mitigate the issue of LOleakage to antenna in system integration. Fig. 9 shows noisefigure (NF) of 3.3-3.9dB at HG and 4.8-7.9dB at LG. Thehigh NF at LG will not affect the system sensitivity since theLNA operates at LG when the received RF signal is strong.

Two-tone tests at 4GHz with 1MHz spacing wereconducted and in Fig. 10 and Fig. lI the results show inputthird order intercept points (IIP3) of -1 8dBm and -1 OdBm atHG and LG, respectively. Fig. 12 and Fig. 13 plots input 1-dB

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Fig. 13. Measured Input P1dB at LG.

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Fig. 14. Measured Input PldB in the TX mode.

compression points (P1dB) of -28dBm and -2OdBm at HGand LG respectively. The measured linear gain in the PIdBtest is a little smaller than the gain in S-parameters becausethe former is conducted with the signal generator and thespectrum analyzer and the losses at the probes and some partsare not taken into account.

Fig. 14 shows an input P1dB of 8dBm at 4GHz in thetransmit (TX) mode. This power handling capability is verygood for the UWB transmitter whose output power is wellbelow OdBm.

The core circuit consumes 5.7mW and 5.2mW for HG andLG, respectively, from 1.2V supply. The output bufferdissipates 2. lmW. The gm bias circuit consumes 3.7mW. Themeasured performance is summarized in Table I.

TABLE ISUMMARY OF MEASURED PERFORMANCE

HG Mode LG ModePower Gain (dB) 17.4-19.2 8.8-9.1Noise Figure (dB) 3.3 - 3.9 4.8-7.9S11 (dB) <-18.2 <-17.0Isolation (dB) > 40.0 >40.0Input IP3 (dBm) -18 -10

Input P1dB (dBm) -28 -20DC Power (mW) 5.7 5.2Control Voltage (V) 0-1.2

Technolos4y 0.13 Ltm CMOS

[3] C. C. Wu, A. Yen, J. C. Chang, "A 0.13ptm CMOS T/Rswitch design for ultrawideband wireless applications,"2006 IEEE International Symposium on Circuits andSystems, pp. 3758-376 1, Greece, May 2006.

V. CONCLUSION

A switched gain UWB LNA has been proposed. Aco-design of UWB LNA and UWB (T/R) switch for Mode 1

OFDM applications is adopted to implement the proposedswitched gain LNA.

Operating in 3.1-4.8GHz, it provides 10dB gain switchbetween high and low gain modes with good gain flatness.The high gain is 17.4-19.2dB and low gain is 8.8-9.1dB.Noise figure is 3.3-3.9dB at high gain mode and 4.8-7.9dB atlow gain mode. The excellent input return loss well below-17dB encourages less off-chip components and more

confidence on simulation and the RF device model.Implemented in UMC 0.13 MMRF CMOS technology,

the experimental results demonstrate that the proposedswitched gain UWB LNA is paving the way to a new

generation of compact low power UWB wirelessapplications.

REFERENCES

[1] A. Batra, et al., "Multiband OFDM physical layerproposal for IEEE 802.15 task group 3a,"http://www.multibandofdm.org, Sep. 2004.

[2] C. C. Wu, M. F, Chou, W. S. Wuen, K. A. Wen, "A lowpower CMOS low noise amplifier for ultra-widebandwireless applications," 2005 IEEE InternationalSymposium on Circuits and Systems, pp. 5063-5066,Kobe, May 2005.

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