Simulink Based Real-Time Laboratory Course Development

James Kang, Brita Olson, Alan Felzer, Rajan Chandra, Salomon Oldak Department of Electrical and Computer Engineering

California State Polytechnic University, Pomona jskang@csupomona.edu

Abstract This paper describes Simulink based laboratory courses on discrete-time signals and systems, digital signal processing, and analog/digital communications. Sample experiments on modulator/demodulator design are briefly discussed. 1. Introduction Our goal is to develop real-time digital communications and signal processing labs in which students are asked to design and implement nontrivial systems on DSP and FPGA boards. We could ask the students to use C, Verilog, or VHDL. But this is really asking too much in the limited amount of time available for labs. Simulink is a much better choice because it takes care of many of the implementation details, but not all [1, 2, 3]. Simulink translates model into appropriate languages for the target boards. The codes generated from Simulink for the target boards are usually convoluted, and may not be the most efficient. But, the time it takes to implement complex systems using Simulink is considerably shorter than manually coding in C, Verilog, or VHDL. External signals can be interfaced to the target devices through ADCs and DACs [4]. Many basic blocks that work in the simulation may not work in the implementation with target boards [5]. The target boards for our labs include Texas Instruments’ C6713 DSK, Xilinx Spartan 3, Xilinx XUP Virtex-II Pro Development System, and PC. For Xilinx boards, in addition to the Xilinx ISE and Simulink, Xilinx System Generator for DSP is needed. Analog Devices boards and Altera boards can also be used. 2. Laboratory Courses Simulink based laboratory courses can be developed for discrete-time signals and systems, digital signal processing, and analog and digital

communications systems. Typical labs for a discrete-time signals and systems lab course include sampling and reconstruction, convolution, correlation, simple digital filters, sound effects, and FFT/IFFT. For digital signal processing laboratory course, the topics for experiments include IIR filter design, FIR filter design, adaptive filter design, power spectrum estimation, linear prediction, parameter estimation, and multirate filters. For communication systems laboratory course, the topics for experiments include source coding, modulator and demodulator design (AM, FM, ASK, FSK, PSK, CPM, QAM), pulse shaping, channel characteristics, equalizers, error detection and correction, interleaving, carrier synchronization, symbol synchronization, software defined radio (SDR), and orthogonal frequency division multiplexing (OFDM). 3. Modulator/Demodulator Design Fig.1 shows a frequency modulator/demodulator model. In the FM modulator subsystem shown in Fig.2, the gain is used to select the modulation index. The sum of the carrier radian frequency (normalized by sampling rate) and the input signal is applied to an accumulator (integrator), and then to user defined functions for rem(u,2*pi) and cos(u). The FM demodulator subsystem shown in Fig.3 consists of a multiplier, loop filter, voltage-controlled oscillator (VCO), and a lowpass filter. The loop filter is the same as the one shown in Fig.6 (proportional and integral). The VCO is identical to the FM modulator subsystem with gain set at one. Fig. 4 shows a model for BPSK modulator and demodulator implemented on DSP board. In this model, the binary data from Bernoulli binary generator is used, but the data can be from an external source through an ADC. In the model shown in Fig.4, the modulator and demodulator are in the same model. But, the modulator and

2007 IEEE International Conference on Microelectronic Systems Education (MSE'07)0-7695-2849-X/07 $20.00 © 2007

demodulator can be implemented on two separate boards and the two boards can be connected through wired or wireless radio.

Unbuffer

To WaveDevice

From WaveDevice

In1

In2Out1

FMMod

In1Out1

FMDemod

2*pi*3/40

Constant1

Buffer

Fig.1 FM modulator/demodulator.

1Out1

0.5

Gain

cos(u)

Fcn1

rem(u,2*pi)

Fcn

z-1

Delay

2In2

1In1

Fig.2 FM modulator subsystem.

1Out1

In1

In2Out1

VCO

Product

In1 Out1

LF0.1

Gain1

FDATool

Digi talFilter Design

2*pi*3/40

Constant

1In1

Fig.3 FM demodulator subsystem. The model shown in Fig.4 can easily be modified for other modulations such as ASK, FSK, QAM, etc.

Rate Transition

In1Out1

Modulator

In1Out1

Demodulator

C6713 DSKDAC

DAC1

C6713DSK

Bernoul liBinary

Bernoul li BinaryGenerator

Fig.4 BPSK modulator and demodulator model. The demodulator subsystem is shown in Fig.5. The demodulator subsystem consists of a carrier recovery subsystem and a correlator receiver. The carrier recovery subsystem consists of squarer, digital phase-locked loop (DPLL) and frequency divider connected in cascade. The DPLL subsystem shown in Fig.6 consists of the loop filter (proportional and integral) and a VCO. The frequency divider subsystem consists mainly of a D Flip-Flop, which is used as a binary counter. The data type conversion is

needed to convert Boolean format to double format.

LPF

1

Out1Product1

80

Downsample

DF FIR

Digital Filter2

z-4

Delay

In1Out1

CarrierRecovery

1In1

Fig.5 Demodulator subsystem.

1Out1

1

Kp

0.9

KI

z-1

Delay1

z-1

Delay

1In1

Fig.6 DPLL subsystem. 5. Conclusion In the paper, development of laboratory courses based on Simulink and target devices such as DSP boards, FPGA boards, and PC are discussed. 6. References

[1] John Turner and Joseph P. Hoffbeck,

“Putting Theory into Practice with Simulink,” Proceedings of the 2005 ASEE Annual Conference and Exposition.

[2] Lisa Huettel and Leslie M. Collins, “A Vertically-Integrated Application-Driven Signal Processing Laboratory,” Proceedings of the 2005 ASEE Annual Conference and Exposition.

[3] Chris Dick, Fred Harris and Michael Rice, “FPGA Implementation of Carrier Synchronization for QAM Receivers,” Journal of VLSI Signal Processing 36, 57-71, 2004.

[4] James S. Kang and Alan P. Felzer, “A Digital Signal Processing Laboratory Course Using Field Programmable Gate Array Boards,” Proceedings of the 2005 ASEE Annual Conference and Exposition.

[5] Michael A. Shanblatt and Brian Foulds, “A Simulink-to-FPGA Implementation Tool for Enhanced Design Flow,” Proceedings of the 2005 IEEE International Conference on Microelectronic Systems Education.

2007 IEEE International Conference on Microelectronic Systems Education (MSE'07)0-7695-2849-X/07 $20.00 © 2007