Scheduling Semiconductor Wafer Fabrication with Optimization of Multiple objectives*

Zuntong Wang, Fei Qiao, and Qidi Wu School of Electronics & Information Engineering.

Tongji University Shanghai, China

wangzt@mail.tongji.edu.cn

.Abstract –CPC is a compound priority control strategy used for scheduling semiconductor wafer fabrication. The compound priority of wafers is calculated according to their current processing step, to the amount of wafers waiting for processing in current step buffer, in upstream step buffer, and in downstream step buffer. Wafers with the highest compound priority are dispatched to certain machine to be processed. Compared to common used scheduling strategies, CPC strategy exhibits high performance in reducing total amount of WIP, decreasing cycle time and its standard deviation, and increasing the throughput rate.

Index Terms –Semiconductor manufacturing; compound priority; scheduling; lot release; multi-objective optimization.

I. INTRODUCTION

Semiconductor manufacturing (SM) is one of the fastest growing industries in the world today. Moreover, SM is one of the most complex production systems due to the intricate manufacturing processes involved as well as the range of product types. Any technology that increases factory output by even modest amounts can have significant impact on the manufacturers’ bottom line.

Semiconductor manufacturing system is considered as the third class manufacturing system, which is labelled as re-entrant lines [1]. Traditionally, manufacturing systems have mainly been classified into job shops and flow shops. While in a semiconductor wafer fabrication facility (often referred to as wafer fab), wafers are put in a special box (referred to as lot), and flow in a specific process route. The expensive machine is not assigned entirely to a specific processing step, but re-visited by the wafers (lots) at different stages. The re-entrance characteristic of the wafer fab increases the competition of lots for machine, and consequently, prolongs significantly the time that lots spend to wait for processing. Therefore, the processing sequence of lots should be scheduled under certain disciplines so as to improve the wafer fab’s performances, and to meet the customer’s need for due date.

. * This work is partially supported by the National Basic Research Program (973) of China (under grant 2002CB312202-03), the National Science Foundation of China (under grant 70531020), and the Chinese Postdoctoral Fellowship Foundation (under grant 2004036343).

II. LITERATURE REVIEW

In semiconductor wafer fabrication, multiple performance measures should be optimized at the same time, such as reducing inventories, decreasing cycle time and its standard deviation, and improving the utilization of resources, etc. This optimization depends highly on appropriate scheduling strategy and lot release strategy. The scheduling strategy determines when specified lot(s) is/are processed by a specific machine, while the lot release strategy determines when and how many lots are released into the wafer fab.

An early study by Wein [2] represents simulation researches on lot release strategies and scheduling strategies in semiconductor fabrication environment. The results reveal that both lot release and scheduling have significant impacts on wafer’s average cycle time, while the effects of specific sequencing rules used for selecting lot(s) to fabricate are highly dependent upon both the type of lot release strategy and the number of bottleneck workstations in the fab. Spearman et al. [3] describe a pull-based lot release strategy, CONWIP, which can keep a constant amount of WIP (Work-In-Process) in the fab. Rose [4] proposes a new lot release strategy, CONLOAD, which can keep the utilization of bottleneck machines at a desired level and provide a smooth evolution of the WIP.

Uzsoy et al. [5, 6] describe the characteristics of various approaches to the shop-floor control problem in semiconductor manufacturing. Mittler et al. [7, 8] present a comparison of performance of the dispatching rules using simulation results for two large semiconductor wafer fabrication facilities. The results show that which dispatching rule achieves the best results depends on the fab, on the load of the fab and on the product, while the efficiency of dispatching rules that utilize only local information is very limited in reducing the effects of variability on cycle times. Vargas-Villamil and Rivera [9] investigate a two-layer production control method that is applied to a semiconductor re-entrant line. Results show that this approach is able to maximize or track the desired production rate while keeping in-process inventories at desired levels. Lee and Kim [10] discuss how to control the balance of WIP flow to achieve maximum throughput under short manufacturing cycle times. Experiments show that balance driven management leads to 15-33% more production in 21% shorter manufacturing cycle time than production driven management. Oey and Mason [11]

Proceeding of the 2006 IEEEInternational Conference on Automation Science and EngineeringShanghai, China, October 7-10, 2006

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develop a modified shifting bottleneck (MSB) scheduling approach to minimize the total weighted tardiness.

Dabbas et al. [12] propose a modified dispatching approach that combines multiple dispatching criteria into a single rule to optimize multiple performance measures. They represent the use of experimental design methodology as well as a desirability function approach in the optimization of the weights' assignment to different criteria. Results using the new approach show significant improvement versus the use of a single dispatching criterion [13, 14]. Qu and Mason [15] present two meta-heuristic solution approaches for scheduling of 300-mm lots containing multiple orders under two different typical wafer fab environments: single unit processing and single lot processing. Experimental results demonstrate that the meta-heuristic approaches can find near-optimal solutions for realistic-sized 300-mm scheduling problems in an acceptable amount of computation time.

Wu and Yeh [16] propose a drum development method for semiconductor manufacturing environments with bottleneck re-entrant flows. They represent a numeric example and a real-life IC substrate manufacturing case utilized to evaluate the application of the proposed method. Employing this proposed methodology, they implement a drum-buffer-rope (DBR) management system that effectively increases throughput, lowers work in process, shortens cycle time, and improves on-time delivery performance. M. T. Zhang [17] describes some practical storage management approaches to adjust wafer distribution in the factory to improve manufacturability by taking advantages of the data warehouse capability of various automation systems.

In this paper, we use a new compound priority control strategy, CPC, to optimize multiple objectives of semiconductor wafer fabrication. The CPC strategy can balance the amount of WIP at different processing steps, and avoid overstock of wafers waiting for processing at different stages.

III. THE DESCRIPTION OF CPC STRATEGY

An ideal situation is that all performance measures of the wafer fab are optimized at the same time. But it cannot be achieved in practice, because some performance measures conflict with the others. From the viewpoint of practical optimization, it is reasonable to compromise among some conflicting performance measures, which can be optimized together to certain extent. For example, the average cycle time and the amount of WIP can be decreased to a certain level, while the throughput rate keeps a relatively high standard. It is the motivation that we pursue to seek for a wafer fab scheduling strategy with the ability of optimizing multiple performance measures.

Firstly, the related concepts are explained. Ji (i = 1, 2, …, n) is the job corresponding to the ith processing step, e.g. J1 is the job corresponding to the first processing step. BFi is the buffer where job Ji waits for processing, and Birepresents the number of jobs Ji waiting for processing in BFi. BiM is the maximum capacity of buffer BFi, and Bim

the minimum capacity of BFi. In the above description, n is the number of total steps in a process route.

The compound priority of wafers is calculated according to their current processing step, to the amount of wafers waiting for processing in the current step buffer, in the upstream step buffer, and in the downstream step buffer, etc. In other words, the CPC strategy controls the processing sequence of lots according to certain global information of the wafer fab. The compound priority is composed of the following sub-priority items:

A. Sub-priority pin

It is a sub-priority assigned only to the new lots which are released into the fab to be processed. When certain amount of lots has finished their processing route and flows out the fab, the new lots gain the sub-priority pin for processing their first step. In this paper, let pin equals 1, when there are 3 lots flow out the fab; let pin become 0 when 3 new lots are processed their first step.

B. Sub-priority pBi

It is a sub-priority given to lots waiting for processing in buffer BFi. The value of pBi varies with the number of jobs (lots) Ji in buffer BFi, calculated as:

,,,

3

2

1

imi

imiiM

iMi

Bi

BBCBBBC

BBCp . (1)

where C1, C2, and C3 are constants of pBi for different Bi(number of jobs Ji). It is need to point out that C3 may be assigned negative value. In this paper, let C1 = 1, C2 = 0, and C3 = -1.

C. Priority pBi+1

It is a sub-priority given to lots waiting for processing in buffer BFi, which varies with the number of jobs Ji+1 of the downstream processing step, i.e. the number of lots waiting for processing in buffer BFi+1. Sub-priority pBi+1 is represented as following:

,,,

113

1112

111

1

mii

miiMi

Mii

Bi

BBDBBBD

BBDp . (2)

where D1, D2, and D3 are values of pBi+1 for different Bi+1(number of jobs Ji+1). D1 may be assigned negative value. In this paper, let D1 = -1, D2 = 0, and D3 = 1.

D. Priority pBi-1

It is a sub-priority given to lots waiting for processing in buffer BFi, which varies with the number of jobs Ji-1 of the upstream processing step, i.e. the number of lots waiting in buffer BFi-1. Sub-priority pBi-1 is in reverse with the sub-priority pBi+1, and represented as following:

,,,

113

1112

111

1

mii

miiMi

Mii

Bi

BBEBBBE

BBEp . (3)

254

where E1, E2, and E3 are the values of pBi-1 for different Bi-1(number of jobs Ji-1). E3 may be assigned negative value. In this paper, let E1 = 1, E2 = 0, and E3 = -1.

E. Priority pJi

It is a sub-priority given to lots at different processing stages. The job Ji with higher foot number, i.e. near to the end of process route, has higher sub-priority pJi. In this paper, pJi is calculated as:

nipJi / . (4)

F. FIFO rule

FIFO rule works when jobs in the same buffer compete with each other for processing.

In the above sub-priorities, pin aims at reducing the amount of WIP in the fab. Sub-priorities pBi, pBi-1 and pBi+1represent that the amounts of jobs waiting in the buffers of the current step, the upstream step, and the downstream step have influence on the priority of lots waiting for processing in buffer BFi respectively. The objectives of these sub-priorities are to balance the WIP in different process steps, to reduce the overall number of the WIP, and to lower the cycle time and its standard deviation. Sub-priority pJi has the effect to reduce the mean cycle time. While the FIFO rule works in the same process step buffer, which aims to reduce the standard deviation of the cycle time. Consequently, the CPC strategy has the potential to optimize multiple performance measures.

The compound priority Pi of lots waiting for processing in buffer BFi is calculated as bellow:

ni,ppp1n2,3,...,i,pppp

1i,pppP

Jn)n-1B(nB

Ji1Bi1BiBi

J1B2in

i. (5)

In Equation (5), n is the total steps in a complete process route. By comparing the compound priority of jobs waiting for processing in all buffers before a specific machine, the CPC strategy determines which lot(s) is/are processed when the machine is available. Furthermore, if re-entrance exists in the first machine (or machine group) which deals with the first process step of a specific process route, new lots released into the fab compete with re-entrant lots for processing. Only if the new lots have higher compound priorities than the re-entrant lots, they would be processed by the idle machine. Therefore, it is the CPC strategy that determines the actual time when the new lot(s) is/are processed in the fab.

IV. SIMULATION

A. The Wafer Fab Model

A typical semiconductor wafer fab produces several products concurrently, and contains hundreds of different machines and tools. Few machines are used for only one dedicated processing step, while most machines are designed to carry out several very similar operations during the whole processing sequence and for multiple

products. Machines of the same type are usually grouped into work stations for several reasons: reduction of setup time, redundancy in case of breakdowns, efficient utilization of operators, and having backup when maintenance work is done [8].

Wein [2] describes a wafer fabrication model in which each lot has a uniform process route that consists of 172 total steps at the 24 different work stations, i.e., 172n .The model has three versions which are referred to as fab 1, fab 2, and fab 3 respectively. The main difference among the three fabs is the numbers of identical machines in some work stations. Therefore the bottlenecks in the three fabs are different. Fab 3 has four stations that are heavily utilized, and is selected for the simulation model in this paper. But it is necessary to point out that the practical utilization of work stations varies with lot release strategy and scheduling strategy used. The sequence of stations to

be visited in the process flow is shown in Fig. 1, and the basic parameters describing fab 3 are shown in Table 1.

As shown in figure 1, most work stations are re-visited more than one time, e.g. the photolithographic exposure station (station 14) is re-visited 12 times, and the resist strip station (station 23) 23 times. The model exhibits the re-entrance characteristic existed in the process route of wafer fabrication.

Some column names in Table 1 are interpreted just under the table. While the rest column names are explained respectively as bellow:

SMPT is the sum of mean processing time (hr.) that a work station spent in a specific process route, which is represented as:

LNVMPTSMPT / . (6) MPT/M is the mean processing time (hr.) each machine

of the work station spend in a specific process route, which is represented as:

NMSMPTMMPT // . (7) MU is the maximum utilization of a work station, which

is calculated as:

Enter 1 2 13 14 23 15 20 22 23 22 17 13 14

15 23 16 24 23 22 17 1 8 4 22 22 1 2 8

13 14 18 23 15 16 23 18 22 1 1 13 14 23 15

16 24 23 22 17 1 2 8 9 21 22 1 4 22 22

1 2 13 14 23 15 16 24 24 23 22 17 24 1 2

7 1 3 22 13 15 23 22 22 22 17 13 14 18 23

15 16 20 23 1 17 1 1 3 13 14 16 24 23 22

17 9 21 1 3 13 14 15 23 15 16 24 23 22 1

7 1 3 13 14 23 15 16 23 15 16 24 23 22 17

1 3 10 22 12 6 22 6 1 1 4 10 19 23 1 10

13 14 16 21 12 13 14 18 23 15 15 15 16 19

23 22 17 11 13 14 15 21 23 5 Exit

Fig. 1 Process flow [2]

255

%100MTTRMTBF

MTBFMU . (8)

TNMPT represents the total net mean processing time in a full process route, which is calculated by the following equation:

LNVMPTTNMPT / . (9) In this wafer fab model, TNMPT equals to 549.3 hours.

B. Simulation Results

In order to verify the performance of the CPC strategy, simulations has been implemented on the wafer fab model, fab 3 described above. The FIFO and SRPT strategies have been used for comparison of performances. The deterministic time interval strategy is used to control the lot release rate, and 26, 30, 34, 38, 42, 46, and 50 (hr.) are used respectively as the time intervals (referred to as TIR)between two new lots are released into the fab. The simulation time period is 3 years (25920 hours), and the warm-up time is 6 months (4320 hours). The performance measures used for comparison are the mean cycle time (MCT) and its standard deviation (St. Dev.), the throughput rate (TR), the mean amount of WIP, the mean total queue time (MTQT), and the percent improvement in mean total

queue time for CPC and SRPT strategies as against that for FIFO strategy. Figure 2 shows the MCT for FIFO, SRPT, and CPC strategies for various TIR. Figure 3 shows the standard deviation of MCT for the three scheduling strategies for various TIR.

It can be seen from figures 2 and 3 that, both the MCTand the standard deviation of MCT for CPC are lower than that for FIFO and SRPT. The MCT and its standard deviation for the three scheduling policies decline with the increasing of TIR, but they have different inflexion where the downtrend slows down greatly if TIR increases. The inflexions of FIFO and SRPT appear where TIR is

Fig. 2 The Mean Cycle Time

TABLE IEQUIPMENT DESCRIPTION

Station No. Station Name Operation Type NM NV/L MPT SMPT MPT/M MTBF MTTR MU

1 CLEAN Deposition 1 19 1.55 29.45 29.45 42.18 2.22 95.0%2 TMGX Deposition 1 5 4.98 24.90 24.90 101.11 10.00 91.0%3 TMGX Deposition 1 5 5.45 27.25 27.25 113.25 5.21 95.6%4 TMGX Deposition 1 3 4.68 14.04 14.04 103.74 12.56 89.2%5 TU11 Deposition 1 1 6.14 6.14 6.14 100.35 6.99 93.5%6 TU43 Deposition 1 2 7.76 15.52 15.52 113.25 5.21 95.6%7 TU72 Deposition 1 1 6.23 6.23 6.23 16.78 4.38 79.3%8 TU73 Deposition 1 3 4.35 13.05 13.05 13.22 3.43 79.4%9 TU74 Deposition 1 2 4.71 9.42 9.42 10.59 3.74 73.9%

10 PLMSL Deposition 1 3 4.05 12.15 12.15 47.53 12.71 78.9%11 PLMSU Deposition 1 1 7.86 7.86 7.86 52.67 19.78 72.7%12 SPUT Deposition 1 2 6.10 12.20 12.2 72.57 9.43 88.5%13 PHPPS Lithography 2 13 4.23 54.99 27.50 22.37 1.15 95.1%14 PHGCA Lithography 3 12 7.82 93.84 31.28 21.76 4.81 81.9%15 PHHB Lithography 1 15 0.87 13.05 13.05 387.20 12.80 96.8%16 PHB1 Lithography 1 11 2.96 32.56 32.56 No Failure 100.0%17 PHF1 Lithography 1 10 1.56 15.60 15.6 119.20 1.57 98.7%18 PHJPS Lithography 1 4 3.59 14.36 14.36 No Failure 100.0%19 PLM6 Ethcing 1 2 13.88 27.76 27.76 46.38 17.42 72.7%20 PLM7 Ethcing 1 2 5.41 10.82 10.82 36.58 9.49 79.4%21 PLM8 Ethcing 1 4 7.58 30.32 30.32 36.58 9.49 79.4%22 PHWET Ethcing 1 21 1.04 21.84 21.84 118.92 1.08 99.1%23 PHPLO Resist Strip 1 23 1.09 25.07 25.07 No Failure 100.0%24 IMP Ion Implant 1 8 3.86 30.88 30.88 55.18 12.86 81.1%

NM: Number of Machines MTBF: Mean Time between Failures (hr.) NV/L: Number of Visit per Lot MTTR: Mean Time To Repair (hr.) MPT: Mean Processing Time (hr.)

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approximately 38 (hr.), while the inflexion of CPC appears at 34 (hr.).

The simulation results such as TR, WIP, MTQT, and the percent improvement in MTQT for the CPC and SRPT strategies versus the FIFO strategy are shown in figures 4, 5, 6, and 7 respectively.

From figure 4, it can be seen that the maximum throughput rate TR for FIFO is about 0.026 (lot/hr.) when TIR is 38 (hr.). The TR for SRPT is about 0.026 (lot/hr.) when TIR is not larger than 38 (hr.), and then the TR drops down with the increasing of TIR. The TR for CPC strategy reaches its maximum, 0.030 (lot/hr.), when TIR is 30 (hr.), and decreases obviously from about 0.029 (lot/hr.) when TIR increases from 34 (hr.). It can also be seen that the

throughput rates for the three scheduling strategies are almost overlapped with each other when TIR is larger than 38 (hr.).

From figure 5, it is observed that the amount of WIP for CPC strategy is the smallest. But when TIR is larger than 42 (hr.), the amounts of WIP for all the three strategies are almost the same.

Figure 6 shows the mean total queue time MTQT for the three strategies varying with the increasing of TIR. In fact, the variation trend of MTQT is similar to that of MCT, it is because MTQT = MCT – TNMPT, while TNMPT is a constant 549.3 (hr.) in the simulation model.

From figures 5 and 6, it is also observed that, both the WIP and the MTQT have an inflexion where their downtrends lower down when TIR is larger. The inflexion points for WIP and MTQT are just the same as that for MCT and its standard deviation.

Figure 7 shows the percent improvement in MTQT for CPC and SRPT strategies compared to FIFO strategy. It can be observed that the CPC strategy decreases the mean total queue time MTQT greatly compared to the FIFO strategy. The maximum percent improvement of MTQT for CPC strategy as against that for FIFO strategy is 89.43%, while the minimum is more than 50%. When TIR is lower, the SRPT strategy can also decrease the MTQT compared to FIFO. But when TIR is larger than 34 (hr.), the improvement of MTQT lowers down rapidly. While as the

Fig. 5 The WIP

Fig. 3 The Standard Deviation of MCT

Fig. 4 The Throughput Rate

Fig. 6 The Mean Total Queue Time

Fig. 7 The Percent Improvement of MTQT

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TIR increases nearly to 36 (hr.) or more, the MTQT for SRPT strategy is more than that for FIFO strategy.

In general, it is the best situation that a wafer fab has a high throughput rate, while the mean cycle time and its standard deviation are lower, and the WIP is in a reasonable range. From this point of view, CPC is preferred.

The CPC strategy decreases the mean cycle time MCTand its standard deviation, lowers mean amount of WIP,and reduces the mean total queue time MTQT than FIFO strategy or SRPT strategy. The mean total queue time for CPC strategy decreases more than 50% as against that for FIFO strategy. The CPC strategy can increase the throughput rate of the wafer fab with a maximum 0.03 (lot/hr.), while that for FIFO and SRPT is about 0.026 (lot/hr.). The reasonable range of time interval TIR of lot release for the CPC strategy is from 30 to 38 (lot/hr.).

V. CONCLUSION

CPC is a compound priority control strategy used to scheduling semiconductor wafer fabrication. The compound priority of each lot varies with its current processing step, the numbers of wafers in the current step buffer, in the upstream step buffer, and in the downstream step buffer. By comparing the compound priorities of wafers waiting for processing, the CPC strategy determines which lot(s) is/are processed when the machine is available. Compared to FIFO and SRPT strategies, the CPC strategy exhibits high performance in reducing the total amount of WIP, decreasing the mean cycle time MCTand its standard deviation St. Dev., lowering the mean queue time MTQT, and increasing the throughput rate TR.

We also notice that the CPC strategy has got preliminary good optimization results for a abstract wafer fab model, and its validity for practical wafer fab is need to be verified in practice use. Usually, in a practical wafer fab, there are many lots of wafers of different types of products with their specific processing routes. It is expected that, the CPC strategy will exhibits better validity in more complicated practical semiconductor manufacturing environment.

REFERENCES

[1] P. R. Kumar. ‘Re-entrant lines’, Queueing Systems, 1993, vol. 13, no. 2, pp. 87-110.

[2] L. M. Wein, ‘Scheduling semiconductor wafer fabrication’, IEEE Transactions on Semiconductor Manufacturing, 1988, vol. 1, no. 3, pp. 115-130.

[3] M. L. Spearman; , D. L. Woodruff & W. J. Hopp, ‘CONWIP: a pull alternative to kanban’, International Journal of Production Research, 1990, vol. 28, no. 5, pp. 879-894.

[4] O. Rose, ‘CONLOAD - a new lot release rule for semiconductor wafer fabs’, Proceedings of the 1999 Winter Simulation Conference, Phoenix, AZ, 1999, pp. 850-855.

[5] R. Uzsoy; C. Lee & L. Martin-Vega, ‘A review of production planning and scheduling models in the semiconductor industry, Part I: System characteristics, performance evaluation and production planning’, IIE Transactions on Scheduling and Logistics, 1992, vol. 24, no. 4, pp. 47-61.

[6] R. Uzsoy; C. Lee, & L. Martin-Vega, ‘A review of production planning and scheduling models in the semiconductor industry, Part II: Shop Floor Control’, IIE Transactions on Scheduling and Logistics, 1994, vol. 26, no. 5, pp. 44-55.

[7] M. Mittle; A. K. Schoemig & N. Gerlich, ‘Reducing the Variance of Cycle Times in Semiconductor Manufacturing Systems’, Proceedings of the International Conference on Improving Manufacturing Performance in a Distributed Enterprise: Advanced Systems and Tools, Edinburgh, UK, 1995, pp. 89-98.

[8] M. Mittler & A. K. Schoemig, ‘Comparison of dispatching rules for semiconductor manufacturing using large facility model’, Proceedings of the 1999 Winter Simulation Conference, Phoenix, AZ, 1999, pp. 709-713.

[9] F. D. Vargas-Villamil & D. E. Rivera, ‘Multilayer optimization and scheduling using model predictive control: application to reentrant semiconductor manufacturing lines’, Computers and Chemical Engineering, 2000, vol. 24, no. 8, pp. 2009-2021.

[10] Y. H. Lee & T. Kim, ‘Manufacturing cycle time reduction using balance control in the semiconductor fabrication line’, Production Planning and Control, 2002, vol. 13, no. 6, pp. 529-540.

[11] K. Oey & S. J. Mason, ‘Scheduling batch processing machines in complex job shops’, Proceedings of the 2001 Winter Simulation Conference, Piscataway, NJ 2001, pp. 1200-1207.

[12] R. M. Dabbas; H. N. Chen; J. W. Fowler, et al. ‘A combined dispatching criteria approach to scheduling semiconductor manufacturing systems’, Computers & Industrial Engineering, 2001, vol. 39, no. 3-4, pp. 307-324.

[13] R. M. Dabbas; J. W. Fowler; D. A. Rollier, etc., ‘Multiple response optimization using mixture-designed experiments and desirability functions in semiconductor scheduling,’ International Journal of Production Research, 2003, v 41, n 5, 20, pp 939-961

[14] R. M. Dabbas and J. W. Fowler, ‘A new scheduling approach using combined dispatching criteria in wafer fabs,’ IEEE Transactions on Semiconductor Manufacturing, 2003, v 16, n 3, pp 501-510

[15] P. Qu and S. J. Mason, ‘Metaheuristic scheduling of 300-mm lots containing multiple orders,’ IEEE Transactions on Semiconductor Manufacturing, v 18, n 4, Nov. 2005, pp 633-643

[16] H. H. Wu and M. L. Yeh, ‘A DBR scheduling method for manufacturing environments with bottleneck re-entrant flows,’ International Journal of Production Research, v 44, n 5, Mar 1, 2006, pp 883-902

[17] M. T. Zhang, ‘Advanced scheduling in WIP management for semiconductor manufacturing,’ Semiconductor Technology, v 29, n 1, 2004, pp 35-39

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