2005 IEEE International SOI Conference

Edge-Defined 90nm TFTs with Adjustable VT in a 3-D Compatible ProcessJawad Nasrullah,*t James B. Burr,t G. Leonard Tyler,* Yoshio Nishi**Dept. of Electrical Engineering, Stanford University, Stanford, CA 94305

Telephone: (650) 725-1638, Email:jawad@ieee.orgtTransmeta Corporation, 3990 Freedom Circle, Santa Clara, CA 95054

Introduction

Threshold voltage (VT) adjustability through back-gate bias(VB) facilitates power management in VLSI by providing amechanism for balancing leakage and switching energies [1].Dynamic threshold voltage control with back-gate bias hasbeen demonstrated in SOI [2]; it is especially important for3-D stacking where heat builds up [3]. We implement short-channel thin-film transistors (TFTs) in solid-phase crystallizedpolycrystalline silicon (poly-Si) with dynamically adjustableVT, in a 3-D compatible process. Aggressive scaling of devicefeatures is achieved via a low-temperature-compatible edge-defined patterning process [4]. Edge-defined lithography isattractive for 3-D integration, since it offers a very cost-effective solution for the multiple CD mask layers in stackeddevices. This work focuses on the processing technology thatachieves device VT adjustability in second and higher layersof short-channel stacked devices. The device mobility andadjusted subthreshold behavior reported here are, however,comparable to those in other TFT work [5].

Process and Device Details

Fig.1 shows key steps of edge-defined TFT fabrication. TheTFT's active area is built in a 50nm-thick deposited amor-phous silicon (a-Si) channel that is later crystallized usingrapid thermal annealing (RTA). An underlying-blanket, boron-doped Si film is used as a global back-gate electrode, separatedfrom the channel by a 50-nm thick deposited back-gate-oxidefilm. A blanket film of 12nm deposited oxide is used forfront-gate dielectric after active-area patterning. An in-situphosphorus-doped a-Si film is deposited and patterned into90nm-length gates, Fig.l(a). The device gates are fabricatedwith an edge-defined patterning process as detailed in Ref.[4]. First, a spacer is defined around a sacrificial registrationblock. The sacrificial block is then stripped away, leavingthe outline of the registration as a spacer. The spacer widthis defined by the spacer-film thickness, and controls thefinal gate length (Lg) by acting as the mask, Fig.l(b). Asecond pattern is superimposed at this stage with a patternedphotoresist, enabling fabrication of edge-defined and photo-defined features at the same level. The photoresist and spacerare then used to pattern gates of the transistors, as shown inFig. l(c). The TFT channels are undoped. Arsenic is implantedto create sources and drains, whereas the gates are depositedin-situ doped a-Si. After opening up contact holes, the devicesare subjected to a 900°C spike RTA to activate dopants andto convert the channel a-Si to poly-Si form. Contact metal isa 50nm titanium film followed by a 450nm aluminum film.Lastly, the devices are annealed at 350°C in forming gas foran hour.

0-7803-9212-4/05/$20.00 ©2005 IEEE

ResultsFig.2(a) is a micrograph of a typical device, comprised ofthree 90nm edge-defined front gates. These three gates aredefined by two edge-registration polygons. A gate contact padis superimposed, to make electrical connection to the gate.Fig.2(b) is a close-up of a 90nm gate stack fabricated usinga similar edge-defined patterning process. Note the roundedspacer mask on top of the patterned gate, and the sidewallvariations [4]. Fig.2(c) shows the device structural details.

Fig.3 shows the device performance adjustability of atypical single-gate device with the application of back-gatebias. Fig.3(a) presents the ID-VG family of curves for thisdevice with values of VB ranging from -6V to +6V. Forpoly-Si TFTs, the value of subthreshold slope is typically300-400mV/decade, which is higher than the ideal value of6OmV/decade. Fig.3(b) presents the ID-VG family of curvesfor this device at VD=1.5V. Comparison of Fig.3(a) withFig.3(b) shows that 'off is 2-3 orders of magnitude higherfor VD=1.5V. The dependence of the turn-off behavior on thedrain voltage results in a lower threshold voltage; hence IDincreases. Figs.3(c)-(f) show the behavior of four specific pa-rameters vs. VB, based on the device ID-VG curves for VD=0.3and 1.5V, described above. Fig.3(c) gives the change of VTwith VB. Fig.3(d) shows the change in subthreshold slope,SS, with VB. Subthreshold slope decreases with decreasingvalues of VB due to better front-gate control for lower valuesof VB. Fig.3(e) shows the change of the on-state current,lo, with VB for a fixed gate potential of 3.3V. On currentdecreases with decreasing values of VB due to increase in VT.For VD=1.5V, Io decreases more rapidly with reduction inVB than is the case where VD=0.3V. Fig.3(f) shows the offcurrent, 'off, change with VB for a fixed front-gate potentialof OV. Off current decreases due to decreasing values of VBand increasing VT.

Fig.4(a) shows the family of ID-VD curves with VB =5Vand OV for a Lg =9Onm device. These curves do not showsaturation of the drain current with increasing VD, suggestingcontrol of the channel conductivity by the drain similar tothat from the gate. We attribute this to series resistance,uncontrolled inward diffusion of dopant atoms from the sourceand the drain resulting in shorter electrical channel length, andthe formation of unwanted resistive current paths beyond thecontrol of the front-gate. In a quadruple-front-gate device, theID-VD curves look more saturated as seen in Fig.4(b); butits turn-off behavior is similar to that for a single-front-gatetransistor, Fig.4(c).

Fig.5 shows the back-gate bias behavior of device pa-rameters for -20°C, 60°C, and 110°C. Fig.5(a) shows VTchange with VB. Higher temperatures result in lower VT. Sub-threshold slope decreases with lower temperature, consistentwith traditional device behavior, Fig.5(b). Fig.5(c) shows Ion

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change with VB. On current decreases with lower values ofVB due to increasing VT. However, with higher temperatureIOn increases. Carrier mobility is already lower than c-Sidue to poly-Si grain boundaries in the channel; therefore thedegradation in mobility with temperature is not apparent inIon behavior as would be the case with c-Si channel devices.Instead, reduction in VT helps to increase I with hightemperature.

Fig.6 shows device performance variations with VB for foursimilar devices a few hundred microns apart. Fig.6(a) showsthe change in VT with VB; note that for devices A, B, and DVT can be shifted by approximately 70 mV/V of VB. Device C,however, has 300mV and lower threshold voltage as comparedto the other three devices. This indicates that devices A, B, andD have similar turn-on behavior, whereas device C is different.Figs.6(b)&(c) respectively show the variations in SS and Ionfor these four devices. The device variations are expected [6],and we observed them. These device performance variationscome from randomly oriented grain boundaries and enhanceddopant diffusion along grain boundaries. Since the TFT gatelength is comparable to the grain size, device variations are

pronounced due to less grain-effect averaging. The grain

boundaries perpendicular to the channel result in increased VTand lowered mobility, whereas the ones parallel to the channeldegrade subthreshold performance. The enhanced diffusionalong grain boundaries results in channel shortening, hencein increased on-current.

ConclusionsThin-film transistors of Lg =90nm with insulated back

gates, compatible with 3-D stacking, have shown VT adjusta-bility. Threshold voltages of these devices are adjustable byabout 1OOmV per volt of back-gate bias. Threshold-voltagevariations are observed in these devices, and are plausiblyattributed to poly-Si grain-boundary related charge traps andto channel-length shortening.

AcknowledgmentThe authors acknowledge helpful discussions with A.Matthews, J. McVittie, E. Perozziello, and V. Svilan.

References[I] V. Svilan et. al., in ISLPElD, pp. 268-272, Aug. 2000.[2] L. Y. Yang et. al., IEEE 7T Electron lDev., vol. 44, pp. 822-831, May 1997.[3] S. J. Souri et. al., in Proc. 37lh Con/: on lDesign Automation, 2000.[4] J. Nasrullah et. al., in IEEE Con!: on Nanotech., pp. 502-505, Aug. 2003.[5] R. Watts and J. Lee, Elect. l)ev. Lett., vol. 14, pp. 515-517, Nov. 1993.[6] P. Walker et. al., IEEE 1: Electron l1ev., vol. 51, pp. 212-219, Feb. 2004.

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