ISSCC97 I SESSION 8 I DATA CONVERTERS I PAPER FA 8.6

FA 8.6: A 1GSamplels 10b Full Nyquist Silicon Bipolar Track&Hold IC

Thorsten Baumheinrich', Bernd PregardieP, Ulrich Langmann'

'Ruhr-Universitat Bochum, Lehrstuhl fur Elektronische Bauelemente, Bochum, Germany 2 N ~ ~ with Rockwell Semiconductor Systems, Newport Beach, CA

Track-and-hold amplifiers (THA) are key components for high- speed and medium-resolution AD-converters for measurement, multimedia, and advanced digital signal processing systems. This THA architecture provides a substantial improvement in linearity. The THA chip incorporates only npn transistors and is fabricated in a 25GHz-fT silicon bipolar production technology with an effective emitter stripe width of 0.4pm. It offers 10b linearity over the full Nyquist band at lGSample/s. Compared to the 8b lGSample/s circuit that is the starting point for the development of the current IC, the THD is improved by more than lOdB while keeping the power dissipation at a similar level (490mW) [11. The improved THA architecture as shown in Figure 1 consists of the input preamplifier Al, the analog switches SA1, two metal-to-poly hold capacitors and an output buffer A2. Two compensation amplifiers A3 and A4 complement the circuit. Their output signals are controlled by the switches SA3 and SA4, respectively. Because of the benefits of lower power-dissipation, lower distortion, and higher analog bandwidth, a fully-differen- tial approach is chosen. To guarantee a maximum bandwidth, the THA employs an open-loop structure during track-mode, while a closed-loop operation helps improving its accuracy in hold-mode.

In the previous design, one of the limiting factors for the THD is the non-linear modulation of the collector currents in the input differential pair [l]. The nonlinear part of the Vbe-modulation of the input differential pair Ql,Q2 ofAl in Figure 2 is compensated by the base-emitter voltage of Q3 and Q4, the bias currents of which are counter-modulated by Q5, Q6. This results in improved linearity of the internal analog signal [2].

The analog switches SA, are switched emitter followers Qsl and Q,,, combined with the compensation capacitances C, , for the minimization of the hold-mode feed-through [3,41. Because the dynamic charge and discharge currents of the hold capacitances CHI, contribute to the distortion of the differential analog signal, C,, are only 300fF. This increases the analog bandwidth and results in decreased values of both settling and acquisition time.

The small hold capacitances require additional measures to keep the hold-mode signal undistorted. One measure, implemented in the output buffer A2, aims at minimizing the differential droop by making the base currents of the emitter-followers Q29 and Q30 equal (Figure 3). Circuit A2 consists of a compensating part that generates a signal proportional to the hold voltage and of a stabilizing part. By means of the coupling resistors R13,R14 the compensation signal modulates the bias currents of Q29,Q30 so the signal-dependent part of their base currents diminishes. The voltage gain of the compensation amplifier Q31, Q32 must be slightly higher than 1, so the resulting signal currents across R13, R14 provide the required equalization. Because of the remaining single-ended droop, the compensating part ofA2 tends to loose its bias point during long hold-times. To avoid this, the mean value of the single-ended hold voltages is generated by the stabilizing part and applied to point C in Figure 3.

Amplifier A3 in Figure 1 generates a replica of the analog input signal that is inversely switched onto the internal load resistors during the hold mode. In conjunction with the feed-forward

capacitors, C,,, this results in a clear reduction ofhold-mode feed- through that is critical because of the small hold capacitances. However, due to the phase delay between the signal generated by A1 and the compensation signal of&, this compensation is band- limited to about 6OOMHz. Simulations indicated that the net feed- through is more than 54dB below the analog input signal for frequencies up to 500MHz.

Another drawback resulting from the small hold capacitances is the distinct increase of the pedestal, caused by the voltage step that appears a t the internal load resistors during the transition from track to hold-mode. This step is due to the currents being switched to the load resistors during the transition. These cur- rents can be divided into a signal-independent part resulting from the switched emitter-followers and a signal dependent part evoked by the feed-through compensation signal of A3.

An effective method for minimizing the pedestal is the equaliza- tion of the single-ended voltage steps resulting in a differential step close to zero. This function is realized by the pedestal compensating circuit A4, that produces a static signal almost equal to the output signal of A3 during the track-to-hold transi- tion (Figures 1, 3). The output signals A3 and A4 are coupled to the internal load resistors R, a t the same time, causing a signifi- cantly-reduced pedestal. Simulations show a pedestal of i3mV remaining, due to the finite time that Qsl and QS2 need to change to a non-conducting state. During this time, the loop consisting of A4, S , and Al, SA, has a gain that is still not far below 1. Another limiting factor for compensation of the pedestal is the phase delay between the output signals of A3 and A4.

For measurement, two THAs including two clock-buffers and bandgap-references as well as an additional output buffer be- tween THAs are integrated on the same die. During measurment and simulation a sinusoidal clock of 600mVpp is used. The produced chip shown in Figure 7 is mounted in a test fixture. The tests are based on the resampling technique described in Refer- ences 1 and 4. Figure 4 shows the THD of the beat signal produced by the two THAs and the resulting effective number of bits (ENOB) as afunction ofthe input signalfrequency. Incase (a), the clock frequency is fixed to lGSample/s and in case (b), the test is under Nyquist conditions. The effective number of bits i s l 0 b up to the Nyquist frequency for lGSample/s. The spectrum of a 500.005MHz input signal sampled by the first and second THA at rates of 1G and 5OOMS/s respectively, is shownin Figure 5. Figure 6 demonstrates the operation of a single THA under Nyquist condition at this sampling rate. Table 1 summarizes THA perfor- mance.

The authors acknowledge both the fabrication of the experimen- tal T&H IC and the test support by Hewlett-Packard Company.

References:

[11 Pregardier, B., U. Langmann, W. J. Hillery, "A 1GSamplek 8b Silicon Bipolar Track & Hold IC," ISSCC Digest of Technical Papers, pp. 58-59, 1995.

[21 Miki, T., et al., "A 10-b 50 MS/s 500-mW AID Converter Using a Differential-Voltage Subconverter, " IEEE Journal of Solid-state Circuits, vol. 29, pp. 516-518, 1994.

[31 SH, " ISSCC Digest of Technical Papers, pp. 178-179, Feb., 1983.

[41 Vorenkamp, P., J. P. M. Verdaasdonk, "Fully Bipolar, 120MSls lob- Track-and-Hold Circuit, " IEEE Journal of Solid-state Circuits, vol. 27, pp. 988-992, 1992.

Blauschild, R. A., "A 8b 5011.9 Monolithic AID Converter with Internal

142 1997 IEEE International Solid-state Circuits Conference

ISSCC97 / February 7,1997 I Salon 7 I 1 1 :15 AM

l G S k sampling rate (a) -C undy Nyquist condl!ion (b) . +.

12b

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8b . ~ . ~ ........... . ~~ ........ , ........ ..... I ..... ~~ ........ L .................. ~. .......

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7b

Figure 1: THA architecture. Track mode switch position. Switches controlled by internal clock-buffer.

-74

-68

-62

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A3 Figure 2:

Figure 3:

THA schematic - Part 1.

THA schematic - Part 2.

Clock frequency lGSample/s Measured total harmonic distortion

Analog input Differential analog output across 50R lV,, Voltage swing of sinusoidal

clock signals 600mVpp Measured slew rate of Hold-to-track transition 4.2 kV/ps

over full Nyquist band up to 1GS/s -62dB 1VPP

!!e5 BA 20 3 l iz 13dEl V l d Hw 30 H! AF Att 20 U0 1 6 1 r ' v ( I f f

nrf l e v D ~ l l i l -73 69 db ['F S t p 3 000 kHz

Figure 5: Beat signal measured spectrum. fan~,og=500.005MHZ,fc,kL=1GSample/s, fa,=500MSample/s.

Figure 6 ,7 : See page 444. Measured hold pedestal - <8mV Droop rate (simulated) O.l25mV/ns for

Power consumption of 1 THA

Transistor count 103 Power supply -5.2V Size of 2 THA chip as in Figure 7 2.22~0.76"~ Size of 1 THA core without bond-pads 0.72xO.42mmZ

hold-intervals up to 4ns

excluding the output buffer 490mW

Table 1: Performance characteristics of the Track&Hold IC.

DIGEST OF TECHNICAL PAPERS 143

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FA 8.6: A 1GSamplels 10b Full Nyquist Silicon BipolarTrack&Hold IC (Continued from page 143)

Figure 6: Measured signals for f,,,,og+500MHz,fc,,=lGSample/s.

Figure 7: Chip comprising two T U .

FA 8.7: A 10b 250MHz BiCMOSTrack and Hold (Continued from page 145)

Figure 6 Chip micrograph.

444 1997 IEEE International Solid-State Circuits Conference