A 1024-Ph Plastic Ball Grid Array for Flip Chip Die

ABSTRACT

by Andy Switky and Vijay Sajja Aptix Corporation

2980 North First Street San Jose, CA 95134

Joel Damauer and Wayne Wei Ming Dai Computer Engineering Board of Studies University of California at Santa Cruz

MECHANICAL DES IGN

Described in this paper is a 1024-pin ball grid array package (BGA) that contains an area array die flip-chip mounted to a sili- con transposer. The transposer, which fans the area array to two rows of pads on its periphery, is wire bonded to a printed circuit board substrate. Mechanical and electrical design considerations of the BGA are discussed, as well as the results of SPICE models.

INTRODUCTION

Aptix currently sells a 1024-pin field programmable interconnect device (FPIC), the AX1024R. The FPIC die is flip-chip-mounted to a ceramic land grid array package (LGA), which is then housed in a molded plastic screw-mounted socket fitted with "fuzz button" contacts. The package's contacts are arranged in a 32x32 array on 40 mil pitch.

Although this system works well, it is relatively expensive. In an attempt to reduce costs, we designed a ball grid array package (BGA). BGAs combine LGA features with a flip-chip-style board interconnect. Like LGAs, BGAs have an array of contacts on their bottom surfaces, rather than more traditional peripheral surface mount pins. Like flip-chip, the contacts on the bottom of the package are solder balls, which connect to il circuit board through a C4-type (for controlled collapse chip connection) solder connec- tion.

There are several types of BGAs; the most common BGAs are plastic or ceramic. Although both plastic and ceramic BGAs are gaining acceptance rapidly, plastic BGAs, which are made from printed circuit board (PCR) technologies and materials, are pre- ferred over ceramic BGAs because of the PCB materials' lower costs, their compatibility with existing assembly equipment, and their thermal expansion coefficients (TCE) match mother-board TCE. Unfortunately, plastic BGAs do not lend themselves readily to direct die flip-chip attachment. To rectify this, we have devel- oped a silicon transposer to which the FPIC die is flip-chip- mounted. The transposer is wire-bonded to a plastic BGA sub- strate (see Figure 1).

This paper will discuss the criteria used to design the PCB sub- strate and the silicon transposer. We will also discuss the perform- ance of the transposer (which spreads the fine pitch of a flip-chip die to a wire-bondable pitch) and the substrate.

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Substrate

Ideally, we would attach our die to the PCB substrate as we cur- rently attach our die to a ceramic substrate: direct flip-chip. There are several factors preventing flip-chip attach directly to PCB sub- strates. First, routing inner bumps outside the die's bump array is not possible using standard processes. Assuming 12 mil bump pitch, 6 mil diameter pads, two mil PCB trace width, and 2 mil space between traces, only the outer row and one inner row can be routed out of the array. Routing other rows requires additional layers. To access lower layers, vias - either full through-holes or blind vias - must be drilled through the substrate. Since each layer can only route at most two rows, it would become impossible to plate the blind vias. One could, however, print, etch, and plate each of the layers and then sequentially laminate them as a final step. This approach is prohibitively expensive.

Second, a flip-chip bump must be placed on a pad, not a via. If the pad is offset from the via there will be less room for traces, further exacerbating the routing congestion. Several vendors claim they can plug vias successfully.

Lastly, cost, the reason we were looking at PCB substrates in the first place, became a serious consideration. Assuming, for a mo- ment, that it is possible to sequentially laminate the substrate or plug vias and use a controlled-depth drill to connect layers, the substrate would still be 10-16 layers. Prices quoted for such structures (which the vendors were not sure they could deliver) were higher than those of our current ceramic substrate.

Instead of direct flip-chip to a PCB substrate, we used a silicon transposer to fan out the 12 mil bump array to a wire-bondable perimeter. The limiting factor then becomes wire-bonding, rather than PCB manufacture. After discussions with wire bonder ven- dors, we settled on a staggered 6.8 mil pitch (3.4 mil effective). At this pitch the translator is 0.96" on a side.

One of the drawbacks of fine-pitch wirebonding is that all 1024 traces must be routed to vias on one layer; or, if there are two bonding levels, all traces must be routed on two layers. This is be- cause a pad on the substrate must be connected to a via, which then connects to a solder ball on the bottom of the BGA substrate. Routing congestion again becomes an issue.

Cavity packages provide an excellent answer to routing congestion problems. Cavity packages have a bonding floor (on the same level as the die attach area) and a bonding shelf. Unfortunately, a

0569-5503/94/0000-0032 $3.00 01994 JEEE

transposerkavity package does not allow full routing to the 1024- pin array on two routing levels. The pads on the bond shelf, for example, define a square 1.2" on a side. If roughly half of the transposer's bond pads are connected to the bonding shelf (the other half bond to the floor), the shelf must route over 500 signals. However, there are only two rows of the 32x32 array beyond the edge of the bonding shelf, or around 240 pins. The solution is to route the signals that cannot be routed directly to the 1024-pin ar- ray to auxiliary vias outside the 32x32 array (see Figure 2). On another layer these signals will be routed into the bump array. Thus, what used to be a 1024 array with 1024 vias becomes more like 1024 array (on the bottom there are still only 1024 solder balls) with 1250 vias.

We used aggressive - but realistic - design rules for the substrate traces. Under these design rules we allowed fmour escapes (traces that escape the P I C area) between vias. More escapes require finer geometries; fewer escapes and the substrate is unroutable. Assuming four traces between vias, we chose a trace pitch of 5.7 mils. That is, any combination of trace width and space between traces equal to 5.7 mils is acceptable. These dimensions are en- tirely dependent on the substrate vendor's ability to align the PCB layers and drill accurately, and not necessarily to the diameter of the drill bit he uses. The key is to reduce the diameter of the cover pad, the pad to which a trace terminates at a via. After working with our vendor, we managed to achieve 15.5 mil cover pad by using an 8 mil drill, 3 mil drill ac:curacy, and allowing 3.5 mil PCB layer misregistration.

Assembly of the BGA follows the procedures for standard packag- ing technologies. After the die is flip-chip-mounted to the trans- poser, the transposer is attached to the BGA using a low stress die attach film. Next, the transpose1 is wire-bonded to the substrate. The assembly can then be capped or "glob-topped." Balls are at- tached to the bottom of the substrate. The device can be tested or burned-in before or after ball-attach.

TtansDoser Selecting materials and designing the interconnect were more dif- ficult than reducing the transposer size. To complete the design we needed to specify the number of layers and line widths on the transposer. We also were interested in studying the impact of changes in materials used in the dielectric and conducting layers and the thickness of each, although in practice our control over the fabrication process was limited to aluminum interconnect and 5 micron polyimide.

Since the cost of a wafer increases monotonically with the number of processing steps and thus the number of signal planes, we began the transposer design with the goal of using a single signal layer. In addition to the signal layer, we were also )forced to use a solid power plane to lower the inductance of th'e power distribution net- work and to allow sites for decoupling capacitors. The degener- ately doped silicon substrate of the transposer was used as a ground plane. Confining the escape pattern beneath the FPIC to a single layer resulted in a maxinium line pitch of 23 microns at the perimeter of the bump array, resulting in highly resistive 13 mi- cron wires and possibly low yields. The akmative, however, was to add another signal layer, which would increase the transposer's cost. To counteract these problems, we decided to cut a hole in the power plane directly beneath the FPIC die xnd to use the area for routing wires. This approach allows wider wires, but the lack of a solid reference plane and the thin dielectric between wires on neighboring layers increases the crosstalk unacceptably unless an

X-Y routing pattern is used. Since the power and ground pins of the FPIC device are at the periphery of the FPIC die, the impact on power distribution is negligible. With this strategy, the line pitch became 28 microns, allowing wider 15 micron lines.

To alleviate the high-resistance of the traces, we considered a number of alternatives. The first was to taper the traces, from 15 microns in the high-density FPIC area to a maximum width of 60 microns at the bond pads. Although this reduces the line resis- tance, it also increases the capacitance, so the effect on perform- ance is not necessarily positive, but it comes at no additional cost. We also considered replacing the aluminum interconnect with copper, which has a lower sheet resistance but more processing expense. Finally, we considered increasing the thickness of the conducting layers beyond the 2.5 micron thickness available to us, but again that could only be done with non-standard procl-sses and increased cost. At this point we needed to see exactly how the line resistance was impacting the system performance.

ELECTRICAL CONSIDERATIONS

An ideal package provides ideal electrical connections and presents a stable and noise free power supply to the chip it enclosc:~. Real packages must contend with noise and performance degradation caused by less than ideal signal lines and impedances i n the power distribution network. For our package there were two overriding concerns. First, we had to determine the performance loss associ- ated with introducing resistive thin-film interconnections to the package and the sensitivity of performance to line width. Second, we needed to determine the correct number of power and ground connections at each package level to minimize the effects of simul- taneous switching noise. We will address these questions sepa- rately.

Electrical Performance

The translator's geometries, not the substrate's, drive the overall electrical performance of the package because of the relatively high resistance of the thin film interconnect (around 8 ohms per cm for 15 micron lines). Fortunately. the interconnections inside the FPIC device itself are fairly resistive, so the resistance of the thin film lines is still a small percentage of the overall resistance. We estimated the performance difference between the existing low-parasitic ceramic package and the proposed packaging alter- native by modeling the proposed package with SPICE.. We con- nected lumped element models of each of the levels irr the packag- ing hierarchy to on-chip circuitry and a hypothetical signal source and load. Conceptually, the circuit is represented by the block diagram shown in Figure 3. The board U 0 lines model the few inches of PCB trace between the package, source, and loacl and were added so that the metric of performance was the piopiagation delay, measured as the time switching threshold and the time this same crossing is observed at the load. We compared thc impact of tapering, the use of aluininum or copper, and the ust: of 15 micron versus 30 micron lines on performance.

The dominant delay in the system is the RC delay, whir h IS the time it takes to charge a load capacitance through a finite iesis- tance. This delay is roughly the product of the line resi\tance and the capacitance that it must drive. All other things \wing equal, re- ducing the resistance makes the signal delay decrea5r Widening

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the lines reduces their resistance at the cost of an increased capaci- tance. Whether this reduces or increases the system delay depends on the sensitivity of the delay to line resistance and source imped- ance and load. If, for example, the load capacitance is very large and the source impedance is small, the increase in capacitance on the lines will be negligible compared to the total capacitance, whereas the reduction in resistance might be large compared to the overall resistance. We estimated that the resistance of the typical 15 micron aluminum line would be about 12 ohms. Since the in- temal circuitry of the P I C has an effective DC resistance of about 100 ohms, we estimated that this would result in about a 10% in- crease in signal delay over the low resistance lines in the ceramic package. Calculations showed that using wider lines or introduc- ing taper would improve the performance.

For more robust data, we created approximate lumped-element models of the thin film lines, and analyzed the bump and bond parasitics. The use of lumped elements for the lossy transmission lines introduces some error, but this was deemed acceptable beca- use the transmission line delays are not particularly long relative to the typical edge rates. We simulated the models several times, varying the source impedance and load to reflect different envi- ronments. Our initial simulations showed that the thin film resis- tance added about 10% to the overall delay compared with the previous ceramic package under the most pessimistic assumptions for driver and load. Tapering the lines typically improved the de- lay by 3%, and since there was no cost in choosing tapered lines, we quickly adopted this option for the remainder of the simula- tions. Switching to copper interconnect would have reduced the delay even further, making it only a few percent slower than the original package. Since we did not have access to a fab with cop- per lines, however, we constrained the rest of our simulations to aluminum lines. We then simulated three packages: the original ceramic package; a BGA with silicon transposer using 15 micron wide aluminum lines in the FPIC region; and the same BGA using 30 micron wide lines to see the effect of adding another signal layer. Simulations were performed over a variety of operating conditions and assumptions. Figures 4 and 5 show typical results. These plots show the delay for each package type with a 15 ohm source driving a 15 pF load through the FPIC and 4 inches of PCB, with either a TTL-compatible buffer or no buffer on the sig- nal path inside the FPIC device. The effect of the line variation in this case is quite small, although the wider lines have a small ad- vantage. The new package adds about 10% to the propagation delay.

Noise -eous Switching Any system with a large number of UOs that might switch simul- taneously must contend the accompanying noise. Although we originally believed that this would not be a problem because the P I C has relatively little power-consuming logic, the low ratio of signal to powedground pins caused some concern. Unfortunately. the need to provide large numbers of power and ground connec- tions can be costly, as mentioned above.

. .

There are three planes of interest for each voltage reference: one on the plastic BGA, one on the transposer, and the power and ground grids on the FPIC itself. Each stage of this hierarchy is connected to the others by elements that have finite inductances. Each stage is also capacitively coupled to each of the signal lines. When the source switches, current flows into the FPIC to charge the line, producing transitory current and voltage fluctuation at each of the reference planes. These sniall fluctuations can itccu- mulate if sufficiently large numbers of devices switch, causing the reference planes to "bounce" away from valid logic levels, propa- gating false logic values to other parts of the system or causing re-

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ceivers to misread inputs. These effects can be minimized by the proper selection of decoupling capacitors and by adding parallel wire bonds or bumps to reduce the series induciance of the refer- ence planes. We decided to use 50 power and ground bonds to lower the inductance between the transposer and BGA to around 0.05 nH. Further improvement was not possible because the in- ductance of the BGA lands themselves begins to dominate the equations, and the number of these pins was fixed prior to the package design by pin compatibility requirements (see Figure 6).

We modeled the power networks of the BGA package and simu- lated simultaneous switching noise versus the number of switching buffers by extending the SPICE models used for the performance simulation. Figure 8 shows the relationship between the number of switching outputs and the amplitude of the noise on the FPIC's Vss network. The TTL noise margins are exceeded when more than 60 outputs switch simultaneously, though this may be conser- vative as not all of the noise pulse couples out of tht: FPIC device on quiet lines. Figure 7 shows the signal values of the reference planes for the case when 60 nets switch. lntegrity of the on-chip RAM is maintained throughout by decoupling capacitors on the transposer. We conclude that although simultaneous switching is a problem for high-I/O packages, our new approach does not intro- duce any new limitations.

CONCLUSIONS

1. A high-density plastic BGA package with a bump pitch of 40 mils is feasible. The laminate uses 5.7 mil trace pitch (3.2 mil line, 2.5 mil space), which is aggl-essivt:, but not ouiside the ca- pabilities of many PCB suppliers. 2. The package is about 10% slower than the equivalent ceramic package because of the increased resistance due to the aluminuni thin-film metallization of the transposer. However, with copper metallization, this difference would be negated. 3. It is arguable if this package is cheaper than an equivalent ce- ramic BGA package. In applications where the TCB mismatch and the package size are large, PCB/trmsposer technology is a way to implement the BGA solution.

Acknowledgement

The authors wish to acknowledge the support of King Tat of AT&T and Quaid Nasir of Aptix Corporation

References

[ l ] H B Bdkoglu, Circuits Packacing and Interconnection tor VL- 3 Addison Wesley Publishing ('0 , 1983 [2 ] Robert C. Frye. "Balancing Pc rformdnce arid Cort in CMOS- based Thin-film Multichip Modules," in Proceedingz ot the IEEE Multichip Module Conference, 1993, pp f ) - I 1

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Figure 1: Cross Section of Proposed Package

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/’ CORNER OF 32x32 ARRAY INSIDE THE ARRAY, VW ARE CONNECTED TO SOLDER BALLS ON BACK OF SUBSTRAIE

Figure 2: BGA Bonding Shelf With Auxiliary Vias

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Figure 6: Power Distribution

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Figure 8: Ground Bounce - Switching Outputs vs. FPIC Vss Noise 3a