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China 1991 International Conference on Circuits and Systems, June 1991, Shenzhen, China Circuit Tolerance Analysis and Yield Maximization Using SPICE with Parallel Processing Techniques Daniel K C Li Department of Computer Studies Lingnan College Richard M M Chen Department of Electronic Engineering City Polytechnic of Hong Kong Abstract: Most algorithms using analytical approach for tolerance analysis and yield maximization are based on certain assumptions which may not be true in practical design problems. Thus Monte Carlo analysis Is required to be carried out in order to give a more precise estimation of the yield. In this paper, the problem of nominal design and tolerance assignment is formulated as an optimization problem, in which many SPICE runs are required for the estimation of circuit product yields. Two levels of parallelism are identified. Transputers are chosen as the hardware platform for the implementation of the proposed parallel processing technique to speed up the computation. 1. Introduction SPICE (Simulation Program with Integrated Circuit Enphasis) i s a circuit simulation program, which i s widely used in the electronic design comtunity. SPICE i s very computationally intensive, especially in i t s usage of floating-point nunbers and matrix equation solutions. It can consune a large amount of CPU time and memory usage when it is applied to large circuits of more than a few hundred nodes. This i s especially time consuning task if SPICE is used for tolerance analysis and yield maximization. Therefore, application of parallel processing techniques to run SPICE becomes very valuable in order t o speed up the computation. The main objective of circuit tolerance analysis is to predict the effect on circuit performance caused by the statistical variation of circuit parameter values. Worst-case circuit tolerance analysis can be carried out by performing SPICE runs at every extreme parameter value provided that the circuit performance and component values obey certain conditions such as monotonicity. For a circuit with n such parameters, 2" SPICE runs will be required in general. There i s no guarantee that such a vertex analysis can always provide information on worst performance of the circuit. Monte Carlo analysis is usually more powerful and provides more information for tolerance analysis. However, the nunber of samples required for a given accuracy requirement may be so large that not only it i s expensive t o perform, but also it takes long time t o compute. Tolerance analysis is an open loop approach in the sense that it provides useful information for predicting yield given a set of tolerances. Assigning a tolerance set with the least component cost to achieve maximm yield i s a much challenging task, which will lead to the loop to be closed if it i s successful. Although many algorithms and tools have been found by experience to offer valuable design aids t1-31, Monte Carlo analysis is often needed to verify the yield of the design with the assigned tolerance. Running SPICE for Monte Carlo analysis can be arranged t o be performed concurrently. Furthermore, a nunber of tasks in SPICE can be carried out at different level using parallel processing, such as setting up of circuit equation matrix C41, finding circuit responses at a nunber of frequencies, and solving the circuit equation by partitioning techniques 15-81. INMOS transputer T800 i s especially relevant in connection with the above tasks, because of i t s floating point performance and the interface to large amount of external memory. The transputer was specially designed to allow many of them to be used to solve a single problem. 2. Problem Formulation The problem of circuit design associated with the determination of nominal design and component tqlerance assignment for cost minimization and yield minimization can be transformed into the following mathematical optimization problem: Find the values of two n-vectors, and 1, to minimize the cost function or where and was (2) vector representation of ci rcui t component value, vector representation of component tolerance value, fixed cost per circuit product, cost weighting constant associated with the ith component tolerance, weighting constant associated with the yield, estimated yield using Monte Carlo ana 1 ys i s, a positive integer. The cost function C,(x,t) defined in Eq. (1) The formulation is an unconstrained used by Singhal and Pinel C91. optimization problem. Many optimization algorithms can be employed for the solution. We propose the use of a multi-algorithm approach because the conputation of Y i s expensive and time consuning. During the i n i t i a l searching stage, a small nunber of samples are generated to estimate the yield. When the search i s close to an optimal solution, a much larger nunber of sanples should be employed so 0 1991 IEEE 761

[IEEE 1991 International Conference on Circuits and Systems - Shenzhen, China (16-17 June 1991)] 1991 International Conference on Circuits and Systems - Circuit tolerance analysis

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Page 1: [IEEE 1991 International Conference on Circuits and Systems - Shenzhen, China (16-17 June 1991)] 1991 International Conference on Circuits and Systems - Circuit tolerance analysis

China 1991 International Conference on Circuits and Systems, June 1991, Shenzhen, China

Circuit Tolerance Analysis and Yield Maximization Using SPICE with Parallel Processing Techniques

Daniel K C Li Department of Computer Studies

Lingnan College

Richard M M Chen Department o f Electronic Engineering

City Polytechnic of Hong Kong

Abstract: Most algorithms using analytical approach for tolerance analysis and yield maximization are based on certain assumptions which may not be true in practical design problems. Thus Monte Carlo analysis Is required to be carried out in order t o give a more precise estimation of the yield. In this paper, the problem of nominal design and tolerance assignment is formulated as an optimization problem, in which many SPICE runs are required for the estimation of circuit product yields. Two levels o f parallelism are identified. Transputers are chosen as the hardware platform for the implementation of the proposed parallel processing technique t o speed up the computation.

1. Introduction

SPICE (Simulation Program with Integrated C i rcu i t Enphasis) i s a c i r c u i t simulat ion program, which i s widely used i n the e lect ron ic design comtunity. SPICE i s very computationally intensive, especial ly i n i t s usage o f f loat ing-point nunbers and matrix equation solutions. I t can consune a large amount o f CPU time and memory usage when i t i s applied t o large c i r c u i t s of more than a few hundred nodes. This i s especial ly time consuning task i f SPICE i s used f o r tolerance analysis and y i e l d maximization. Therefore, appl icat ion of p a r a l l e l processing techniques t o run SPICE becomes very valuable in order t o speed up the computation.

The main objective of c i r c u i t tolerance analysis i s t o predic t the e f fec t on c i r c u i t performance caused by the s t a t i s t i c a l var ia t ion of c i r c u i t parameter values. Worst-case c i r c u i t tolerance analysis can be carr ied out by performing SPICE runs a t every extreme parameter value provided that the c i r c u i t performance and component values obey cer ta in conditions such as monotonicity. For a c i r c u i t with n such parameters, 2" SPICE runs w i l l be required in general. There i s no guarantee that such a vertex analysis can always provide information on worst performance of the c i r c u i t . Monte Carlo analysis i s usually more powerful and provides more information f o r tolerance analysis. However, the nunber o f samples required f o r a given accuracy requirement may be so large that not only i t i s expensive t o perform, but also i t takes long time t o compute.

Tolerance analysis i s an open loop approach i n the sense that i t provides useful information f o r predic t ing y i e l d given a set o f tolerances. Assigning a tolerance set with the least component cost t o achieve maximm y i e l d i s a much challenging task, which w i l l lead t o the loop t o be closed i f i t i s successful. Although many algorithms and too ls have been found by experience t o o f f e r valuable design aids t1-31, Monte Carlo analysis i s o f ten needed t o v e r i f y the y i e l d of the design with the assigned tolerance.

Running SPICE f o r Monte Carlo analysis can be

arranged t o be performed concurrently. Furthermore, a nunber of tasks in SPICE can be carr ied out a t d i f fe ren t leve l using p a r a l l e l processing, such as se t t ing up of c i r c u i t equation matrix C41, f ind ing c i r c u i t responses a t a nunber of frequencies, and solving the c i r c u i t equation by p a r t i t i o n i n g techniques 15-81.

INMOS transputer T800 i s especial ly relevant in connection with the above tasks, because of i t s f loa t ing point performance and the in ter face t o large amount o f external memory. The transputer was specia l ly designed t o al low many of them t o be used t o solve a s ing le problem.

2. Problem Formulation

The problem of c i r c u i t design associated with the determination of nominal design and component tqlerance assignment f o r cost minimization and y i e l d minimization can be transformed i n t o the fol lowing mathematical optimization problem:

Find the values of two n-vectors, and 1, t o minimize the cost funct ion

or

where

and

was

(2)

vector representation of c i r cu i t component value, vector representation of component tolerance value, f i xed cost per c i r c u i t product, cost weighting constant associated with the ith component tolerance, weighting constant associated with the yield, estimated y i e l d using Monte Carlo ana 1 ys i s,

a pos i t i ve integer.

The cost funct ion C,(x,t) defined i n Eq. (1)

The formulation i s an unconstrained

used by Singhal and Pinel C91.

optimization problem. Many optimization algorithms can be employed f o r the solut ion. We propose the use of a mul t i -a lgor i thm approach because the conputation of Y i s expensive and time consuning. During the i n i t i a l searching stage, a small nunber of samples are generated t o estimate the y ie ld . When the search i s close t o an optimal solution, a much larger nunber of sanples should be employed so

0 1991 IEEE 761

Page 2: [IEEE 1991 International Conference on Circuits and Systems - Shenzhen, China (16-17 June 1991)] 1991 International Conference on Circuits and Systems - Circuit tolerance analysis

tha t the estimated y i e l d i s f a i r l y accurate. Thus, the Nelder-Head Sinplex algori thm 1101 i s selected fo r the optimization during the i n i t i a l stage of the optimization process, and switch t o a gradient based optimization algori thm 1111 during the f i n a l stage o f search.

The choice of the Nelder-Mead Sinplex algori thm i s based on i t s three strengths: i t s tolerance of f m c t i o n noise, i t s non-reliance on MY gradient approximations, and the extreme s imp l i c i t y o f i t s inplanentation. By switching t o a gradient based algorithm, the e f fec t of the weaknesses o f the Simplex algori thm i s being reduced.

I t i s noted that the whole optimization process may take hours or days t o run on a current model of personal conputer even f o r a re la t i ve simple c i r c u i t i f we do not r e l y on para l l e l processing techniques or some analyt ical fo r ru la t ions f o r the estimation of y ie lds and y i e l d gradients.

3. Transputer Implementatkm of The A d i c a t i o n

3.1 Parallel Fortran

SPICE i s recreated using INMOS 3L pa ra l l e l Fortran ccnpi ler I121 and running on a PC/386 microconputer. The iserver task i s an appl icat ion program that r m s on the host. I t loads executable f i l e s onto the transputer and also acts as a f i l e server, handling I / O rcqwsts made by the transputer. The iserver and the transputer execute i n pa ra l l e l and c-icate v ia an INMOS l ink .

A conf igurat ion f i l e Aust be created t o describe the system t o be built. The f i l e l i s t s a l l the physical processors i n the system, the wires connecting them, the tasks t o be loaded i n t o the system and the i r log ica l interconnections.

A Mult i- transputer program i s built in two stages. First , each indiv idual task i s compiled, l inked end converted i n t o an executable image. Second, the configurer i s used t o create the f i n a l program. The configurer w i l l automatically generate a l l the bootstrap and loader software required t o make sure tha t a l l the tasks are loaded i n t o the speci f ied transputer when the complete appl icat ion i s started on the root transputer by the iserver.

This compiler also provides the processors with a farming technique t o create appl icat ions which w i l l automatical ly configure themselves t o run on any network of transputers.

3.2 Farming Technique

The appl icat ion p r inc ip le of the farming technique 1131 i s that the same appl icat ion has t o be run many times, each with d i f f e ren t sets of input data, and where the outputs can be stored independently. I t i s possible t o operate a farm of farms, whereby an appl icat ion i s farmed, but each appl icat ion consists o f a farm of worker sub-tasks. Therefore, i t i s very sui table fo r our appl icat ion as shown in Figure 1.

The inplementation s ta r t s wi th a ported appl icat ion tha t has been decomposed i n t o a nunber of modules a t d i f f e ren t levels. A t the 1st level the SPICE program (Module S) i s farmed and a t the 2nd level the AC analysis task (Module AC) w i th in SPICE w i l l be farmed. Between the non-farmed part of the appl icat ion and the farmed module, there i s a farm control module, FC, which i s wr i t ten in OCCAM. The farm cont ro l le r divides the t o t a l task i n to a nunber o f sub-tasks, and in jec ts these sub- tasks i n t o the farm using the Routers R. Module AC and S are repl icated in the farm, completely without change. Addit ional ly, the farm cont ro l le r FC ensures that results, which w i l l be returned in a non-deterministic order v ia Mergers M, are sui tably returned t o the rest of the application.

4. Numerical Example

The formulation described i n Section 2 has been implemented in Fortran on a PC/386 microcanputer with a IMS BOO8 (which i s a Transputer Module motherboard) 1141 plugged in. The SPICE program i s ca l led as a subroutine t o estimate the attenuation (a) of the f i l t e r f o r d i f f e ren t sets of input parameter. The sample c i r c u i t we choose t o tes t i s a f i f t h -o rde r high pass f i l t e r 191 as shown i n Figure 2. The complete speci f icat ions fo r the f i l t e r are shown in Figure 3. The reference frequency i s WO Hz and 5 other frequencies a t 170, 350, 440, 630 and 650 Hz are used.

Root TrE.nrput.1 waneputer 1 1 1

R - Router U - Merger FC - Farm control module

~~

Figure 1: Farming part of the application.

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Page 3: [IEEE 1991 International Conference on Circuits and Systems - Shenzhen, China (16-17 June 1991)] 1991 International Conference on Circuits and Systems - Circuit tolerance analysis

Figure2: Circu i t diagram of high pass f i l t e r .

I

Yie ld v e r i f i c a t i o n based on 300 samples

The random var ia t ions of conponents are a s s 4 t o be independently uniformly d is t r ibu ted except that the res is tors modeling inductor losses are taken as conpletely correlated with the inductors. Two optimization runs were performed using Eqs. (1) and (2) seperately. The fol lowing constants were used:

U, = 1 f o r i = l t o 5

y = 2 f o r i=6 and 7

wg = 1000

p = 2 and

Both runs achieved the same resu l t of y i e l d (89.3%) and cost (3.72) defined by Eq. (1). However, the optimization process using Eq. (2) converges much faster than Eq. (1). 300-sample Monte Carlo analyses were used during the f i n a l stage of the optimization runs. The d e t a i l resu l ts are shown i n Table 1.

I

89.3

Cost estimate using Eq. (1)

1 1

i 3

i Y

, - 0

3.72

Figure 3: Response and speci f icat ion of high pass f i l t e r .

run the SPICE in the program i s

where

I,, - nunber of time the SPICE i s ca l led

T,, - computation time of each SPICE run

A n estimate of the t o t a l computation time 181 required t o run the SPICE in the program, using N,, farm worker processors, i s given as

where

ZN,,T- - the overhead associated with the s e r i a l l i n k s between successive transputers i n the processor farm (assune the worse case that a l l the input and output packets t rave l the f u l l length of the farm).

NI, - nunber of transputers used i n the farm

The processor t o processor communication time,

( 5 )

T-, i s given by

1- = Nbyfw / Linkspeed

where

N,,, - average Size of the input and output package

Linkspeed - 1 M bytes/sec

Using Eqs. (3) and (41, the speed up factor associated with NI,-processor farm i s then

Table 1: Optimization resu l t o f the example.

The appl icat ion of optimization techniques and Monte Carlo analyses require t o run SPICE thousands of times. Implementation o f Para l le l Processing technique w i l l reduce the overa l l computation time s ign i f icant ly .

A t the f i r s t level, the farm technique i s applied t o the SPICE f o r Monte Carlo analyses.

The t o t a l time used f o r s ing le processor t o

For the sample f i l t e r c i r c u i t , the input package s ize i s 319 bytes and output package s ize i s 3.7 Kbytes, so the N,,, i s 2 Kbytes and the 2NtpTm i s very small conpared wi th the Tmp (about 5 sec.). Therefore, the speed up factor i s almost the same as the nunber of transputers that we used.

763

Page 4: [IEEE 1991 International Conference on Circuits and Systems - Shenzhen, China (16-17 June 1991)] 1991 International Conference on Circuits and Systems - Circuit tolerance analysis

A t the second level, farm technique w i l l be applied t o the AC analysis subroutine in the SPICE program. I n the f i l t e r exanple, c i r c u i t solut ions w i l l be evaluated a t the speci f ied frequencies f o r each SPICE run. Therefore, the speed can s t i l l be inproved a l o t i f ue have enough transputers.

5. Discussion

During the i n i t i a l stage of the optimization process, i t i s not necessary t o have accurate estimation of yields. Therefore, there i s no need t o use large nunber of samples in Monte Carlo analyses, or a s imp l i f ied y i e l d estimation formulation may be enployed t o replace Monte Carlo ana 1 ys i s.

During the f i n a l stage of the optimization process, searching of the optimun so lut ion w i l l be i n the v i c i n i t y o f the region of acceptabi l i ty RA as shown i n Figure 4, i n which, R, and R', are the regions of tolerance. As repeated SPICE runs can be avoided for these overlapped region of R, and R',, t o t a l nunkr of SPICE runs can be great ly reduced. I t i s necessary t o establ ish a database t o s tore the computed resul ts i n the neighborhood of RA and therefore there i s no need t o re-run SPICE a t the sane points already computed. Furthermore, regression techniques can be employed t o use the database f o r estimation of yields.

Figure 4: Graphical i l l u s t r a t i o n o f RA and R,.

6. Acknowledament

The authors would l i k e t o thank Dr . Andrew M. Layf ie ld f o r h i s valuable information on transputer re la ted subjects and t o Mr. Andreu C. K. Cheung f o r h i s assistance in the preparation of the f i n a l version of t h i s paper. The second author i s gratefu l t o the City Polytechnic of Hong Kong f o r providing the funds and f a c i l i t i e s f o r t h i s research pro ject .

7. References

111 R. Spence and R. S. Soin, Tolerance Design of Electronic Circuits. Addison-Uesley, 1988.

I21 U. Maly, ITonputer-Aided Design f o r VLSI C i r c u i t Manufacturability,18 Proc. IEEE, Vol. 78, No. 2, pp. 356-392, Feb. 1990.

131 R. M. M. Chen and Y. M. Lai, "An E f f i c i e n t Algorithm f o r Optimm A s s i g m n t of C i rcu i t Conponen t Tolerances,Il Proc. China 1991 In ternat ional Conference on C i rcu i ts and

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A. Hamilton and C. Dyson, IIPorting SPICE t o the INMOS IMS T800 Transputer," INMOS Technical Note 52 (INMOS Corp., P 0 Box 16000, Colorado Springs, Co., USA), Sept. 1988.

G. Kron, Diakoptics - The Piecewise Solutions of Larqe-Scale Systems, London, MacDonald, 1963.

G. D. Hachtel and A. L. Sangiovanni- Vincentel l i , "A Survey of Third-Generation Simulation Techniques," Proc. IEEE, Vol. 69, NO. 10, pp. 1264-1280, Oct. 1981.

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R. M. M. Chen, U. C. Siu and A. M. Layfield, 08Running SPICE i n Parallel,18 Proc. 1991 Internationat Symposiun on C i rcu i ts and Systems, Singapore, June 1991.

K. Singhal and J. F. Pinel, "S ta t i s t i ca l Design Centering and Tolerancing Using Parametric Sampling,'a IEEE Trans. C i rcu i ts and Systems, Vol. CAS-28, No. 7, pp. 692-702, July 1981.

Cl01 J. A. Nelder and R. Mead, "A Simplex Method f o r Function Minimization,@I Computer Journal, Vol. 7. pp. 308-313, Jan. 1965.

1111 J. E. Dennis Jr. and R. B. Schnabel, "A View i f Unconstrained Optimization," in: G. L. Nemhauser, A. H. G. Rinnooy Kan and M . J. T o d d (eds.), Handbooks i n Owrat ion Research and Management Science, Vol. 1 Optimization, Elsevier Science, North-Holiand, 1989.

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