IEEE 1588 Hardware Assist - NXP

TM

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007-2008.

IEEE® 1588 Hardware AssistSession ID: AZ317

Freescale Technology Forum, June 2007

Satoshi IidaApplications Engineering Manager

TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007-2008. 1

Agenda

► IEEE® 1588• Protocol Overview• Synchronization Overview • Why Create Another Protocol?• Target Applications

►Hardware Assist• Synchronization Using Hardware Assist• Software-Only vs. Hardware Assisted Implementations• Hardware Assist in PowerQUICC ® II Pro Family devices

►Expansion into Network Applications• Synchronization vs. Syntonization• Synchronizing Across a Network• Boundary Clocks and Transparent Clocks

►Proposed IEEE 1588 Rev 2.0 Changes►Conclusion


IEEE® 1588 Overview

► IEEE 1588 – Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems

• The standard defines a Precision Time Protocol (PTP) designed to synchronize real-time clocks in a distributed system

• Intended for local area networks using multicast communications (including Ethernet)• IEEE 1588 was designed to work within a building or factory

Intended typically for industrial automation and test and measurement systems (e.g. synchronized printing presses)

• Targeted accuracy of microsecond to sub-microsecond with easy configuration and fast convergence between components

• Approved on September 2002 and published on November 2002Available from the IEEE 1588™ web site (http://ieee1588.nist.gov)

Node A:Time =

9:04

NETWORK

Node B:Time =

9:29

Node C:Time =

9:28

Node A:Time =

9:04

Node B:Time =

9:04

Node C:Time =

9:04

NETWORK


IEEE® 1588 Synchronization Overview

►Networked clocks organized in master-slave hierarchy

►Two-way time exchange between master and slaves

• “Master” clock sends messages to “Slave” clocks to initiate synchronization process

• Each “Slave” responds by synchronizing itself to corresponding “Master”

►This sequence is repeated throughout the network

► IEEE 1588 Message Types exchanged between Master and Slave:

• Sync• Delay_Req• Follow_Up• Delay_Resp• Management


IEEE® 1588 Synchronization Overview (Message Sequence)

PTP Appl.Master Clock

G/MII G/MIISlave Clock

PTP Appl.

t0

t3

t2

t1

Estimated Send Time (100)

Precise Send Time (101)

Precise Receive Time (106)

SYNC(100??)

FOLLOW_UP(101!)

Precise Send Time (111)

DELAY_REQ

DELAY_RESP(108)

Precise Receive Time (108)

100

Offset Computation

102

110

104

106

108

112

104

106

114

108

110

112

116

A

B

Key Equations:► A = t1 – t0 = Delay + Offset► B = t3 - t2 = Delay – Offset► Delay = (A+B) / 2► Offset = (A-B) / 2

Example:► A = 106 – 101 = 5► B = 108 – 111 = -3► Delay = (5-3) / 2 = 1► Offset = (5+3) / 2 = 4

UDP port 319: Sync and Delay_Req

UDP port 320: Follow_up, Delay_Resp, and Mgmt


IEEE® 1588: Why Create Another Protocol?

►Many protocols distribute time and synchronize network elements• Most use moderate compute resources

NTP Network Time Protocol, RFC 1305– Less accurate (milliseconds) and longer synch time (minutes to

hours)GPS Satellite based Global Positioning SystemTTP www.ttpforum.orgSERCOS IEC 61491

• IEEE 1588 differentiates for target marketsSmall compute and network footprint (<1% CPU utilization)Highest accuracy (<1 microsecond)Fast network synch resolution time (<1 minute)Easy configuration and operation by non-expert usersLow cost

http://www.ttpforum.org/

TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007-2008.

IEEE® 1588 Target Applications


IEEE® 1588 in Industrial Control

Servo Drive

Servo Drive

Servo Drive

Switch

E

E

E

Master Time

Motion Controller

ControllerEEthernet

AdapterServo Drive

Servo Drive

Servo Drive

Switch

E

E

E

Master Time

Motion Controller

ControllerEEthernet

Adapter

Motion Controller

ControllerControllerEEthernet

Adapter

Peer Controlling Other Peers

Distributed Control

SwitchMaster Time

Servo DriveE

Motion Controller

ControllerEEthernet

Adapter

Servo DriveE

Motion Controller

ControllerEEthernet

Adapter

Servo DriveE

Motion Controller

ControllerEEthernet

Adapter

SwitchMaster Time

Servo DriveE

Motion Controller

ControllerEEthernet

Adapter

Servo DriveE

Motion Controller

ControllerEEthernet

Adapter

Motion Controller


Adapter

Servo DriveE

Motion Controller

ControllerEEthernet

Adapter

Servo DriveE

Motion Controller

ControllerEEthernet

Adapter

Motion Controller


Adapter

Servo DriveE

Motion Controller

ControllerEEthernet

Adapter

Servo DriveE

Motion Controller

ControllerEEthernet

Adapter

Motion Controller


Adapter

►Issues due to mismatched cable lengths are minimized

►Servos can be added or deleted without having to rewire other servos

►Industrial Control applications typically augment IEEE 1588 hardware to provide trigger inputs and outputs


IEEE® 1588 in Test and MeasurementRemote Test

Controller

Pattern Generator

Test Board

Oscilloscope

Spectrum Analyzer

Logic Analyzer

Ethernet Network

Trigger In

Test Point

Trigger Out

►IEEE 1588 allows coordination and control of Test and Measurement equipment over a distributed Ethernet network

►Precise timing delivery allows test equipment to deliver patterns and measure responses at specific times

Enables accurate time stamping of measured dataAllows coordination of input stimuli and any associated measured data

►Trigger inputs and outputs enable coordination of other devices


IEEE® 1588 in a Wireless Network

* With proper changes to the current standard

RNC

Primary Time Server

Secondary Time Server

1588GrandMaster

1588GrandMaster

Precision Time Source

GPS

Precision Time Source

GPS

1588 Slave Clock

BaseStation

EBase

Station

EBase

Station

EBase

Station

E

Packet Based Radio Access

Network


Hardware Assist


What is Hardware Assist?

►An hardware that generates timestamps at the physical level of the protocol stack


Synchronization at Application Layer –Assisted by Hardware at Physical Layer

Master Clock Slave Clock

PacketNetwork

L5

L4

L3

L2

L1

L5

L4

L3

L2

L1

APPL:OTH.

Insert Timestamps into packet

header

Extract Timestamps from

packet header

Reconstruct clock from extracted

timestamps and packet arrival

times

Apply filtering and smoothing as

necessary

TCP/UDP

IP

MAC

PHY

APPL:SYNC

APPL:OTH.

TCP/UDP

IP

MAC

PHY

APPL:SYNC

Timestamp generation /

message detection

Timestamp generation /

message detection

Milliseconds of delay and

variation introduced

by protocol stack


Software-only vs. Hardware Assisted Implementations

►Software-only Implementations• Timestamps are generated at the application level• Microsecond range synchronization is possible

►Hardware Assisted Implementations• Timestamps are generated at the physical level • Nanosecond range synchronization is possible


Hardware Assist in PowerQUICC® II Pro Family Devices

►Freescale currently has IEEE® 1588 drivers available for MPC8349E and MPC8360E

►PowerQUICC II Pro Families supporting 1588 with Hardware Assist• MPC8360E (includes MPC8358E)• MPC8313E


Expansion into Network Applications


Expansion into Network Applications

►Benefits:• Eliminates need for extra equipment

i.e. GPS receivers• 1588 provides greater accuracy• Time to synchronize

►Concerns:• Synchronization Algorithm Factors

Delay can be added by repeaters, switches, routers, and network topologiesBoundary clocks and transparent switches (Version 2.0 only) can also help overcome this added delay


Clock Signal Relationships:Synchronization vs. Syntonization

► Synchronization• Clocks are characterized by :

Same Time of DaySame Frequency

– Frequency is locked– Each clock has the same definition

of a time unit (e.g., a second)Same Phase

– Phase is Locked

► Syntonization• Clocks are characterized by:

Same Frequency – Frequency is locked– Each clock has the same definition

of a time unit (e.g., a second)Phase offset is constant but unbounded

– Time of Day may be different

Note variation between signals within small specified limits (jitter)

1 UI 2 UI

Clock 1

Clock 2

Recovered Clock

Source Clock

1 UI 2 UI

Note variation between signals within small specified limits (jitter)

1 UI 2 UI

Clock 1

Clock 2

Recovered Clock

Source Clock

1 UI 2 UI1 UI 2 UI

Note constant but uncontrolled time/phase relationship between signals

Clock 1

Clock 2

Recovered Clock

Source Clock

1 UI 2 UI

1 UI 2 UI

Note constant but uncontrolled time/phase relationship between signals

Clock 1

Clock 2

Recovered Clock

Source Clock

1 UI 2 UI1 UI 2 UI

1 UI 2 UI


IEEE® 1588 : Synchronizing a Pair of Clocks Across a Network (General Method)

Master Clock

Slave Clock PTP Software

PTP Software

Not in SYNC

Local Counter

Local Counter

X 0 X 0 0 X X X 0

0 0 X 0 X 0 X 0 X



Master Clock


PTP Software

SYNC

Local Counter

Local Counter

2 8 3 1 5 2 7 3 0

2 8 3 1 3 0 0 0 0

2 8 3 1 5 9 3 3 0

X 0 X 0 0 X X X 0

0 0 X 0 X 0 X 0 X



Master Clock


PTP Software

SYNC

Local Counter

Local Counter

2 8 3 1 5 2 7 3 0

2 8 3 1 3 0 0 0 0

2 8 3 1 5 9 3 3 0

Clock Phase/Freq. Compare

X 0 X 0 0 X X X 0

0 0 X 0 X 0 X 0 X



Master Clock


PTP Software

SYNC

Local Counter

Local Counter

2 8 3 1 5 2 7 3 0

2 8 3 1 3 0 0 0 0

2 8 3 1 5 9 3 3 0


Clock Phase Adjust

X 0 X 0 0 X X X 0

0 0 X 0 X 0 X 0 X



Master Clock


PTP Software

SYNC

Local Counter

Local Counter

2 8 3 1 5 2 7 3 0

2 8 3 1 3 0 0 0 0

2 8 3 1 5 9 3 3 0


Clock Phase Adjust

X 0 X 0 0 X X X 0

0 0 X 0 X 0 X 0 X


Addressing the Variable Network Delay Problem

PTP

UDP

IP

MAC

PHY

Master Clock

PTP

UDP

IP

MAC

PHY

Slave Clock

Variable delay introduced by Network due to topology:

•Hundreds of nanoseconds to sub-microseconds for repeaters & switches

•Milliseconds for routers

Network

Impact of variable network delay minimized by using Boundary clocks


PTP

UDP

IP

MAC

PHY

(Slave)

PTP

UDP

IP

MAC

PHY

(Master)

Switch / Router with Boundary Clock

Boundary Clock

PTP

UDP

IP

MAC

PHY

Master Clock

PTP

UDP

IP

MAC

PHY

Slave Clock

Network 1

Boundary Clocks provide the ability to synchronize clocks across multiple networks/subnets by serving as a slave at one port and a master on all other ports

Network 2


Notes on Boundary Clocks

► Boundary clocks define a parent-child hierarchy of master-slave clocks

► Boundary clocks do NOT pass SYNC, FOLLOW_UP, DELAY_REQ, or DELAY_RESP messages

• Boundary clocks segment the network in terms of IEEE® 1588synchronization

► Within a subnet, a boundary clock port acts just like an ordinary clock with respect to synchronization

• Each port terminates PTP as a master or a slave

► The boundary clock port that is receiving the “master” clock becomes the single slave port. All other ports of the boundary clock internally synchronize to this slave port, and become masters for their respective subnets

PTP

UDP

IP

MAC

PHY

(Slave)

PTP

UDP

IP

MAC

PHY

(Master)

Switch / Router with Boundary Clock


MAC

PHY

MAC

PHY

Switch with Transparent Clock

Transparent Clock

PTP

UDP

IP

MAC

PHY

Master Clock

PTP

UDP

IP

MAC

PHY

Slave Clock

Network 1

Transparent Clocks syntonize to the Master Clock (i.e., have the same definition of a second), but do not synchronize to the Master Clock

Network 2

SwitchingFunction

TimeCorrection


Proposed IEEE® 1588 Rev 2.0 Changes


***PROPOSED*** IEEE® 1588 Rev 2.0 Changes/Clarifications

► Calls for SHA-1/2 authentication of PTP messages

• Critical for Telecom and other applications where messaging takes place over public networks

► Support for faster SYNC message rates (up to 1000 per second)

• Critical for Telecom, Residential Ethernet, and many control applications

► Support for PTP transport directly over Ethernet (via an Ethertype designation)

• Needed in applications where timestamping is required without using UDP transport – typically control applications

► Support for Clocking Redundancy• Critical for Telecom and many control

application

► Support for shorter PTP messages, unicastmessaging, as well as new messages (delay request) and message fields

• Critical for control, telecom, and Residential Ethernet applications where bandwidth allocated for this function is limited

► Support for phase-aligned output PPS• Requirement for some applications

where PPS output demonstrates synchronization

► Support for sub-nanosecond accuracy• Critical for all high accuracy applications

► Support for Transparent Clocks• Used in Residential Ethernet (and

possibly Telecom) applications, these correct timestamps, sometimes on the fly


Conclusion

►Freescale supports software-based IEEE® 1588 (PTP) implementations on both current and future PowerQUICC devices

► IEEE 1588™ Hardware Assist features are available on both current and Future PowerQUICC devices

• Both eTSEC- based products and products built on QUICC Engine™ technology

QE: 836x and future QE-based deviceseTSEC: 831x, 837x, and future eTSEC-based devices

• Intended to address industrial automation, test, and other applications• Implementation allows for multiple clock options, flexible support for

PTP frame detection, and rich set of external signal interfaces

TM

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007-2008.

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IEEE 1588 Hardware Assist - NXP