IE1204 Digital Design L10: State Machines (Part 2) · 2015. 9. 29. · state machines 1. Analyze the specification of the circuit 2. Create state diagrams 3. Set up the state table

IE1204 Digital Design

L10: State Machines(Part 2)

Masoumeh (Azin) Ebrahimi ([email protected])

Elena Dubrova ([email protected])KTH / ICT / ES

• BV pp. 528-532, 557-567

This lecture

IE1204 Digital Design, Autumn2015 2

Sequential System

a (t)

f (a (t))

Lecture 8 - Lecture 13

A sequential system has a built-in memory - the outputdepends therefore BOTH on the current and previousvalue(s) of the input signal


Basic method for the design ofstate machines

1. Analyze the specification of the circuit2. Create state diagrams3. Set up the state table4. Minimize state table (this lecture)5. Assign codes for states6. Choose the type of flip-flops7. Realize the circuit using Karnaugh maps


• In a Moore-type machine output signalsdepend only on the current state

Moore Machine

NEXT STATEDECODER

STATE REGISTER OUTPUTDECODER

State

Clk

Inputsignals

Outputsignals


Input vs. output - Moore

In1 In2

O1 O2

The input sequence

The output sequence

State changed here (at clock edge)

Output visible after the state has changed


• In a Mealy machine, output signals dependon both the current state and inputs

Mealy-type machine

NEXT STATEDECODER

STATE REGISTER OUTPUTDECODER

State

Clk

Inputsignals

Outputsignals


Input vs. output - Mealy

In1 In2

O1 O2

The input sequence

The output sequence

State changed here (at clock edge)

Output appears directly after the input has changed


Unused state

• Sometimes you get more states when you needwhen selecting a code

• ”Unused” states must be taken care of so that thestate machine does not hangs at the start-up (if resetis not used)

C z 1=¤

Reset

B z 0=¤A z 0=¤w 0=

w 1=

w 1=

w 0=

w 0= w 1=

State

The state transition

State identifier

Value of output signal

Present Next state

state w = 0 w = 1 Output

y2y1 Y2Y1 Y2Y1z

A 00 00 01 0B 01 00 10 0C 10 00 10 1

11 dd dd dUnused State


Example: (0,0,1) sequencegenerator

S0 | 0

S1 | 0

S2 | 1

S3 | -

If the machine falls inthis position, we wantit to find move toanother state as soonas possible

3 states => 2 flip-flops. One unused state.

Dangeroustransition(Machine hangs)


Next-state function

Currentstate

Outputsignal

Next state

y2y1 z Y2Y1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 - - - (not 11)

S0S1S2

S0 | 0

S1 | 0

S2 | 1

S3 | -


Karnaugh maps

0 1

0 -

y1

y2 0 101

1 0

0 -

y1

y2 0 101

0 0

1 -

y1

y2 0 101

Y2= y1 Y1= y2y1 z = y2

Currentstate

Outputsignal

Next state

y2y1 z Y2 Y1

0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 - - - (not 11)

1 0 1

1 1 01 1

S0S1S2


State table after Karnaughminimization

The unused state goes to S2

Currentstate

Outputsignal

Next state

y2y1 z Y2Y1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1 0

S0S1S2

S0 | 0

S1 | 0

S2 | 1

S3 | 1

(0,0,1) sequence generator


Logic circuit for the sequence

y1

y1

z

y2

y2

Clk

The implementation uses D flip-flops

Y2= y1 Y1= y2y1 z = y2

Y2 Y1


Logic circuit in the structure ofMoore machine

Clk

Input-signals

Output-signals

Combinationalcircuit


Flip-flops

Clk

Y1

z

y1

Y2 y2

Y2= y1

Y1= y2y1

z = y2

? ??


Logic circuit for the sequence

y1

y1

z

y2

y2

Clk

Y2 Y1

Clk

Input-signals

Output-signals



Flip-flops

Clk

Y1

z

y1

Y2 y2

Y2= y1

Y1= y2y1

z = y2


• When designing complex state machines, itoften happens that there are equivalentstates that can be grouped together to obtaina more efficient implementation

• Two states S1 are S2 are called equivalent ifand only if, for every possible input sequence,the same output will be produced regardlessof whether S1 or S2 is the initial state

State minimization


• The following example illustrates oneminimization method which is can be used forstate minimization

• This method identifies states which are notequivalent (this is often easier)

• First, we introduce some terminology

State minimization


• If input w = 0 is applied to a state machine instate S1 and the result is that the machinemoves to state S2, we say that S2 is a 0-successor of S1

• If input w = 1 is applied to a state machine instate S1 and the result is that the machinemoves to state S3, we say that S3 is a 1-successor of S1

• We will refer to successors as k-sucessors,where k can be 0 or 1

0- and 1-sucessors

S1

S2w=0

S3w=1


• Two states are not equivalent if they havedifferent output values

State minimizationBasic idea

Az = 1

Bz = 0≠


• Two states are not equivalent if at least oneof their k-sucessors are not equivalent

State minimizationBasic idea

Az = 1

Bz = 1≠

Cz = 1

Dz = 0

w = 1 w = 1


ExampleState minimization

Az = 1

Bz = 1

w = 0w = 0

Dz = 1

w = 1

Cz = 0

Fz = 0

w = 0

w = 0

Gz = 0

w = 1

w = 1

w = 1

w = 0

w = 1

Ez = 0

w = 0

w = 0

w = 1

w = 1

(Moore Machine)

7- states uses 3 flip-flops (23 = 8)IE1204 Digital Design, Autumn2015 22

State table

Present Next state Outputstate w = 0 w = 1 z

A B C 1

Az = 1

Bz = 1

w = 0w = 0

Dz = 1

w = 1

Cz = 0

Fz = 0

w = 0

w = 0

Gz = 0

w = 1

w = 1

w = 1

w = 0

w = 1

Ez = 0

w = 0

w = 0

w = 1

w = 1


State table


A B C 1B D F 1C F E 0D B G 1E F C 0F E D 0G F G 0

Az = 1

Bz = 1

w = 0w = 0

Dz = 1

w = 1

Cz = 0

Fz = 0

w = 0

w = 0

Gz = 0

w = 1

w = 1

w = 1

w = 0

w = 1

Ez = 0

w = 0

w = 0

w = 1

w = 1


• The minimization procedure first considersthe state of a machine as a set and thenbreaks this set into partitions that are notequivalent.

• A partition consists of one or more blocks– each block contains states that may be equivalent– different blocks contain states that are definitely

not equivalent

Partition


• Start– Just one block containing all states

• P1= (ABCDEFG)

Example state minimization


• Stage 1:– Which states have different outputs?

• ABD has output z = 1• CEFG have output z = 0• => P2= (ABD) (CEFG)

Example state minimizationP1= (ABCDEFG)

States A, B, D can therefore neverbe equivalent to any of theconditions C, E, F, G so they formdifferent groups

Az = 1

Bz = 0≠


• Stage 2– Which states have different k-successors?

• Block ABD– 0-successor: A ® B , B ® D , D ® B (all transitions go to the

same block)– 1-successor: A ® C , B ® F , D ® G (all transitions go to the

same block)• Block CEFG

– 0-successor: C ® F , E ® F , F ® E , G ® F (all transitions goto the same block)

– 1-successor: C ® E , E ® C , F ® D , G ® G (F ® D goes toanother block)

=> P3= (ABD) (CEG) (F)

Example state minimizationP2= (ABD) (CEFG)

Az = 1

Bz = 1≠

Cz = 1

Dz = 0

w = 1 w = 1

w=0

w=1

ABD

CEFG


• Stage 2– Which states have different k-successors?

• Block ABD– 0-successor: A ® B , B ® D , D ® B (all transitions go to the

same block)– 1-successor: A ® C , B ® F , D ® G (all transitions go to the

same block)• Block CEFG

– 0-successor: C ® F , E ® F , F ® E , G ® F (all transitions goto the same block)

– 1-successor: C ® E , E ® C , F ® D , G ® G (F ® D goes toanother block)

=> P3= (ABD) (CEG) (F)

Example state minimizationP2= (ABD) (CEFG)

Az = 1

Bz = 1≠

Cz = 1

Dz = 0

w = 1 w = 1

w=1

ABD

CEFG

w=0


• Step 3– What states have different k-successors?

• Block ABD– 0-successor: A ® B, B ® D, D ® B (all transitions go to the

same block)– 1-successor: A ® C, B ® F, D ® G (B ® F goes to another

block)=> P4= (AD) (B) (CEG) (F)

• Block (CEG)– 0-successor: C ® F, E ® F, G ® F (all transitions go to the

same block)– 1-successor: C ® E, E ® C, G ® G (all transitions go to the

same block)=> P4= (AD) (B) (CEG) (F)

Example state minimizationP3= (ABD) (CEG) (F)

ABD

CEG

F

w=0w=1

w=1

w=0


w=0

w=1

• Next partition P5 becomes the sameas P4. Thus the procedure is finished.– States in each block are equivalent

• if they were not, their k-successors would have tobe in different blocks

• A becomes the representive of AD and Crepresents CEG.

Example state minimizationP4= (AD) (B) (CEG) (F)

P4 = (AD)(B)(CEG)(F) = (A)(B)(C)(F)

AD

CEG

F

w=0

w=1

w=0

Bw=1


w=0

w=1

w=0

w=1

Final state table

Present Next State Outputstate w = 0 w = 1 z

A B C 1B A F 1C F C 0F C A 0



P4 = (AD)(B)(CEG)(F) = (A)(B)(C)(F)

Final State Table


Final state table





P4 = (AD)(B)(CEG)(F) = (A)(B)(C)(F)

Final State Table


Final state diagram

Az = 1

Bz = 1

w = 0

w = 1

Cz = 0

Fz = 0

w = 0

w = 0

w = 1

w = 1

w = 1

w = 0



4 states needs 2 flip-flops (22 = 4).


Comparison

• Only 2 flip-flops are needed to implement 4states in the minimized state table

• 3 flip-flops are needed to implement 7 statesin the original state table

Az = 1

Bz = 1

w = 0

w = 1

Cz = 0

Fz = 0

w = 0

w = 0

w = 1

w = 1

w = 1

w = 0

Az = 1

Bz = 1

w = 0w = 0

Dz = 1

w = 1

Cz = 0

Fz = 0

w = 0

w = 0

Gz = 0

w = 1

w = 1

w = 1

w = 0

w = 1

Ez = 0

w = 0

w = 0

w = 1

w = 1


Some thought!

• Fewer state does not necessarily lead to asimpler design!– The advantage of state minimization is instead

that it makes it easier to create the initial statediagram, when you do not have to get it to beminimal from the beginning!


• Given an implementation of asynchronous circuit, we can produce itsfunction by making the synthesis stepsin a reverse order!1. Get expressions for

• next state decoder• output decoder

2. Get the state table3. Draw the state diagram

Analysis of synchronoussequential circuits


Example: Analysis of asynchronous sequential circuit

D Q

Q

D Q

Q

Clock

Resetn

y2

y1

Y 2

Y 1

w

z

It is difficultto figure outdirectlyfrom theschematichow asequentialcircuitbehaves!


Example: Moore-machine!


1. Get expressions for• next state decoder• output decoder


212

211

wywyYwyywY

+=+=2wy

1wy

1yw

w

2yw

w1y

1y

z1y

2y

1Y

2Y


21 yyz =

2. Get the state table


Present Next State

state w = 0 w = 1 Output

y2y1 Y2Y1 Y2Y1z

0 0 0 0 01 00 1 0 0 10 01 0 0 0 11 01 1 0 0 11 1


A A B 0B A C 0C A D 0D A D 1

211 wyywY +=212 wywyY += 21 yyz ×=


A:”00” B:”01” C:”10” D:”11”

3. Draw state diagram– Left as exercise for students... (but check

the state table to make sure it is a bitsequence detector for three subsequent1s)


Az = 0

Bz = 0

Cz = 0

Dz = 1

1=w

0=w




State diagram



Az = 0

Bz = 0

Cz = 0

Dz = 1

1=w

0=w

0=w

0=w

1=w

1=w

0=w1=w

Sometimes you may need tochange the order of the statesto get a clearer chart.


State diagram



C and D have changedplaces resulting in nointersecting state arrows.

Az = 0

Bz = 0

Dz = 1

Cz = 0

1=w0=w

0=w

0=w

1=w

1=w

0=w 1=w


• State transition diagrams areconvenient for describing the behaviorof small state machines only

• To describe larger state machines,another type of diagrams, calledAlgorithmic State Machine (ASM)charts are often used

• An ASM is a flow diagram consistingof three types of elements: state box,decision box and conditional outputbox

ASM Charts

w

w

w0 1

0

1

0

1

A

B

C

z

Reset


ASM Charts

Output signalsor actions

(Moore type)

State Name

Conditionexpression

0 (False) 1 (True)

Conditional outputsor actions (Mealy type)

(A) State Box

(B) Decision box

(C) Conditional output box


• State Box– Represents a state in a FSM

• Output values for state are given here (Moore outputs)

• Decision Box– Depending on the values of the input signals, it

determines a transition to the next state• Conditional outputs Box

– Specifies the values of the outputs at a statetransition (Mealy outputs)

ASM Charts


ASM chart for11 sequence detector (Moore)

w

w

w0 1

0

1

0

1

A

B

C

z

Reset

z = 1 only in the state C

C z 1=¤

Reset

B z 0=¤A z 0=¤w 0=

w 1=

w 1=

w 0=

w 0= w 1=


ASM chart for11 sequence detector (Mealy)

z = 1 only when the state transitionB-to-B with w = 1 takes place

w

w0 1

0

1

A

B

Reset

z

A

w 0= z 0=¤

w 1= z 1=¤Bw 0= z 0=¤

Resetw 1= z 0=¤


• To treat state machines in a formal way,we need a formal model

• The following model can describe bothMoore and Mealy machines

Formal model for sequentialcircuits



CombinationalCircuit

Yk

Y1

yk

y1

w1

wn

z1

zm

Outputs

Next-statevariables

Current-statevariables

Inputs


• A synchronous sequential circuit can beformally defined as

• W, Z, and S are finite, nonempty sets of inputs,outputs and states, respectively

• φ is the state transition function, such as S(t+1) =φ[W(t), S(t)]

• λ is the output function, such as λ(t) = λ(S(t)) for theMoore model and λ(t) = λ(W(t), S(t)) for the Mealymodel


),,,,( ljSZWM =



),,,,( ljSZWM ={ }{ }{ }

{ }{ }

))(),(()())(()(

))(),((...)(

,...,,

,...,,,...,,,...,,

,...,,

1

21var

21var

21

21

21

tStWttSt

tStWYYttS

YYYYyyyy

SSSSzzzZwwwW

Mealy

Moore

m

miablesstatenext

miablesstatepresent

mstates

moutputs

minputs

llll

j

==

==D+

=

==

=

=

--

--


• Bottle dispenser consists of severalparts– COIN RECEIVER– DROP BOTTLE– COIN RETURN

• Machine accepts only the followingcoins: 1 Euro, 50 Cent, 10 Cent

• The vending machine only returns 10Cent coins

Bottle dispenser


• DROP_READY is active for one clock cycle after thebottle has been ejected

• CHANGER_READY is active for one clock cycle after a10 Cent coin is ejected

• Because of the mechanical properties, the followingsignals are active and inactive for several clock cycles:– COIN_PRESENT (active for several clock cycles after the coin

drop)– DROP_READY (active for several clock periods after bottle

drop)– CHANGER_READY (inactive for several clock periods after coin

return)

Signal Properties


Flow diagram of control system

• Coin– 10 Cent, 50 Cent, 1 Euro

• Coin return– 10 Cent

• Bottle Price– 1 Euro

Reset

Coinregistered?

Total?

Ejectbottle

Resetsum

Return10 Cent

No

Yes

Total <1 €

Total = 1 € Total> € 1

Decreasesum


State diagram (Moore)(a)

(b)

(c)

(d)

(e)

(f)

(g)

COIN_PRESENT

COIN_PRESENT

COIN_PRESENT

COIN_PRESENT

GT_I_EURO

LT_I_EURO

EQ_I_EURO

CHANGERREADY

CHANGER_READY

DROPREADY

DROP READY

DEC_ACCCLR_ACC

RETURN_10_CENTDROP

• Upon entry into the state,signal becomes active

• When exiting the state,signal becomes inactive

(a) Wait for coin

(b) Register coin

(c) Coin is registered (3 cases)

(d) Drop bottle

(e) Reset sum

(f) Return 10 Cent

(g) Decrease sum with 10 Cent


State diagram(a)

(b)

(c)

(d)

(e)

(f)

(g)

COIN_PRESENT

COIN_PRESENT

COIN_PRESENT

COIN_PRESENT

GT_I_EURO

LT_I_EURO

EQ_I_EURO

CHANGERREADY

CHANGER_READY

DROPREADY

DROP READY

DEC_ACCCLR_ACC

RETURN_10_CENTDROP

• State assignmentwith no claim foroptimality (Ad hoc)– (a) next to (b)– (b) next to (c)– (d) next to (e)– (f) next to (g)

• For all these cases,only one variablechanges

AB

00 01 11 10

C0 a - d f

1 b c e g

(”-” = don’t care)


State diagram(a)000

(b)001

(c)011

(d)110

(e)111

(f)100

(g)101

COIN_PRESENT

COIN_PRESENT

COIN_PRESENT

COIN_PRESENT

GT_I_EURO

LT_I_EURO

EQ_I_EURO

CHANGERREADY

CHANGER_READY

DROPREADY

DROP READY

DEC_ACCCLR_ACC

RETURN_10_CENTDROP

• The state diagramcontains all informationrequired to generate animplementation

• Assumption: D flip-flopsare used as stateregister

• 7 states: 3 flip-flops areneeded

The state variable order isABC, i.e. state (c) isA = 0, B = 1,C = 1


Unused state?!(a)000

(b)001

(c)011

(d)110

(e)111

(f)100

(g)101

COIN_PRESENT

COIN_PRESENT

COIN_PRESENT

COIN_PRESENT

GT_I_EURO

LT_I_EURO

EQ_I_EURO

CHANGERREADY

CHANGER_READY

DROPREADY

DROP READY

DEC_ACCCLR_ACC

RETURN_10_CENTDROP

• If fall into the unusedstate (h) we are stuck!!Possible ways out:• going to (c) and

continue.• going to (d) and

offering soft drinks!!• going to (e) and

resetting anyprevious payment.

• Which option do youprefer for your design?!

• Which option leads to asimpler design?


(h)010

Construction of next-state andoutput decoders (Moore machine)

D

D

D

NextState

Decoder

COIN_PRESENTLT_I_EURO

EQ_I_EUROGT_I_EURO

DROP_READYCHANGER_READY

ABC

DB

DC

B

C

OutputDecoder

DROP

CLR_ACCDEC_ACC

Clk

RETURN_I0_CENT

At next step, we develop the logic for the next state (DA, DB, DC) and outputs

DA A


Clk

Input-signals

Output-signals



Flip-flops

Construction of next-state andoutput decoders

D

D

D

NextState

Decoder


EQ_I_EUROGT_I_EURO


ABC

DB

DC

B

C

OutputDecoder

DROP

CLR_ACCDEC_ACC

Clk

RETURN_I0_CENT

At next step, we develop the logic for the next state (DA, DB, DC) and outputs

DA A


Clk

Input-signals Output-signals(Combinational circuit)

Outputdecoder(Combinational circuit)

Flip-flopsNext statedecoder

? ?

Decoder: Next state - DA

(a)000

(b)001

(c)011

(d)110

(e)111

(f)100

(g)101

COIN_PRESENT

COIN_PRESENT

COIN_PRESENT

COIN_PRESENT

GT_I_EURO

LT_I_EURO

EQ_I_EURO

CHANGERREADY

CHANGER_READY

DROPREADY

DROP READY

DEC_ACCCLR_ACC

RETURN_10_CENTDROP

DA AB

00 01 11 10

C0 0 - 1 1

1 0 (=) + (>) 0 0

CA)B(A)B(ADA +>+==

(=) : EQ_1_EURO(>) : GT_1_EURO

63IE1204 Digital Design, Autumn2015 63

• Variable-Entered Mapping can help to draw andminimize Karnaugh diagrams with many variables.– In this example there are several variables as:

Coin_Present, Drop_Ready, Changer_Ready, GT, LT, EQ.

• Instead of opening an "extra dimension" we write avariable into the Karnaugh map

• You must be extra careful when drawing circuits sothat you do not forget a variable combination!

Variable-Entered Mapping (VEM)

DA AB

00 01 11 10

C0 0 - 1 1

1 0 (=) + (>) 0 0


Decoder: Next state - DB

(a)000

(b)001

(c)011

(d)110

(e)111

(f)100

(g)101

COIN_PRESENT

COIN_PRESENT

COIN_PRESENT

COIN_PRESENT

GT_I_EURO

LT_I_EURO

EQ_I_EURO

CHANGERREADY

CHANGER_READY

DROPREADY

DROP READY

DEC_ACCCLR_ACC

RETURN_10_CENTDROP

DB AB

00 01 11 10

C0 0 - 1 0

1 CP (=) 0 1

CBA)CPC(BCB)B(ADB +++==

(=) : EQ_1_EUROCP : COIN_PRESENT


Decoder: Next state- DC

(a)000

(b)001

(c)011

(d)110

(e)111

(f)100

(g)101

COIN_PRESENT

COIN_PRESENT

COIN_PRESENT

COIN_PRESENT

GT_I_EURO

LT_I_EURO

EQ_I_EURO

CHANGERREADY

CHANGER_READY

DROPREADY

DROP READY

DEC_ACCCLR_ACC

RETURN_10_CENTDROP

DC AB

00 01 11 10

C0 CP - DR CR

1 1 0 0 1

CB(CR)BA

(DR)CB(CP)ACDC

++

+=

CP : COIN_PRESENTDR: DROP_READYCR: CHANGER_READY


Decoder: Output signals

• Output decoder istrivial, since its valueis directly dependenton the current state

(a)000

(b)001

(c)011

(d)110

(e)111

(f)100

(g)101

COIN_PRESENT

COIN_PRESENT

COIN_PRESENT

COIN_PRESENT

GT_I_EURO

LT_I_EURO

EQ_I_EURO

CHANGERREADY

CHANGER_READY

DROPREADY

DROP READY

DEC_ACCCLR_ACC

RETURN_10_CENTDROP

CBADEC_ACC

BCACENTRETURN_10_

ABCCLR_ACCCABDROP

=

=

==


Logic Design

D

D

D

NextState

Decoder


EQ_I_EUROGT_I_EURO


ABC

DB

DC

B

C

OutputDecoder

DROP

CLR_ACCDEC_ACC

Clk

RETURN_I0_CENT

Now you can design ”Next State Decoder” and ”Output Decoder” by knowingthe logic function of Da, Db, Dc, and logic funtion of outputs ”Drop”,”Return_10_Cent”, ”CLR_ACC”, and ”DEC_ACC”.

DA A


• State minimization• Analysis of a synchronous sequential

circuit• ASM charts• Formal model for sequential circuits• Next lecture: BV pp. 98-118, 418-426,

508-519

Summary


Documents

IE1204 Digital Design L10: State Machines (Part 2) · 2015. 9. 29. · state machines 1. Analyze the specification of the circuit 2. Create state diagrams 3. Set up the state table