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DATASHEET
XLL JUNE 20, 2017 1 ©2017 Integrated Device Technology, Inc.
IDT XO LVDS Crystal Oscillator XLL
DescriptionThe XLL is an LVDS crystal oscillator with 0.89ps typical phase jitter over 12kHz to 20MHz bandwidth. Available in a wide frequency range from 0.750MHz to 1350MHz, the IDT XLL series crystal oscillator utilizes a family of proprietary ASICs, with a key focus on noise reduction technologies.
The 3rd order Delta Sigma Modulator reduces noise to the levels that are comparable to traditional bulk Quartz and SAW oscillators. With short lead-time, low cost, low noise, wide frequency range, excellent ambient performance, the XLL is an excellent choice over the conventional technologies. The XLL has stabilities as tight as ±20ppm with extremely quick delivery for both standard and custom frequencies
Features• Frequency range: 0.750MHz to 1350MHz
• Output type: LVDS
• Frequency stability: ± 20ppm, ± 25ppm, ± 50ppm, or ± 100 ppm
• Supply voltage: 2.5V or 3.3V
• Phase jitter (1.875MHz to 20MHz): 225fs typical
• Phase jitter (12kHz to 20MHz): 0.89ps typical
• Package options: 3.2mm x 2.5mm x 1.0mm (JX6)5.0mm x 3.2mm x 1.2mm (JS6)7.0mm x 5.0mm x 1.3mm (JU6)
• Operating temperatures: -20°C to +70°C or -40°C to +85°C
Pin Assignment
Pin Descriptions
1. Pulled high internally.
Pin Number Pin Name Description
1 E/D Enable/Disable1 (0=Output Disabled)
2 NC No connect
3 GND Connect to ground
4 OUT Output
5 OUT2 Complementary Output
6 VDD Supply voltage
1 2 3
456
6-pin CLCC
E/D NC
OU
T
OU
T2
VD
D
GN
D
IDT XO LVDS CRYSTAL OSCILLATOR 2 JUNE 20, 2017
XLL DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the XLL. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
ESD Compliance
Mechanical Testing
Solder Reflow Profile
Item Rating
VDD -0.5 to +5.0V
E/D -0.5V to VDD + 0.5V
OUT -0.5V to VDD + 0.5V
Storage Temperature -55°C to 125°C
Theta Ja (Junction to Ambient) 102°C/W – Still Air
Human Body Model (HBM 1000V
Machine Model (MM) 150V
Parameter Test Method
Mechanical Shock Drop from 75cm to hardwood surface–3 times
Mechanical Vibration 10–55Hz, 1.5mm amplitude, 1 minute sweep2 hours each in 3 directions (X, Y, Z)
High Temperature Burn-in Under power at 125°C for 2000 hours
Hermetic Seal He pressure: 4 ±1kgf/cm2 2 hour soak
tP 10 seconds Max within 5°C of 260°C peak
Ramp down not to exceed 6°C/s
Ramp up 3°C/s Max
120 ±20 seconds in pre-heating
area
50 ±10 seconds
above 225°C reflow area
400 seconds MAX from +25°C to 260°C peak
25°C
160°C
180°C
225°C
260°C
JUNE 20, 2017 3 IDT XO LVDS CRYSTAL OSCILLATOR
XLL DATASHEET
DC Characteristics (VDD= 3.3V ±5%, TA= - 20°C to +70°C; -40° to +85°C)
* A pullup resistor from pin 6 (VDD) to pin 1 (E/D) enables output when pin 1 is left open.
AC Characteristics (VDD= 3.3V ±5%, TA= - 20°C to +70°C; -40° to +85°C)
Note: Inclusive of initial frequency accuracy, operating temperature range, supply variation, load variation, 3 times solder reflow, shock, vibration and 1 year aging at 25°C. We do not recommend hand soldering the devices
Parameter Symbol Condition Min Typ Max Units
Power Supply Current IDD Common Frequencies 100 mA
Differential Output Voltage VOD Standard LVDS load 0.6 V
Output Offset Voltage VOS Standard LVDS load 1.3 V
Enable/Disable Input HIGH Voltage (Output enabled)*
VIH 70%VDD V
Enable/Disable Input LOW Voltage(Output disabled)
VIL 30%VDD V
Parameter Symbol Condition Min Typ Max Units
Output Frequency Range FOUTR 0.750 1350 MHz
Frequency Stability Temperature = -20°C to +70°C ±20 ±100 ppm
Temperature = -40°C to +85°C ±25 ±100 ppm
Aging (1st year) Ta = 25°C 3
Aging (10 years) Ta = 25°C 10
Output Load Differential 100 Ohms
Start-up Time TST Output valid time after VDD meets minimum specified level
10 ms
Output Rise Time 20% to 80% VPP 400 ps
Output Fall Time 80% to 20% VPP 400 ps
Output Clock Duty Cycle TDTCY 50%VP-P 45 55 %
Output Enable/ Disable Time TOE 100 ns
Period Jitter, RMS JPER Frequency = 156.25MHz 3.0 ps
Random Jitter RJ Frequency = 156.25MHzPer MJSQ spec (Methodologies for Jitter and Signal Quality specifications)
1.3 ps
Deterministic Jitter DJ 5.8 ps
Total Jitter TJ 23.6 ps
Phase Jitter (12kHz – 20MHz) JITTER Common Frequencies 0.89 ps
Phase Noise PerformanceFrequency = 156.25MHz
NOISE 100Hz of Carrier -80 dBc/Hz
1kHz of Carrier -115 dBc/Hz
10kHz of Carrier -118 dBc/Hz
100kHz of Carrier -124 dBc/Hz
1MHz of Carrier -142 dBc/Hz
10MHz of Carrier -151 dBc/Hz
Output Frequency (Common) FOUT 100MHz, 106.25MHz, 1258MHz, 150MHz, 155.52MHz, 156.25MHz, 200MHz, 212.5MHz, 250MHz, 300MHz, 312.5MHZ, 400MHz(Contact IDT for additional frequencies)
IDT XO LVDS CRYSTAL OSCILLATOR 4 JUNE 20, 2017
XLL DATASHEET
DC Characteristics (VDD= 2.5V ±5%, TA= - 20°C to +70°C; -40° to +85°C)
* A pullup resistor from pin 6 (VDD) to pin 1 (E/D) enables output when pin 1 is left open.
AC Characteristics (VDD= 2.5 ±5%, TA= - 20°C to +70°C; -40° to +85°C)
Note: Inclusive of initial frequency accuracy, operating temperature range, supply variation, load variation, 3 times solder reflow, shock, vibration and 1 year aging at 25°C. We do not recommend hand soldering the devices
Parameter Symbol Condition Min Typ Max Units
Power Supply Current IDD Common Frequencies 26 65 mA
Differential Output Voltage VOD Standard LVDS load 0.4 V
Output Offset Voltage VOS Standard LVDS load 1.25 V
Enable/Disable Input HIGH Voltage (Output enabled)*
VIH 70%VDD V
Enable/Disable Input LOW Voltage(Output disabled)
VIL 30%VDD V
Parameter Symbol Condition Min Typ Max Units
Output Frequency Range FOUTR 0.750 1000 MHz
Frequency Stability Temperature = -20°C to +70°C ±20 ±100 ppm
Temperature = -40°C to +85°C ±25 ±100 ppm
Output Load Differential 100 Ohms
Start-up Time TST Output valid time after VDD meets minimum specified level
10 ms
Output Rise Time 20% to 80% VPP 400 ps
Output Fall Time 80% to 20% VPP 400 ps
Output Clock Duty Cycle TDTCY 50%VP-P 45 55 %
Output Enable/ Disable Time TOE 100 ns
Period Jitter, RMS JPER Frequency = 156.25MHz 4.0 ps
Random Jitter RJ Frequency = 156.25MHzPer MJSQ spec (Methodologies for Jitter and Signal Quality specifications)
1.4 ps
Deterministic Jitter DJ 9.2 ps
Total Jitter TJ 29.2 ps
Phase Jitter (12kHz – 20MHz) JITTER Frequency = 156.25MHz 1.04 ps
Phase Noise PerformanceFrequency = 156.25MHz
NOISE 100Hz of Carrier -83 dBc/Hz
1kHz of Carrier -105 dBc/Hz
10kHz of Carrier -113 dBc/Hz
100kHz of Carrier -119 dBc/Hz
1MHz of Carrier -137 dBc/Hz
10MHz of Carrier -146 dBc/Hz
Output Frequency (Standards) FOUT 100MHz, 106.25MHz, 1258MHz, 150MHz, 155.52MHz, 156.25MHz, 200MHz, 212.5MHz, 250MHz, 300MHz, 312.5MHZ, 400MHz(Contact IDT for additional frequencies)
JUNE 20, 2017 5 IDT XO LVDS CRYSTAL OSCILLATOR
XLL DATASHEET
Output Waveform
Typical Phase Noise (3.3V)
Oscillator Symmetry
Output Levels/Rise Time/Fall Time Measurements
OUTPUT 2
OUTPUT 1
OUTPUT 2
OUTPUT 1
50% VPP
VOH
VOL
VOD
½ Period
Period
TR TF
20% to 80% VPP
Ideally, Symmetry should be 50/50 for ½ period –Other expressions are 45/55 or 55/45
50% VPP VOS
IDT
XO L
VDS
CR
YSTA
L O
SCIL
LATO
R6
JUN
E 20
, 201
7
XLL
DAT
ASH
EET
JS6
Pac
kag
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E 20
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77
IDT
XO L
VDS
CR
YSTA
L O
SCIL
LATO
R
XLL
DAT
ASH
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JS6
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IDT
XO L
VDS
CR
YSTA
L O
SCIL
LATO
R8
JUN
E 20
, 201
7
XLL
DAT
ASH
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JU6
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JUN
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IDT
XO L
VDS
CR
YSTA
L O
SCIL
LATO
R
XLL
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ASH
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JU6
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IDT
XO L
VDS
CR
YSTA
L O
SCIL
LATO
R10
JUN
E 20
, 201
7
XLL
DAT
ASH
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JX6
Pac
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JUN
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, 201
711
IDT
XO L
VDS
CR
YSTA
L O
SCIL
LATO
R
XLL
DAT
ASH
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JX6
Pac
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e O
utl
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IDT XO LVDS CRYSTAL OSCILLATOR 12 JUNE 20, 2017
XLL DATASHEET
IDT Ordering Information
XLFamily and ASIC
LOutput Type
5Package
3Voltage
5Precision
125.000000Frequency
ITemperature Range
I: Industrial range ‐40 to +85 °C
K: Extended industrial range ‐40 to +105 °CX: Extended commercial range ‐20 to +70 °C
V: 50 ppm APR (VCXO)
0: ±100 ppm
5: ±50 ppm6: ±25 ppm
8: ±20 ppm
1: 1.8 VDC ±5%
2: 2.5 VDC ±5%3: 3.3 VDC ±5%
3: 3.2 x 2.5 mm
5: 5.0 x 3.2 mm
7: 7.0 x 5.0 mm
H: HCMOS Enable/Disable Pin 1
J: HCMOS Enable/Disable Pin 2
L: LVDS Enable/Disable Pin 1
M: LVDS Enable/Disable Pin 2
P: LVPECL Enable/Disable Pin 1Q: LVPECL Enable/Disable Pin 2N: HCSL Enable/Disable Pin 1
O: HCSL Enable/Disable Pin 2
X: XHCMOS Comp HCMOS Enable /Disable Pin 1
Y: XHCMOS Comp HCMOS Enable/Disable Pin 2
XL: 1,000fs jitter
XU: 400fs jitter
125.000000 Listed in MHz as example
3 digits before decimal and 6 digits past decimal
000.016000 to 000.999999 16.000kHz to 999.999kHz
001.000000 to 009.999999 1.000000MHz to 9.999999MHz
010.000000 to 099.999999 10.000000MHz to 99.999999MHz
100.000000 to 999.999999 100.000000MHz to 999.999999MHz
A00.000000 to A99.999999 1000.000000MHz to 1099.999999MHz
B00.000000 to B99.999999 1100.000000MHz to 1199.999999MHz
C00.000000 to C99.999999 1200.000000MHz to 1299.999999MHz
D00.000000 to D99.999999 1300.000000MHz to 1399.999999MHz
E00.000000 to E99.999999 1400.000000MHz to 1499.999999MHz
F00.000000 1500.000000MHz
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, withoutnotice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installedin customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for anyparticular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intel-lectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonablyexpected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property ofIDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.
Corporate Headquarters6024 Silver Creek Valley Road San Jose, CA 95138 USAwww.IDT.com
Sales1-800-345-7015 or 408-284-8200 Fax: 408-284-2775www.IDT.com/go/sales
Tech Supportwww.IDT.com/go/support
XLL JUNE 20, 2017 13 ©2017 Integrated Device Technology, Inc.
Revision History
Date Originator Description of Change
10/28/16 P. Jenkins Update ordering information decoder tables by separating them into Scheme 1 and Scheme 2; add note to distinguish the two tables.
06/13/17 L.S. Removed “Ordering Information Scheme #1 (for reference only)”. Replaced with a single ordering information table.
06/20/17 L.S. Corrected frequency errors in Ordering Information table.