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© imec 2002
Identification of Critical Parameters for Plasma-Induced
Damage in 130 and 100nm CMOS technologies
Geert Van den bosch, Brice De Jaeger,Zsolt Tőkei and Guido Groeseneken
IMECLeuven, Belgium
© imec 2002 GVDB – ESSDERC02 2
Outline
IntroductionAssessment methodologyCritical process steps and modulesGate oxide thickness dependenceLong-term reliability projectionConclusions
© imec 2002 GVDB – ESSDERC02 3
Introduction
n 100/90nm CMOS will have ~1.5nm oxynitride in FEOL, Cu/low-k damascene in BEOL. n New steps and materials have to be integratedn Their reliability must be guaranteed
n In ultrathin oxide the main manifestation of P2ID is a consumption of available time-to-breakdown. n Not only yield but also reliability issue.
n P2ID assessment itself must be reconsidered:n antennas suitable for damascene BEOLn detection methods of charging damage in ultrathin oxide
n Fundamental scaling issues wrt P2ID are not well established: n gate oxide thickness dependence in ultrathin regimen impact on gate oxide long-term reliability
© imec 2002 GVDB – ESSDERC02 4
Outline
IntroductionAssessment methodologyCritical process steps and modulesGate oxide thickness dependenceLong-term reliability projectionConclusions
© imec 2002 GVDB – ESSDERC02 5
Antennas for SD and DD BEOL
Trench process steps (leading to metal interconnect) cannot be evaluated by simple metal antennas.
n Charging is collected by contacts (vias) in the trench bottom.
Trench layout provides an additional free parameter: confinement of the hole by the trench walls.
n Quantified by opening angle Ω of contact (via) hole to plasma.
© imec 2002 GVDB – ESSDERC02 6
Antennas for SD and DD BEOL
M1 grid-on-contact, M2 grid-on-via variations with increasing confinement of contact (via) holes.
Ω
Ω
© imec 2002 GVDB – ESSDERC02 7
P2ID evaluation in thin oxides
Contact antenna conventional Ig (tox=3.5nm @2V)
n Very low current level, featureless distributions.n Quantitative P2ID info heavily depends on spec.
10-13
10-11
10-9
10-7
10-5
2 contacts100 contacts1e3 contacts1e4 contacts
0 20 40 60 80 100
Gat
e cu
rren
t (A
)
Percent
© imec 2002 GVDB – ESSDERC02 8
High-bias, short-time pre-stress before conventional Ig*
Pre-stress to reveal latent damage & soft failures.*(G. Van den bosch et al., P2ID2002)
P2ID evaluation in thin oxides
10-13
10-11
10-9
10-7
10-5
0.001
0 20 40 60 80 100
2 contacts100 contacts1e3 contacts1e4 contacts
Gat
e cu
rren
t (A
)
Percent
0 20 40 60 80 100
Percent
@2V @2V after ~1s@5V
© imec 2002 GVDB – ESSDERC02 9
Outline
IntroductionAssessment methodologyCritical process steps and modulesGate oxide thickness dependenceLong-term reliability projectionConclusions
© imec 2002 GVDB – ESSDERC02 10
Optimisation of PreClean time at DD level
PreClean time should be taken minimal.Dramatic impact of M2 grid-on-via layout.
0
20
40
60
80
100
4 5 6 7 8 9 10
1e3 vias
10s preclean30s preclean
Ant
enna
yie
ld (%
)
opening angle (%)
Case 1: Ar-PreClean before Cu-barrier
CONVENTIONALVIA ANTENNA
(M2 PLATE)
© imec 2002 GVDB – ESSDERC02 11
Case 2: Cu-barrier PVD
Benchmarking first and next generation I-PVD
Different plasma/bias power and temperature.P2ID response similar for the two generations.
0
20
40
60
80
100
2 1e2 1e3 1e4
next generation I-PVDfirst generation I-PVD
Ant
enna
yie
ld (%
)
Antenna size (#contacts)
© imec 2002 GVDB – ESSDERC02 12
Case 3: Wafer temperature
Impact of wafer cool time before I-PVD
Lower P2ID with lower wafer temperature.Temperature is crucial as it determines tBD.
0
20
40
60
80
100
2 1e2 1e3 1e4
Short cool timeLong cool time
Ant
enna
yie
ld (%
)
Antenna size (#contacts)
© imec 2002 GVDB – ESSDERC02 13
Outline
IntroductionAssessment methodologyCritical process steps and modulesGate oxide thickness dependenceLong-term reliability projectionConclusions
© imec 2002 GVDB – ESSDERC02 14
Motivation and approach
n Oxide thickness dependence of P2ID is crucial element for further downscaling of technology.
n Contradictory results reported in literature, partly because of uncertainty in evaluation. Can we reach conclusive results with proper detection of P2ID?
n Dedicated experiment in which antennas received fixed processing except for gate oxide growth.
n Level-by-level assessment of P2ID with pre-stress evaluation methodology.
n Each tox requires the proper pre-stress targeted to equal time-to-breakdown.
© imec 2002 GVDB – ESSDERC02 15
Poly level
n Lot of hard P2ID failures seen by conventional Ig
n Slow recovery of P2ID ≤ 3.0nm
0
20
40
60
80
100
5.0nm 3.5nm 3.0nm 2.0nm 1.8nm 1.5nm
Ant
enna
yie
ld (%
)
Gate oxide thickness
0
20
40
60
80
100AR=1e3 AR=1e4 AR=1e5
Ant
enna
yie
ld (%
)CONVENTIONAL
PRE-STRESS
© imec 2002 GVDB – ESSDERC02 16
Contact level
n mostly very soft failures not seenby conventional Ig measurement
n sharp recovery of P2ID ≤ 2.0nm
n absence of P2ID is confirmed by TDDB
CONVENTIONAL
PRE-STRESS
0
20
40
60
80
100100 cts 1e3 cts 1e4 cts
Ant
enna
yie
ld (%
)
0
20
40
60
80
100
5.0nm 3.5nm 3.0nm 2.0nm 1.8nm 1.5nm
Ant
enna
yie
ld (%
)
Gate oxide thickness
© imec 2002 GVDB – ESSDERC02 17
Outline
IntroductionAssessment methodologyCritical process steps and modulesGate oxide thickness dependenceLong-term reliability projectionConclusions
© imec 2002 GVDB – ESSDERC02 18
Long-term reliability projection
Calculate impact of initial P2ID yield loss F0 on product lifetime τ with weibull breakdown statistics.
Impact on τ is smaller with thinner gate oxide.
0.01
0.1
1
0.0001 0.001 0.01 0.1
Rel
ativ
e lif
etim
e τ/
τ ref
Plasma charging induced yield loss F0
β=4.9(tox~5nm)
Fspec=100ppm
β=1.2(tox~1.5nm)
β=1.8(tox~3.5nm)
© imec 2002 GVDB – ESSDERC02 19
Outline
IntroductionAssessment methodologyCritical process steps and modulesGate oxide thickness dependenceLong-term reliability projectionConclusions
© imec 2002 GVDB – ESSDERC02 20
Conclusions
n Critical parameters of P2ID in advanced CMOS have been identified.
n Dedicated antennas for SD and DD BEOL are needed. Improvement of conventional gate current measurement methodology is mandatory.
n P2ID of damascene BEOL can be kept under control. Wafer temperature is a critical process parameter.
n P2ID is relaxed in ultrathin oxynitrides 2nm and below. Whether this is also valid for high-k dielectrics remains an open question.
n Long-term product reliability is less sensitive to P2ID when gate oxide thickness is reduced.
© imec 2002 GVDB – ESSDERC02 21
Acknowledgements
C. Demeurisse, E. Augendre, M. Jurczak, I. Debusschere, M. Van Hove (IMEC)
Part of this work was funded by
n Alcatel Microelectronics in IWT project AUT/990241 (Plasma Induced Damage)
n MEDEA+ project T201 (CMOS logic 0.1µm and below)