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ICE Emulator for Z80 and Z180
TRACE32 Online Help
TRACE32 Directory
TRACE32 Index
TRACE32 Documents ......................................................................................................................
ICE In-Circuit Emulator .................................................................................................................
ICE Target Guides ......................................................................................................................
ICE Emulator for Z80 and Z180 .............................................................................................. 1
WARNING .............................................................................................................................. 4
Quick Start ............................................................................................................................ 5
Troubleshooting ................................................................................................................... 8
Hang-Up 8
Dual-Port Errors 8
FAQ ........................................................................................................................................ 9
Basics .................................................................................................................................... 11
Peripherals Window 11
Z80182 Emulation hints 11
Probe Configuration 12
Emulation Modes 17
SYStem.Clock Clock generation 18
SYStem.CPU MCU operation modes 18
SYStem.Access Dual-port access 19
General Settings and Restrictions ...................................................................................... 20
Restrictions 20
SYStem.Line BusReq Bus access control 20
SYStem.Option REFresh Trace option 21
SYStem.Option Wait options 21
SYStem.Option OMCR OMCR register 21
SYStem.Option DOut Bus control for daisy chain 22
SYStem.Option IO8 Size of I/O space 22
SYStem.Option V33 Voltage sense 22
Exception Control ................................................................................................................ 23
Schematics 24
RESET 24
BUSREQ Line 25
Interrupt Control 26
ICE Emulator for Z80 and Z180 1 ©1989-2019 Lauterbach GmbH
eXception.Activate Force exception 26
eXception.Enable Enable exception 27
eXception.Trigger Trigger on exception 28
eXception.Pulse Stimulate exception 29
eXception.Vector Define vector 29
MAP.DMA DMA area 30
EEPROM Management ......................................................................................................... 31
Using the MMU for Banked Target Systems ...................................................................... 32
SYStem.BankFile Select banking file 32
SYStem.Bank Select bank mode 33
Internal Bank 33
External Bank 34
Extended 35
Parameters for Banking Program 36
Memory and IO Access Routines 37
Using the MMU for Z180 37
Memory Classes ................................................................................................................... 40
State Analyzer ....................................................................................................................... 42
Keywords for the Trigger Unit 42
General Keywords for the Trigger Unit 42
Z80/ED/FD/CB Keywords for the Trigger Unit 44
Z180 Keywords for the Trigger Unit 44
8085 Keywords for the Trigger Unit 44
Keywords for the Display 45
Port Analyzer ........................................................................................................................ 46
Keywords for the Port Analyzer (Z180,84C15) 46
Keywords for the Port Analyzer (Z181) 47
Additional Trace Channels .................................................................................................. 49
Compilers .............................................................................................................................. 53
3rd-Party Tool Integration ................................................................................................... 54
Realtime Operation Systems ............................................................................................... 56
Emulation Frequency ........................................................................................................... 57
Emulation Modules .............................................................................................................. 58
Module Overview 58
Order Information 58
Physical Dimensions ........................................................................................................... 60
Adapter .................................................................................................................................. 71
ICE Emulator for Z80 and Z180 2 ©1989-2019 Lauterbach GmbH
ICE Emulator for Z80 and Z180
Version 06-Nov-2019
For general informations about the In-Circuit Debugger refer to the “ICE User’s Guide” (ice_user.pdf). All general commands are described in “PowerView Command Reference” (ide_ref.pdf) and “General Commands and Functions”.
P:000D75 \\IARZ80\iarz80\sieve+97 ........... MIX A
E::w.d.laddr/line code label mnemonic commentP:000D70 AF xor aP:000D71 ED42 sbc hl,bcP:000D73 381E jr c,0D93 ; c,?0176
{491 flags[ k ] = FALSE;
P:000D75 0E00 ?0178: ld c,0 ; c,0P:000D77 2111C2 ld hl,0C211 ; hl,flagsP:000D7A DD5EFC ld e,(ix-4) ; e,(ix-4)
E::w.v.f /l /c E::w.rj = 15 CY _ A 0 BC 800F SP >0000
{ N N F 2 DE 0C40C -06 0003sieve(); P/V _ B 80 HL 3 -04 000F
-000 sieve() Hc _ C 0F IX 0C40F -02 0000i = 0 Zr _ D 0C4 IY 2D8 FP >C41Fprimz = 3 Sig _ E 0C SP 0C407 +02 0CDCk = 15 IFF _ I 0 PC 0D75 +04 000Fanzahl = 0 Tsk AF' 0 +06 0000
ICE Emulator for Z80 and Z180 3 ©1989-2019 Lauterbach GmbH
WARNING
NOTE: Do not connect or remove probe from target while target power is ON.
Power up: Switch on emulator first, then targetPower down: Switch off target first, then emulator
ICE Emulator for Z80 and Z180 4 ©1989-2019 Lauterbach GmbH
Quick Start
Before debugging can be started, the emulator must be configured by software:
Ready to run setup files for most standard compilers can be found on the software CD in the directory ../Demo/Z80/Compiler. All setup files are designed to run the emulator stand alone without target hardware.
The following description should make the initial setup (to run the emulator together with the target hardware) easier. It describes a typical setup with frequently used settings. It is recommended to use the programming language PRACTICE to create a batch file, which includes all necessary setup commands. PRACTICE files (*.cmm) can be created with the PRACTICE editor pedit (Command: PEDIT <file name>) or with any other text editor.
A basic setup file includes the following parts:
1. Set cpu-type and -mode
2. Set system options
3. Select dualport mode (optional)
4. Set mapper (optional)
5. Select frequency (optional)
6. Activate the emulator
7. Load application file (optional)
8. Set breakpoints (optional)
9. Start application
10. Stop application (optional)
ICE Emulator for Z80 and Z180 5 ©1989-2019 Lauterbach GmbH
Here a typical example, how to setup the system:
1. Set cpu-type
The command sys.cpu is used to select one derivative within a cpu-family and to set its operation mode.
2. Set system options
The system window controls the CPU specific setup. Please check this window very carefully and set
the appropriate options. Use the button in the main tool bar and click to the option check box (Command: HELP.PICK) to get online help in a pop up window.
3. Select dualport mode (optional)
Dualport allows access to emulation RAM, while emulation is running. This is necessary to display variables, set breakpoints or display the flag listings while the emulation is running. System.Access selects how dualport access is done.
4. Set mapper (optional)
The mapper controls the memory access of the CPU. This means the use of internal or external memory, the protection of a memory bank etc. Address ranges must be defined by using memory classes.
system.downsystem.cpu Z182
; switch the system down; select derivative Zilog Z182
system.option IO8 on ; inform the ICE that you are using only ; 8 bit addresses
system.access denied ; dualport is disabled
map.resetmap.ram P:0x0--0x0ffffmap.ram D:0--0x0FFFF
map.intern P:0x0--0x0ffffmap.extern D:
; reset mapper (all external); emulation RAM: 64KB (e.g. for; program) ; emulation RAM: 64KB (e.g. for data); map program memory internal; map data memory external
?
ICE Emulator for Z80 and Z180 6 ©1989-2019 Lauterbach GmbH
5. Select frequency (optional)
The CPU can be clocked by an internal (emulator) or external (target) clock source. If the internal clock is used, the clock is provides by the VCO of the emulator. The setting of the internal clock is done by the “vco” command.
The current CPU frequency can be displayed in the counter window.
6. Activate the emulator
When the emulator is activated a debug-monitor program is loaded into a hidden emulator memory. Afterwards, a bondout reset-signal is inactivated and the monitor program starts. This program allows access to user memory (data.dump, data.list) and cpu-registers, and gives control to start and stop the emulation.
7. Load application file (optional)
Application can be loaded by various file formats. UBROF format is often used to load code and symbol information. For information about the load command for your compiler see Compiler.
8. Set breakpoints (optional)
There are several ways to set breakpoints (Command: Break.Set). Breakpoints can be displayed using the Break.List command.
9. Start application
Application can be started with giving a break address. For example “go main” starts the application and stops at symbol main.
vco.clock 20. ; input clock to the EXTAL pin of the; cpu is set to 20 MHz (only necessary; if internal clock is used)
system.mode emulint ; system works with internal target clock
d.load.u iarz180.dbg ;load application file
breakpoint.set main /program
breakpoint.set flags /write
; set program break on function; main; set write break on variable; ’flags’
go ; run application
ICE Emulator for Z80 and Z180 7 ©1989-2019 Lauterbach GmbH
Troubleshooting
Hang-Up
If you are not able to stop the emulation, there may be some typically reasons:
Dual-Port Errors
To realize the dual-port access (emulation memory) the BUSREQ-line of the CPU is used. Dual-port accesses are allowed only while no external request to the bus occurs and the CPU cycle is completed. If the emulation CPU is in RESET state of the CPU the system controller may always access the emulation memory.
Dual-port errors may occur by the following conditions:
1. The length of the CPU cycle is extended by wait cycles, so that the request timeout signal is generated.
2. External DMA requests (single cycles) are too long.
To solve problems with dualport error first increase the SYStem.TimeReq value. Be sure that the SYStem.TimeOut value is bigger than the access time limit. If it is not possible to solve the problem by changing the values, you must switch to DENIED mode. In this mode no access to memory is possible while running realtime emulation. The internal dual-port access can increase the reaction time for external DMA requests. The performance reduction by the dual-port access is typically 1% with some data windows (dual-ported) on the screen and may be at max. 5% when using dynamic emulation memory.
Clock Error The clock lines between the target and the oscillator of the MCU are very short. Therefore normally no problems should occur when using an external crystal. The clock line for all Z80 type processors is very critical.
Analyzer Function If you switch off the analyzer and the CPU has stopped operation, an invalid display occurs. Make a SYStem.Up command to see the true trace information.
ICE Emulator for Z80 and Z180 8 ©1989-2019 Lauterbach GmbH
FAQ
Debugging via VPN
Ref: 0307
The debugger is accessed via Internet/VPN and the performance is very slow. What can be done to improve debug performance?
The main cause for bad debug performance via Internet or VPN are low data throughput and high latency. The ways to improve performance by the debugger are limited:
In PRACTICE scripts, use "SCREEN.OFF" at the beginning of the scriptand "SCREEN.ON" at the end. "SCREEN.OFF" will turn off screenupdates. Please note that if your program stops (e.g. on error) without exe-cuting "SCREEN.OFF", some windows will not be updated.
"SYStem.POLLING SLOW" will set a lower frequency for target statechecks (e.g. power, reset, jtag state). It will take longer for the debugger torecognize that the core stopped on a breakpoint.
"SETUP.URATE 1.s" will set the default update frequency ofData.List/Data.dump/Variable windows to 1 second (the slowest possiblesetting).
Prevent unneeded memory accesses using "MAP.UPDATEONCE<address_range>" for RAM and "MAP.CONST <address_range>" forROM/FLASH. Address ranged with "MAP.UPDATEONCE" will read thespecified address range only once after the core stopped at a breakpoint ormanual break. "MAP.CONST" will read the specified address range onlyonce per SYStem.Mode command (e.g. SYStem.Up).
ICE Emulator for Z80 and Z180 9 ©1989-2019 Lauterbach GmbH
Target Power Supply Switch
Ref: 0103
Is there a simple way to control target power supply via the ICE to prevent problems after the ICE has been powered off?
Follow the sequence below.
If you own an output probe COUT8, connect it to the STROBE output con-nector.
Type PULSE2. and press F1. You will get the pin out of the output probeCOUT8. Pin 13 (OUT6) delivers +5 V after the emulator has finished its ini-tialization and 0 V if the emulator is powered off. This can be used to drivea relay via a transistor to switch the target power on and off automatically ifthe Pulse Generator is not used for other purposes. The schematic of theswitching unit can be found in the file TARGETC.CMM.
Additionally Pin 13 (OUT6) can be controlled by ICE commands.
Target power supply off. "PULSE2.P +" Target power supply on. "PULSE2.P -"
The following PRACTICE command file creates 3 buttons in the Toolbox for:
Target power on Target power off Target power off and QUIT.
To show the buttons automatically after starting the TRACE32 software, call the script with the DO command from system-settings.cmm in your TRACE32 system directory (create system-settings.cmm if it does not exist).
https://www.lauterbach.com/faq/targetc.cmm
Wrong Location after Break
Ref: 0030
Why is the location after break wrong?
Most emulators use some bytes of user stack for the break system. Therefore it is necessary to have valid stack, if single step or breakpoints are used.
Z80C15
Z84C11/C13/C15 Emulation
Ref: 0047
How must a Z84C15 target be prepared for the emulation, using a Z80 emulator?
To run the emulation mode on the target CPU, the EV pin must be tied to "high". The TRACE32 Z80 emulation probes of the Z84C11/C13/15 emulators, drive the EV pin with a 100 Ohm resistor. On the target, it is recommended to connect the EV pin via a 1 kOhm resistor to ground.
ICE Emulator for Z80 and Z180 10 ©1989-2019 Lauterbach GmbH
Basics
The ICE-80 emulation head supports all Z80 derivatives from Zilog, Renesas and Toshiba and further the 8085 from Intel or NEC. The adaption to different probes is done by changing modules. Modules support both DIL and PLCC versions, if available. The maximum frequency of the base module is 20 MHz. The modules are delivered with the fastest available chip. The emulation probes support all modes of the CPUs, some modes without dual-port access capability. The 8085, Z80 and TMPZ84Cxx probes support 256 banks with 64K each. The Z180 like probes may run with 16 banks of 1 MByte each. An additional slot in the base module offers upgrading with the Port-Analyzer to get timing and state trace features for all MCU I/O ports.
Peripherals Window
After the internal IO base address has changed (Z180,Z181,Z182), the Peripherals Windows must be reprogrammed. Use the PER.RP command, otherwise the windows has a wrong content.
Z80182 Emulation hints
IMPORTANT:
For emulation without a target or for emulation of a target but without a CPU on it, put a Z80182 CPU into the socket at the Z182 adapter.
For emulation of a target with a CPU on it, remove the Z80182 CPU from the Z182 adapter.
In order to emulate a Z80182 target, the CPU on the target (if there is one) must stay in the special mode (Mode1). This mode is selected if pin EV1 is connected to VCC, and pin EV2 is connected to GND. It cannot be accomplished through any emulator instruction. The user must cater for the correct signal levels by himself. For a normal operation without an emulator (Mode0), it is recommended to connect both pins to the appropriate level via 2 high-resistive resistors. The Z80182 probe is able to drive these pins via 100 Ohm resistors to Mode1.
Bear in mind, that the Z80182 is emulated with a Z180 CPU. The internal peripherals should only be moved to the IO base addresses xx00,xx40 or xx80. The additional internal peripherals (start at IO:xxD8) can only be accessed if the emulator is in mode Emulation External or Emulation Internal.
ICE Emulator for Z80 and Z180 11 ©1989-2019 Lauterbach GmbH
Probe Configuration
Z80
: = Jumper open I = Jumper closed
Z80-DILZ84C00-DIL
Z84C0020MHz
I :
I : .................
Z80-PLCCZ84C00-PLCC
Z84C0020MHz
: I
I :
ICE Emulator for Z80 and Z180 12 ©1989-2019 Lauterbach GmbH
Z84C01
..
I : Z84C0110MHz
: I
Z84C50withXTAL
..Z84C50
I : Z84C0110MHz
: I
ICE Emulator for Z80 and Z180 13 ©1989-2019 Lauterbach GmbH
Z84C50withoutXTAL(CLK in)
Onlyexternal ..Clock Z84C50
: I Z84C0110MHz
I :
ICE Emulator for Z80 and Z180 14 ©1989-2019 Lauterbach GmbH
HD64180
HD64180
I
HD64180
Z180
:
Z180MPU10..15MHz
ICE Emulator for Z80 and Z180 15 ©1989-2019 Lauterbach GmbH
84C11/13/15
Z84C11/15
Z84C0020MHz
1
: I
I :II:II
ICE Emulator for Z80 and Z180 16 ©1989-2019 Lauterbach GmbH
Emulation Modes
The emulation head can stay in 6 modes. The modes are selected by the SYStem.Up or the SYStem.Mode command.
In active mode, the power of the target is sensed and by switching down the target the emulator changes to RESET mode. The probe is not supplied by the target. When running without target, the target voltage is simulated by an internal pull-up resistor.
Format: SYStem.Mode <mode>
<mode>: ResetDownResetUpAloneIntAloneExtEmulIntEmulExt
Reset Down Target is down, all drivers are in tristate mode.
Reset Up Target has power, drivers are logically in inactive state, but not tristate.
Alone Internal Probe is running with internal clock, driver inactive, the dual-chip target CPU is not activated.
Alone External Probe is running with external clock, driver inactive, the dual.chip target CPU is not activated.
Emulation Internal Probe is running with internal clock, strobes to target are generated.
Emulation External Probe is running with external clock, strobes to target are activated.
E::w.syssystem Mode Clock TimeReq CPUDown RESet VCO 1.000ms Mode0
Up Analyzer Low TimeOut Mode1Monitor Mid 50.000us Mode2
RESet ResetDown High Mode3ResetUp Line EXTern
cpu-type NoProbe Access BusReqZ180 AloneInt Nodelay
AloneExt REFresh OptionEmulInt Request REFresh
BankMode EmulExt Denied RamWaitOFF FAST
INTern BankFile DOut EXTern G:\LOT\BNK80.BNK OMCRExtended FF
ICE Emulator for Z80 and Z180 17 ©1989-2019 Lauterbach GmbH
SYStem.Clock Clock generation
SYStem.CPU MCU operation modes
This command selects the operation mode of the CPU (only Z84C01, HD647180). The command may only be executed when the system is down and must be set to the correct operation mode. External mode pins from the target system are not sensed.
Format: SYStem.Clock <option>
<option>: VCOHighMidLow
VCO Variable frequency 1 … 35 MHz.
Low, Mid, High
2.5, 5.0 or 10.0 MHz.
Format: SYStem.CPU <option>
<option>: M0…M3, EXTERN
ICE Emulator for Z80 and Z180 18 ©1989-2019 Lauterbach GmbH
SYStem.Access Dual-port access
Format: SYStem.Access <mode>
<mode>: NodelayREFreshRequestDenied
Nodelay The dual-port access is made between two bus cycles. The max. frequency is 8 MHz on Z80 and Z180 probes.
REFresh The dual-port access is made on CPU refresh cycles. On Z180 probes the refresh function must be switched on. Z80 probes run till 10 MHz and Z180 probes with max. speed if 2 waits for the refresh is specified. 8085 probes do not support this operation mode.
Request This operation allows operation up to the max. speed of the CPU, it runs only on processors with open BUSREQ/BUSACK lines (Not HD647180, HD648180). The CPU speed is slowed down about 1% by dual-port accesses or 5% by refreshing DRAMs as emulation memory.
Denied This mode is available for all types of CPUs. No dual-port access is possible on realtime emulation.
ICE Emulator for Z80 and Z180 19 ©1989-2019 Lauterbach GmbH
General Settings and Restrictions
Restrictions
SYStem.Line BusReq Bus access control
This option allows DMA access without running realtime emulation. External DMA circuits are not stopped on breakpoints.
NMI Routines NMI routines use the IFF1 and IFF2 register. On breakpoint execution there is no distinction between IFF1 and IFF2 register. So the next RETN instruction may set the interrupt flag incorrectly. Running with realtime NMI routines are executed correctly.
Power Down Modes All power down modes which stop the clock generator make fatal emulator errors. On emulation change to an other operation mode.
HALT Realtime emulation may not be stopped if the CPU is in the HALT state. The command Break.Halt activates the breakpoint logic and forces a NMI signal to recover from HALT state.
Trace Internal Registers Write cycles to internal registers are always traced correctly. On read cycles data may be invalid on Z180 and HD64180 probes. The Z181 CPU and the HD647180 enable trace on internal read cycles. On Z181 the ROM emulator mode bit (0ED.1) must be set.
8 Bit I/O When 8-Bit I/O addressing is active (System.Option IO8) it is not possible to map attributes (e.g. intern/extern, wait states) to single I/O locations.
Format: SYStem.Line BusReq [ON | OFF] (Z80)SYStem.Line HOLD [ON | OFF] (8085)
ICE Emulator for Z80 and Z180 20 ©1989-2019 Lauterbach GmbH
SYStem.Option REFresh Trace option
Normally refresh cycles are not traced by the analyzer. On high speed operation with Z80 probes (f > 12.5 MHz) no trace on refresh cycles is allowed as the cycle time of the analyzer must be 150 ns at minimum (ECC8). If activated, the refresh cycles can cause the data selectors to be triggered by refresh cycles, even if the address is not hit by the cycle. To prevent occasionally triggers, address selectors of the trigger unit should be combined with the condition 'N:REFRESH'.
SYStem.Option Wait options
SYStem.Option OMCR OMCR register
The Z180 and Z181 probes must be switched to different internal modes resulting from different bus signals and timings if the OMCR register is changed. The value in this field must be the same value as set by the target software. The CPU is automatically programmed to this pattern on activating the emulation system (SYStem.Up).
Format: SYStem.Option REFresh [ON | OFF]
Format: SYStem.Option <option>
<option>: FAST [ON | OFF]RamWait [ON | OFF]Polarity [ON | OFF]
FAST Must be set to ON with emulation frequency higher than 12 MHz (Z80, Z180).
RamWait This signal generates 1 wait state for all bus cycles that sense the wait input line. As the generation of the wait signal is sometimes very critical in high-speed Z80 systems, this option may help to solve problems with external wait state generators.
PullWait An additional pull-up resistor on the WAIT input line is switched on. Normally needed in standalone mode (Z84C50, Z84C11, Z84C15).
Format: SYStem.Option OMCR <value>
<value>: 0..0FF
ICE Emulator for Z80 and Z180 21 ©1989-2019 Lauterbach GmbH
SYStem.Option DOut Bus control for daisy chain
One big problem in Z80 systems is handling the RETI instruction. This command must be read by the peripherals together with the M1 signal to clear the interrupt daisy chain. No problem occurs if the program is running from the target memory as the data flow is the same like in the system running without emulator. If the program is mapped to internal the peripherals may see other code than the emulation CPU.
In small target systems (no data buffer between CPU and peripherals) the internal code may be send to the data system if DOUT is on. The memory is accessed internal and no memory on the target should block the bus (remove EPROMs).
If a data buffer between CPU and peripherals exists in the target, there are also some possible solutions:
1. Replace the EPROM by a RAM and load the code to the target.
2. Program the RETI instruction to a fixed address in the EPROM on the target and exit every interrupt routine at this location.
3. Use an EPROM simulator to load your program.
4. Some systems use special boot modes to change the data bus direction.
SYStem.Option IO8 Size of I/O space
This option must be set when only 8-bit I/O addresses are used. The option must be set before any memory is mapped or breakpoints are set. Memory attributes, like wait states or protection, are not handled for 8-bit I/O address.
SYStem.Option V33 Voltage sense
The threshold level for the power-down sense is reduced to 2.8 V for operation with 3.3 V targets.
Format: SYStem.Option DOut [ON | OFF]
Format: SYStem.Option IO8 [ON | OFF]
Format: SYStemOption V33 [ON | OFF]
ICE Emulator for Z80 and Z180 22 ©1989-2019 Lauterbach GmbH
Exception Control
The exception control system varies between different processors. The window shown here is for the HD64180 processor.
E::w.xexception Activate Enable Trigger Puls Puls
OFF OFF OFF OFF OFF Single ON RESet ON ON RESet Width
RESet BusReq RESet RESet Int0 1.000usBusReq BusReq Int1 PERiod
NMI NMI Int2 0.000Int0 DREQ1 NMIInt1 PULS BusReq VectorInt2 00 (000.)
ICE Emulator for Z80 and Z180 23 ©1989-2019 Lauterbach GmbH
Schematics
RESET
Format: eXception.Enable RESet [ON | OFF]
Format: eXception.Activate RESet [ON | OFF]
Format: SYStem.M1Out
Format: SYStem.RESetOut
M1Out Z80 PIO may be reset by sending a M1 signal without MRQ/IORQ signals.
RESet Activates RESET line.Enables RESET line.
RESetOUT Forces RESET to target.
RESET (Z80, Z180, Z181)VCC
+1 TRACE
22kRESET-Target
+1-Enable -Puls &1 RESET CPU
-Activate1mA
ResetOut
RESET (8085)
VCC+1 TRACE
22kRESETIN-Target
+1-Enable -Puls &1 RESETIN- CPU
-Activate
RESOUT CPU+1 RESOUT Target
ResetOut
ICE Emulator for Z80 and Z180 24 ©1989-2019 Lauterbach GmbH
BUSREQ Line
Format: eXception.Enable BusReq [ON | OFF]
Format: eXception.Activate BusReq [ON | OFF]
Format: SYStem.Line BusReq [ON | OFF]
Format: eXception.Enable HOLD [ON | OFF]
Format: eXception.Activate HOLD [ON | OFF]
Format: SYStem.Line HOLD [ON | OFF]
BusReq, HOLD
Enables BR line from target.Activates BR, HOLD line.
VCC+1 TRACE
22kBUSREQ-Target
+1-Puls &1 BUSREQ CPU
-Enable M -Activate-Line U
RUN----> X
ICE Emulator for Z80 and Z180 25 ©1989-2019 Lauterbach GmbH
Interrupt Control
Interrupts may be enabled separately for every interrupt input.
eXception.Activate Force exception
Format: eXception.Activate HOLD [ON | OFF]
Format: eXception.Activate RESET [ON | OFF]
Format: eXception.Activate OFF
HOLD Activates the HOLD line.
RESET Activates the $A01$ line.
OFF No activation of any exception line.
INT0,INT1,INT2,NMI input
VCC+1 TRACE
R1INTx-Target
+1-Enable &1 INTx CPU
-Puls
R1 = 22K
ICE Emulator for Z80 and Z180 26 ©1989-2019 Lauterbach GmbH
eXception.Enable Enable exception
The NMI line is not traced directly. A special circuit samples only the falling edge and makes it visible in the next cycles. This allows correct trigger only to edges and not to static levels.
The pulse width of the exception generator defines the length of the interrupt request. As the NMI signal is edge sensitive, only one interrupt is executed.
On INT0 a pulse executes only one interrupt, but if there is no bus cycle within the pulse active time, no interrupt is generated.
Exception vectors are all even values from 0 to 254 (0 to 7 for the 8085). On interrupt stimulation no INTA cycles are made to the target. Therefore stimulated interrupts may run in parallel to interrupts generated by peripherals on the target system.
Format: Exception.Enable NMI [ON | OFF]
Format: Exception.Enable TRAP [ON | OFF]
Format: Exception.Enable Int0 [ON | OFF]
Format: Exception.Enable Int1 [ON | OFF]
Format: Exception.Enable Int2 [ON | OFF]
Format: Exception.Enable RST55 [ON | OFF]
Format: Exception.Enable RST65 [ON | OFF]
Format: Exception.Enable RST75 [ON | OFF]
NMI, TRAP, INTR
Enables NMI from target.
Int0, Int1, Int2 Enables interrupt line from target.
RST55, RST65, RST75
Enables trap line.
Int0, Int1, Int2, INTR, NMI, RST55, RST65
Forces pulse generator to interrupt.
ICE Emulator for Z80 and Z180 27 ©1989-2019 Lauterbach GmbH
eXception.Trigger Trigger on exception
Format: eXception.Trigger BR [ON | OFF]
Format: eXception.Trigger DREQ1 [ON | OFF]
Format: eXception.Trigger HOLD [ON | OFF]
Format: eXception.Trigger NMI [ON | OFF]
Format: eXception.Trigger Pulse [ON | OFF]
Format: eXception.Trigger RES [ON | OFF]
Format: eXception.Trigger TRAP [ON | OFF]
Format: eXception.Trigger OFF
Format: eXception.Trigger ON
BR Trigger on BR line.
DREQ1 Trigger on DREQ1 line.
HOLD Trigger on HOLD line.
NMI Trigger on NMI line.
Pulse Trigger on Pulse line.
RES Trigger on RES line.
TRAP Trigger on TRAP line.
ON Trigger on all exception lines.
OFF No trigger on any exception lines.
ICE Emulator for Z80 and Z180 28 ©1989-2019 Lauterbach GmbH
eXception.Pulse Stimulate exception
eXception.Vector Define vector
Format: eXception.Pulse BR
Format: eXception.Pulse HOLD
Format: eXception.Pulse INTR
Format: eXception.Pulse NMI
Format: eXception.Pulse RES
Format: eXception.Pulse OFF
BR Stimulate BR line.
HOLD Stimulate HOLD line.
INTR Stimulate INTR line.
NMI Stimulate NMI line.
RES Stimulate RES line.
OFF No stimulation on any exception line.
Format: Exception.Vector 0..0FE (Z80)
Vector Defines vector for interrupt simulation.
ICE Emulator for Z80 and Z180 29 ©1989-2019 Lauterbach GmbH
MAP.DMA DMA area
If using the DMA and switching of the M1 signal the emulator cannot distinguish between opfetch cycles and dma read cycles. This may result in fatal errors executing breakpoints. As usually the DMA doesn't access the program area the data area can be marked for the emulator by the mapper. Only DMA memory read areas should be mapped.
Format: MAP.DMA <range>
Format: MAP.NODMA <range>
ICE Emulator for Z80 and Z180 30 ©1989-2019 Lauterbach GmbH
EEPROM Management
The EEPROM of the HD648180 may be initialized with standard set or load commands using the storage class EEPROM:
This function is only available on probes with internal EEPROM.
d.s EEPROM:0B600 2 3 4 5 ; setting bytes
d.s EEPROM:0B600++0x1ff 0x0ff ; clear EEPROM
d.load.b epromdata EEPROM:B600 ; loading data
ICE Emulator for Z80 and Z180 31 ©1989-2019 Lauterbach GmbH
Using the MMU for Banked Target Systems
Banking as described in this chapter refers to address extension of Z80/8085 processors, not the internal MMU of the Z180 family. In banked systems the upper address lines are either supplied internally or by the external bank probe. 8 additional lines offer 256 different memory banks. Accessing the different pages is done by extending all memory and pc addresses to 24 bit. The address bits A16 to A23 select the memory bank. Every command which makes a memory access first calls a special bank driver subroutine to select the temporary memory bank. On realtime emulation the bank number is traced on the upper 8 bits of the address bus. The breakpoints function stores the bank address back to the MSB of the program counter.
SYStem.BankFile Select banking file
This command loads the bank driver. The bank driver is a special subroutine to select the actual bank. Loading a special bank driver gives a maximum of flexibility to the user. A bank address delivered by the emulator may be used to set microcontroller ports or external MMUs in the target system.
The bank file consists of a code number defining the bank operation mode and a code area which consists of a subroutine to set the correct bank state. Writes to internal CPU ports may be executed directly, while ports in target systems must be accessed by a special system call (see end of this chapter). The internal bank address is placed in accu A when calling the subroutine. One return the function must clear A when working on a Z180 with external banking. The write function to the target system needs the address in BC and the data in accu A. The BNK register holds the physical bank number. The PP (Program Pointer) register hold the logical 24-bit PC address. The translation between logical bank and physical bank (also for the common areas and I/O space) is done by the MMU command.
Format: SYStem.BankFile <file>
ICE Emulator for Z80 and Z180 32 ©1989-2019 Lauterbach GmbH
SYStem.Bank Select bank mode
Internal Bank
Internal bank to support paged EPROMs. The internal bank register is set by writing to an address range selected by the command MAP.Bank.
Bank drivers are special subroutines (max. length 256 bytes) to set the bank or an external MMU:
Format: SYStem.Bank <option>
<option>: OFFINTernalEXTernalExtended
; This example uses a common program area on 0--3fffh; a banked area from 4000--7fff with 4 banks
map.resmap.mirror p:0x0--0x03fff p:0x10000map.mirror p:0x0--0x03fff p:0x20000map.mirror p:0x0--0x03fff p:0x30000map.mirror io:0x0--0xffff io:0x10000map.mirror io:0x0--0xffff io:0x20000map.mirror io:0x0--0xffff io:0x30000map.bank 0x4000--0x7fffmmu.onsystem.bankfile banksel.bnksystem.up
; reset mapper; mirror for common area
; set area of banked eprom; activate translation for; addresses; load bank file
org 17FFH
db 1 ; select internal mode
bank: ; accu a is bank address
org 1800h ; destination area in system memory
ld e,0ld hl,1800hcall 100h
ret
; physical bank 0; set hl to banked area; subroutine to write byte to target; system setting the page register; in the EPROM; hl is address, A is date; return
ICE Emulator for Z80 and Z180 33 ©1989-2019 Lauterbach GmbH
External Bank
External banked systems use a register or output pins of the CPU to generate the upper memory addresses. These lines must be feedback to the emulator with the bank probe. Unused inputs of the bank probe must be grounded (or jumpered to ground pin).
This example selects the bank by internal port 45H bit 6 and 7:
Now the bank select is done by an external register selected at A0h:
; This example uses a common program area on 0--3fffh; a banked area from 4000--7fff with 4 banks
map.resmap.mirror p:0x0--0x3fff p:0x10000map.mirror p:0x0--0x3fff p:0x20000map.mirror p:0x0--0x3fff p:0x30000map.mirror io:0x0--0xffff io:0x10000map.mirror io:0x0--0xffff io:0x20000map.mirror io:0x0--0xffff io:0x30000mmu.onsystem.bankfile banksel.bnksystem.up
; reset mapper; mirror for common area
; activate translation for; addresses; load bank file
org 17FFH
db 2 ; select external mode
bank: ; accu a is bank address
org 1800h ; destination area in system memory
push afld bc,45hin a,(c)and 03fhld e,apop afrrcarrcaor eout (c),aret
org 17FFH
db 2 ;select external mode
ICE Emulator for Z80 and Z180 34 ©1989-2019 Lauterbach GmbH
Extended
Extended is used to extend the address space of Z180 CPUs. Up to 16 banks of 1MByte can be used. The bank select routines gets A16..A23 in A and returns the remaining A16..A19 for the CPU address in A. The upper 4 bits are used to specify the 16 banks.
The next examples shows the map and load commands with MMU translation for common ares:
bank: ; accu a is bank address
org 1800h ; destination area in system memory
ld bc,0a0hcall 110H
xor aret
; set BC to banked area; subroutine to write byte to emulation; ram setting bank register; BC is address, A is date; clear BANK (only required for Z180); return
org 17FFH
db 4 ; select extended mode
bank: ; accu a is bank address * 16
org 1800h ; destination area in system memory
push afsra asra asra asra ald bc,0a0hcall 110Hpop afand 0fhret
; shift right; set BC to banked area; subroutine to write byte to emulation; ram setting bank register; A16..A19 will be set by the CPU; return
; This example uses a common program area on 0--7fffh; and a banked area from 8000--ffff with 2 banks; I/O is not banked and uses 8-bit addressing
system.option io8 onsystem.bankfile banksel.bnksystem.mode ai
;load bank file (uses physical; banks)
map.resmap.mirror p:0x0--0x7fff p:0x10000map.mirror io:0x0--0x7fff io:0x10000
; reset mapper; mirror for common area; mirror for I/O accesses
ICE Emulator for Z80 and Z180 35 ©1989-2019 Lauterbach GmbH
Parameters for Banking Program
The following parameters are passed to the banking program:
map.ram p:0--0ffffmap.ram p:18000--1ffffmap.intern
; map memory in banks and common
symbol.resetmmu.resetmmu.create p:00000--07fff p:00000--07fffmmu.create p:08000--0ffff p:08000--0ffffmmu.create p:00000--07fff p:10000--17fffmmu.create p:18000--1ffff p:18000--1ffffmmu.on
d.load.u applic.dbg /nc ; load file from ICCZ80 (IAR)
D Reason for call
0 = Init
1 = Read Memory
2 = Write Memory
3 = Go
4 = Break
A Bank Number
HL Address (PC for Go and Break)
IX Pointer to registers (only Go and Break)
IX+28 = Bank
ICE Emulator for Z80 and Z180 36 ©1989-2019 Lauterbach GmbH
Memory and IO Access Routines
The following routines are available in the emulation control monitor to access external memory or i/o:
Using the MMU for Z180
This command and the commands MMU support the built-in MMU of the Z180 processors.
The analyzer and all memory systems and breakpoints are based on the physical address. The display in the analyzer can be both physical or logical addresses. A logical address can have two formats: smaller than 64K or larger. Smaller addresses are assumed to be an logical address as seen by the CPU in the current
Addr Function Address Data Result
100H MemWrite E-HL A
110H IOWrite BC A
120H MemRead E-HL - A
130H IORead BC - A
ICE Emulator for Z80 and Z180 37 ©1989-2019 Lauterbach GmbH
MMU configuration. If an address is larger than 64K, the address bits A16 to A23 define the bank base address used for the BBR or CBR register. Logical above 64K addresses should only be used, if the MMU registers were already setup. The following schematic shows these relations for some examples:
To activate the correct address translation for breakpoints, the MMU command must be activated. The following example loads a banked application:
mmu.offmap.ram 0x0--0x0fffffmap.immu.ond.load.u iarz180.dbg
preset: CBAR=84, BBR=10, CBR=20
logical address: 5 0 4 5 6 7 (Hex)16 bit
CBR/BBR = 50 logical CPU address
--> physical address: 54567
logical address: 0 0 1 5 6 7 (Hex)16 bit
current-mmu logical CPU address
--> physical address: 1567
logical address: 0 0 4 5 6 7 (Hex)16 bit
current-mmu logical CPU address
--> MMU Bank Area--> physical address: 04567
+BBR 10---=14567
logical address: 0 0 c d e f (Hex)16 bit
current-mmu logical CPU address
--> COMMON1 Area--> physical address: 0cdef
+CBR +20---=2cdef
ICE Emulator for Z80 and Z180 38 ©1989-2019 Lauterbach GmbH
The next example loads a banked application in two logical units:
The MMU translation table is used for translating physical addresses (analyzer, trigger) to logical addresses and logical addresses to physical addresses. The logical to physical translation is done by reading the MMU registers of the CPU and calculating the physical address.
;CBAR=84, CBR=0, BBR=10 or 20
mmu.resetsymbol.resetmap.ram 0x0--0x0fffffmap.immu.create 0x104000--0x107fffmmu.create 0x204000--0x207fffmmu.ond.load.b bank1.cod 0x104000 /nosymbold.load.b bank2.cod 0x204000 /nosymbold.load.b common.cod 0x0 /nosymbold.load.sym bank1.sym /noclearsymbol.reloc p:0x100000 0x4000--0x4fffd.load.sym bank2.sym /noclearsymbol.reloc p:0x200000 0x4000--0x4fffd.load.sym common.sym /noclear
ICE Emulator for Z80 and Z180 39 ©1989-2019 Lauterbach GmbH
Memory Classes
C:, P: and D:
This storage classes operate on the same physically memory. They are only used to be compatible with other emulation probes. CPU internal registers and memory may not be accessed dual-ported, by mapping memory to the same address range data written to the internal memory are also present in the emulation memory.
IO:
The IO address is normally 16 bit. The commands Data.Out and Data.In uses this storage classes on default.
EEPROM:
This storage class is used to program the internal EEPROM. On read cycles there is no difference to the access mode with C: or D:. On write cycles the monitor program executes an EEPROM write protocol.
Access Class Description
C:D:P:AD:AP:IO:
Specify the same address-area (CPU-access) on Z80 family
Absolute (physical) addressing for 64180
IO access
E:ED:EP:EAD:EAP:EIO:
Emulation memory access
Absolute (physical) addressed emulation memory
EEPROM: EEPROM write (HD648180)
d.i 0x34 3 ; read 3 bytes from address 34H
d.o 0x34 55 66 ; sends 2 bytes to address 34H
d.s EEPROM:0E00 " Test "
d.load.b test.bin EEPROM:0e00
ICE Emulator for Z80 and Z180 40 ©1989-2019 Lauterbach GmbH
A:, AD:, AP:
The absolute access storage classes can be used if access to a physical memory location is required. The storage class is only useful on Z180/HD64180 devices.
ICE Emulator for Z80 and Z180 41 ©1989-2019 Lauterbach GmbH
State Analyzer
Keywords for the Trigger Unit
General Keywords for the Trigger Unit
Input Event Meaning Analyzer Hardware
ECC8 HAC HA120 SA120
DATAREAD,MEMRD
Data read access (MEMRDD or MEMRDN)
X X X X
DATAWRITE,MEMWR
Data write access (MEMWRD or MEMWRN)
X X X X
DMA DMA cycle (IORDD or IOWRD or MEMRDD or MEMWRD)
X X X X
FETCH Program fetch cycle(SFETCH or OPFETCH)
X X X X
HALT X X X X
IN, IORD IORDD or IORDN X X X X
INTACK X X X X
IO IORD or IOWR X X X X
IOE, IORQ IO or INTACK X X X X
IORD, IN IORDD or IORDN X X X X
IORDD I/O read by DMA X X X X
IORDN I/O read by CPU X X X X
IORQ, IOE IO or INTACK X X X X
IOWR, OUT IOWRD + IOWRN X X X X
IOWRD I/O write by DMA X X X X
IOWRN I/O write by CPU X X X X
LIR, M1 FETCH or INTACK X X X X
M1, LIR FETCH or INTACK X X X X
ME, MREQ OPMEM or REF X X X X
MEM MEMRD or MEMWR X X X X
MEMIO MEM or IO X X X X
MEMRD Data access read (MEMRDD or MEMRDN)
X X X X
MEMRDD memory read by DMA X X X X
MEMRDN memory read by CPU X X X X
ICE Emulator for Z80 and Z180 42 ©1989-2019 Lauterbach GmbH
MEMWR Data access write (MEMWRD or MEMWRN)
X X X X
MEMWRD memory write by DMA X X X X
MEMWRN memory write by CPU X X X X
MREQ, ME OPMEM or REF X X X X
OPFetch M1 cycle X X X X
OPMEM FETCH or MEM X X X X
OPMEMIO IO or OPMEM X X X X
OUT, IOWR IOWRD or IOWRN X X X X
PORT Input line from port analyzer X X
Read FETCH or IORD or MEMRD X X X X
REF REFESH cycle X X X X
Wait0..Wait6 Waitstates 0..6 X X
WaitX Waitstates greater 6 X X
Write IOWR or MEMWR X X X X
ICE Emulator for Z80 and Z180 43 ©1989-2019 Lauterbach GmbH
Z80/ED/FD/CB Keywords for the Trigger Unit
Z180 Keywords for the Trigger Unit
8085 Keywords for the Trigger Unit
For not CPU-specific keywords, see non-declarable input variables in “ICE/FIRE Analyzer Trigger Unit Programming Guide” (analyzer_prog.pdf).
Input Event Meaning Analyzer hardware
ECC8 HAC HA120 SA120
SFETCH second M1 after switch X X
Input Event Meaning Analyzer hardware
ECC8 HAC HA120 SA120
DREQ1 X X
INT, INT0 X X
INT0..INT2 X X
NMI X X
TEND1 X X
TOUT X X
Input Event Meaning Analyzer hardware
ECC8 HAC HA120 SA120
INTR X X
RST55 X X
RST65 X X
RST75 X X
TRAP NMI signal edge X X
TRAPIN NMI signal X X
ICE Emulator for Z80 and Z180 44 ©1989-2019 Lauterbach GmbH
Keywords for the Display
NMI NMI interrupt (Z80,Z180)
Int0 INT interrupt (Z80,Z180)
Int1 Interrupts (Z180)
Int2
TRAP Interrupt lines (8085)
INTR
RST55,RST65,RST75
TRAPIN
DREQ1 DMA-lines Z180
TEND1
TOUT timer (Z180)
RES
ALE ALE signal (8085)
BR, BA BUS interface lines (Z80,Z180)
HOLD, HLDA BUS interface lines (8085)
SOD, SID (8085)
CKA0 (Z180)
CKA1
CKS
EC 'E' Clock (Z180)
SLEEP sleep occurred before this cycle (Z180)
TXS, RXS Serial interface lines (Z180)
TXA0, RXA0
RTS0, CTS0
TXA1, RXA1
ICE Emulator for Z80 and Z180 45 ©1989-2019 Lauterbach GmbH
Port Analyzer
Keywords for the Port Analyzer (Z180,84C15)
A0 .. A7 Port A
B0 .. B7 Port B
C0 .. C7 Port C
D0 .. D7 Port D
E0 .. E7 Port E
NMI NMI interrupt
Int0 INT interrupt
Int1 Interrupts
Int2
DREQ1 DMA-lines
TEND1
TOUT timer
RES
BR, BA BUS interface lines
CKA0
CKA1
CKS
EC 'E' Clock
SLEEP sleep line
TXS, RXS Serial interface lines
TXA0, RXA0
RTS0, CTS0
TXA1, RXA1
ICE Emulator for Z80 and Z180 46 ©1989-2019 Lauterbach GmbH
Keywords for the Port Analyzer (Z181)
PIA10 .. PIA17 Port 1
PIA20 .. PIA27 Port 2
D6 .. D7 Port D
E0 .. E7 Port E
W W line
SYNC SYNC line
RXD, TXD Communication controller
TRXC, RTXC
DTR, RTS
CTS, DCD
CSRAM, CSROM Chip selects
IEI, IEO Interrupt daisy chain
NMI NMI interrupt
Int0 INT interrupt
Int1 Interrupts
Int2
DREQ1 DMA-lines
TEND1
TOUT timer
RES
ALE ALE signal (8085)
BR, BA BUS interface lines
CKA0
CKA1
CKS
EC 'E' Clock
SLEEP sleep line
TXS, RXS Serial interface lines
ICE Emulator for Z80 and Z180 47 ©1989-2019 Lauterbach GmbH
TXA0, RXA0
RTS0, CTS0
TXA1, RXA1
ICE Emulator for Z80 and Z180 48 ©1989-2019 Lauterbach GmbH
Additional Trace Channels
Not used trace channels on Port-Analyzer are connected to pins placed on the emulation modul.
Module Z80/Z84C00/Z84C01/Z84C50
Module Z180
ICE Emulator for Z80 and Z180 49 ©1989-2019 Lauterbach GmbH
Module 8085
39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 140 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
40 Port.A039 Port.A138 Port.A237 Port.A336 Port.A435 Port.A534 Port.A633 Port.A7
32 Port.B031 Port.B130 Port.B229 Port.B328 Port.B427 Port.B526 Port.B625 Port.B7
24 Port.C023 Port.C122 Port.C221 Port.C320 Port.C419 Port.C518 Port.C617 Port.C7
16 Port.D015 Port.D114 Port.D213 Port.D312 Port.D411 Port.D510 Port.D69 Port.D7
8 Port.E07 Port.E16 Port.E25 Port.E34 Port.E43 Port.E52 Port.E61 Port.E7
ICE Emulator for Z80 and Z180 50 ©1989-2019 Lauterbach GmbH
Module Z181
Module Z84C11
Module Z84C13
Module Z84C15
Module Z80182
9 7 5 3 110 8 6 4 2
1 Port.A02 Port.A13 Port.A24 Port.A35 Port.A46 Port.A57 Port.A68 Port.A79 GND
10 GND
15 13 11 9 7 5 3 116 14 12 10 8 6 4 2
1 Port.A002 Port.A013 Port.A024 Port.A035 Port.A046 Port.A057 Port.A068 Port.A07
9 GND10 GND11 A1812 GND13 A18TO14 +5V15 GND16 GND
ICE Emulator for Z80 and Z180 51 ©1989-2019 Lauterbach GmbH
Module HD648180
15 13 11 9 7 5 3 116 14 12 10 8 6 4 2
1 Port.A02 Port.A13 Port.A24 Port.A35 Port.A46 Port.A57 Port.A68 Port.A7
9 Port.B010 Port.B111 Port.B212 Port.B313 Port.B414 Port.B515 Port.B616 Port.B7
ICE Emulator for Z80 and Z180 52 ©1989-2019 Lauterbach GmbH
Compilers
Language Compiler Company Option Comment
ASM HP-64000-ASM HP Source level debugging
ASM MI-C SYM Source level debugging
ASM AS SDSI SDSC MI-C SYM/LOC No type informationC ICCZ80 IAR Systems AB UBROF Z180 and banking
sup.C MCCZ80 Mentor Graphics
CorporationIEEE no banking support
C HT-Z80 Microchip Technology Inc.
HITECH
C UNIWARE-C SDSI SDSC CC Softools Inc. UBROFPLM ISIS-PL/M Intel Corporation SYM/LOC no type/local info
ICE Emulator for Z80 and Z180 53 ©1989-2019 Lauterbach GmbH
3rd-Party Tool Integration
CPU Tool Company Host
WINDOWS CE PLATF. BUILDER
- Windows
CODE::BLOCKS - -C++TEST - WindowsADENEO -X-TOOLS / X32 blue river software GmbH WindowsCODEWRIGHT Borland Software
CorporationWindows
CODE CONFIDENCE TOOLS
Code Confidence Ltd Windows
CODE CONFIDENCE TOOLS
Code Confidence Ltd Linux
EASYCODE EASYCODE GmbH WindowsECLIPSE Eclipse Foundation, Inc WindowsRHAPSODY IN MICROC IBM Deutschland GmbH WindowsRHAPSODY IN C++ IBM Deutschland GmbH WindowsCHRONVIEW Inchron GmbH WindowsLDRA TOOL SUITE LDRA Technology, Inc. WindowsUML DEBUGGER LieberLieber Software
GmbHWindows
SIMULINK The MathWorks Inc. WindowsATTOL TOOLS MicroMax Inc. WindowsVISUAL BASIC INTERFACE
Microsoft Corporation Windows
LABVIEW NATIONAL INSTRUMENTS Corporation
Windows
TPT PikeTec GmbH WindowsCANTATA QA Systems Ltd WindowsRAPITIME Rapita Systems Ltd. WindowsTESSY Razorcat Development
GmbHWindows
DA-C RistanCASE WindowsTRACEANALYZER Symtavision GmbH WindowsECU-TEST TraceTronic GmbH WindowsUNDODB Undo Software LinuxTA INSPECTOR Vector WindowsVECTORCAST UNIT TESTING
Vector Software Windows
VECTORCAST CODE COVERAGE
Vector Software Windows
ICE Emulator for Z80 and Z180 54 ©1989-2019 Lauterbach GmbH
ICE Emulator for Z80 and Z180 55 ©1989-2019 Lauterbach GmbH
Realtime Operation Systems
Company Product Comment
CMX Systems Inc. CMX-RTXMentor Graphics Corporation
VRTX80
ICE Emulator for Z80 and Z180 56 ©1989-2019 Lauterbach GmbH
Emulation Frequency
The emulation probe is designed for running with CPUs up to 20 MHz. The max. speed is limited by the memory speed and the wait states used for memory access. The CPU type (Z80 or Z180) and some operation options (e.g. Refresh, dual-port access) also affect the max. frequency.
Module CPU F-W0-15
F-W0-35
S-W0-15
S-W0-35
S-W1-15
S-W1-35
DRAM
LA-6665 HD64180R1 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0LA-6665 HD64180Z 15.0+ 15.0 15.0+ 12.6 15.0+ 15.0+ 10.0- HD647180X0 8.0+ 8.0+ 8.0+ 8.0+ 8.0+ 8.0+ 10.0LA-6667 HD648180W 6.0+ 6.0+ 6.0+ 6.0+ 6.0+ 6.0+ 10.0LA-6691 TMP8085 5.0+ 5.0+ 5.0+ 5.0+ 5.0+ 5.0+LA-6661 TMPZ84C00 8.0+ 8.0+ 8.0+ 8.0+ 8.0+ 8.0+ 10.0LA-6661 TMPZ84C013 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0LA-6661 TMPZ84C015 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0LA-6665 Z80180 15.0+ 15.0 15.0+ 12.6 15.0+ 15.0+ 10.0LA-6668 Z80181 12.5+ 12.5+ 12.5+ 12.5+ 12.5+ 12.5+ 10.0LA-6665 Z80182 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0LA-6661 Z8400 8.0+ 8.0+ 8.0+ 8.0+ 8.0+ 8.0+ 10.0LA-6661 Z84013 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0LA-6661 Z84015 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0LA-6661 Z84C00 20.0 13.3 14.5 10.7 20.0+ 20.0+ 10.0LA-6661 Z84C01 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0LA-6661 Z84C13 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0LA-6661 Z84C15 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0LA-6661 Z84C50 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0+ 10.0LA-6665 Z8S180 20.0 15.0 16.0 12.6 20.0+ 20.0+
ICE Emulator for Z80 and Z180 57 ©1989-2019 Lauterbach GmbH
Emulation Modules
Module Overview
Order Information
Order No. Code Text
HD647180X0 PLCC84 3.0..5.5V
TMPZ84C00 DIL40TMPZ84C00 PLCC44
Z8400 DIL40Z8400 PLCC44
Z84C00 DIL40Z84C00 PLCC44
Z84C01 PLCC44
Z84C50 PLCC44
TMPZ84C013 PLCC84
Z84013 PLCC84
Z84C13 PLCC84
LA-6663
TMPZ84C015 ET100-QF06
Z84015 ET100-QF06
Z84C15 ET100-QF06
LA-6664
LA-6661
HD64180R1 PLCC68
HD64180Z DIL64SHD64180Z PLCC68
Z80180 DIL40Z80180 PLCC44
Z8S180 PLCC68
Z80182 ET100-QF06LA-6669
LA-6665
HD648180W PLCC84LA-6667
Z80181 ET100-QF06LA-6668
TMP8085 DIL40LA-6691
LA-6660
ICE Emulator for Z80 and Z180 58 ©1989-2019 Lauterbach GmbH
LA-6945 TC-ICE-M-Z80-F TRACE32 Compact ICE/MPC for Z80 family FastLA-6660 ICE-Z80 ICE-Z80 Base ModuleLA-6661 M-Z80 Module Z80LA-6662 A-Z84C11 Adapter Z84C11LA-6663 A-Z84C13 Adapter Z84C13LA-6664 A-Z84C15 Adapter Z80-Z84C15LA-6665 M-HD64180 Module HD64180-DIL/PLCCLA-6667 M-HD648180 Module for HD648180-PLCCLA-6668 M-Z181 Module Z181LA-6669 A-Z182 Adapter Z182LA-6691 M-8085 Module 8085
Additional OptionsET-1032 ET100-CET-QF06 Clip-Over Adapter for ET100-QF06TO-1260 ET100-ETO-QF06 Emul. Adapter for TO socket ET100-QF06YA-1031 ET100-EYA-QF06 Emul. Adapter for YAMAICHI socket ET100-QF06ET-1030 ET100-SET-QF06 Surface Mountable Adapter for ET100 to QF06TO-1261 ET100-STO-QF06 Emul. Adapter TO-surface mount. ET100-QF06LA-7518 MON-Z80 ROM Monitor for Z80 on ESILA-6450 PA64 Port AnalyzerLA-1925 PLCC-TEST-ADAPTER-44 PLCC Test Adapter 44 PinsLA-1927 PLCC-TEST-ADAPTER-84 PLCC Test Adapter 84 Pins
Order No. Code Text
ICE Emulator for Z80 and Z180 59 ©1989-2019 Lauterbach GmbH
Physical Dimensions
Dimension
LA-6661 M-Z80
cable (400)
66
37
13
13
19
97100103
SIDE VIEW
26
67
9
21
TOP VIEW (all dimensions in mm)
1
1
89
ICE Emulator for Z80 and Z180 60 ©1989-2019 Lauterbach GmbH
LA-6662 A-Z84C11
Dimension
102105
SIDE VIEW
7
10
67
9
14
TOP VIEW (all dimensions in mm)
FemaleConnector
PIN 1
ICE Emulator for Z80 and Z180 61 ©1989-2019 Lauterbach GmbH
LA-6663 A-Z84C13
Dimension
102105
SIDE VIEW
9
10
26
67
13
35
TOP VIEW (all dimensions in mm)
1
ICE Emulator for Z80 and Z180 62 ©1989-2019 Lauterbach GmbH
LA-6664 A-Z84C15
Dimension
102105
SIDE VIEW
7
10
67
14
20
TOP VIEW (all dimensions in mm)
FemaleConnector
PIN 1
ICE Emulator for Z80 and Z180 63 ©1989-2019 Lauterbach GmbH
LA-6665 M-HD64180
Dimension
cable (400)
66
37
13
9
649799103
SIDE VIEW
26
66
8
718
TOP VIEW (all dimensions in mm)
1
7
ICE Emulator for Z80 and Z180 64 ©1989-2019 Lauterbach GmbH
LA-6666 M-HD647180
Dimension
cable (400)
73
37
13
9
4890
107
SIDE VIEW
26
67
17
26
TOP VIEW (all dimensions in mm)
1
ICE Emulator for Z80 and Z180 65 ©1989-2019 Lauterbach GmbH
LA-6667 M-HD648180
Dimension
cable (400)
78
37
13
9
112
116
SIDE VIEW
26
67
16
10
TOP VIEW (all dimensions in mm)
1
ICE Emulator for Z80 and Z180 66 ©1989-2019 Lauterbach GmbH
LA-6668 M-Z181
Dimension
cable (400)
68
37
13
7
102
106
SIDE VIEW
67
10
15
TOP VIEW (all dimensions in mm)
ICE Emulator for Z80 and Z180 67 ©1989-2019 Lauterbach GmbH
LA-6669 A-Z182
Dimension
13
7
97
SIDE VIEW
66
21
13
TOP VIEW (all dimensions in mm)
PIN 1
ICE Emulator for Z80 and Z180 68 ©1989-2019 Lauterbach GmbH
LA-6691 M-8085
Dimension
cable (350)58
37
13
209299
SIDE VIEW
67
8
2
TOP VIEW (all dimensions in mm)
ICE Emulator for Z80 and Z180 69 ©1989-2019 Lauterbach GmbH
LA-6692 M-Z8
Dimension
cable (400)
66
37
13
102105
SIDE VIEW
26
67
11
20
TOP VIEW (all dimensions in mm)
1
312927
ICE Emulator for Z80 and Z180 70 ©1989-2019 Lauterbach GmbH
Adapter
Socket CPU Adapter
ET100-QF06
TMPZ84C015Z80181Z80182Z84015Z84C15
ET-1030 ET100-SET-QF06Surface Mountable Adapter for ET100 to QF06
32
SIDE VIEW
:::::::::::::: :: :::: :::: :::::: :::: :: :: ::
:: :::::: :::: :::: ::
::::::::::::::
4352
TOP VIEW (all dimensions in mm)
ICE Emulator for Z80 and Z180 71 ©1989-2019 Lauterbach GmbH
ET100-QF06
TMPZ84C015Z80181Z80182Z84015Z84C15
YA-1031 ET100-EYA-QF06Emul. Adapter for YAMAICHI socket ET100-QF06
Socket CPU Adapter
6
54
SIDE VIEW
8
56
9
11
TOP VIEW (all dimensions in mm)
1
ICE Emulator for Z80 and Z180 72 ©1989-2019 Lauterbach GmbH
ET100-QF06
TMPZ84C015Z84015Z84C15
ET-1032 ET100-CET-QF06Clip-Over Adapter for ET100-QF06
Socket CPU Adapter
32
SIDE VIEW
:::::::::::::: :: :::: :::: :::::: :::: :: :: ::
:: :::::: :::: :::: ::
::::::::::::::
52
TOP VIEW (all dimensions in mm)
ICE Emulator for Z80 and Z180 73 ©1989-2019 Lauterbach GmbH