ICE Emulator for MC6833X - Lauterbach · 2019-11-06 · ICE Emulator for MC6833X 8 ©1989-2019 Lauterbach GmbH Best-case Setting This target † has no CPU soldered on the board †

ICE Emulator for MC6833X

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TRACE32 Documents ......................................................................................................................

ICE In-Circuit Emulator .................................................................................................................

ICE Target Guides ......................................................................................................................

ICE Emulator for MC6833X ..................................................................................................... 1

WARNING .............................................................................................................................. 6

Quick Start ............................................................................................................................ 7

General Information 7

Best-case Setting 8

Worst-Case Setting 11

Troubleshooting ................................................................................................................... 15

Hang-Up 15

Dualport Errors 16

FAQ ........................................................................................................................................ 17

Basics .................................................................................................................................... 19

Configuration: Address Recovery A19..A31 ...................................................................... 20

Address Recovery by Register Contents 20

SYStem.Option CSBARx Chipselect base address 21

SYStem.Option CSPARx Chip select pin assignment register 21

SYStem.Option PEPAR Port E pin assignment register 21

Address Recovery by PLD Logic 22

Example for PLD Logic 23

Example for PLD logic for 68340/68341 25

Software Based Address Recovery 26

Chip Select Replacement by PLD logic 27

Configuration: Control Lines Recovery ............................................................................. 29

Function Codes have alternate Pin Function 29

Port-E Control Lines Recovery for SCIM Modules 29

Port-E Control Lines Recovery for SIM Modules 30

DTACK Lines have alternate Pin Function 30

AS- has alternate Pin Function 30

DS- has alternate Pin Function 30

SIZ0 and/or SIZ1 have alternate Pin Function 31

ICE Emulator for MC6833X 1 ©1989-2019 Lauterbach GmbH

AS, DS, SIZ0, SIZ1 Port Replacement 31

SYStem.Line AS/DS/SIZ Port replacement 32

SYStem.Option PRBASE Peripheral address 32

Configuration: DIP-Switches ............................................................................................... 33

General SYStem Settings and Restrictions ....................................................................... 34

General Restrictions 34

Emulation Modes 36

SYStem.Access Dualport modes 37

SYStem.Option BASE Peripheral address 37

SYStem.BdmClock BDM clock speed 38

SYStem.Clock Clock modes 38

SYStem.CPU CPU operating mode: 68HC16Y1/68396 only 39

SYStem.Line ADDR Address mask 39

SYStem.Line BKPT External BKPT input 39

SYStem.Option DMA modes 40

SYStem.Option DSACK DSACK mode 40

SYStem.Option FastTerm Fast termination cycles 41

SYStem.Option FCode FCODE pins 41

SYStem.Option LIMITDP Dualport access limitation 41

SYStem.Line/Option MODCLK PLL mode 42

SYStem.Line/Option VCCSYN PLL mode 42

SYStem.Option ONCE On-circuit emulation 42

SYStem.Option RamWait Wait state for memory 43

SYStem.Option ResetMode, ResetExt Reset vector 43

SYStem.Option ShowBreak/ShowTrace Show cycles 43

SYStem.Option ShowBERR Show buserror cycles 44

SYStem.Option Size SIZE pins 44

SYStem.Option STBY Standby voltage 44

SYStem.Option TEST TEST mode 44

SYStem.Option TestClock Clock error check 45

SYStem.Option TraceWait Wait state for memory 45

SYStem.Option VFPEx Flash programming voltage 45

SYStem.Option WDELAY Write strobe delay 45

SYStem.RESetOut Peripheral reset 46

SYStem.TimeDebug Timeout for debug-interface 46

Special Settings 68HC16T3/Z1 ............................................................................................ 47

Special Settings 68HC16X1 ................................................................................................. 47

Special Settings 68HC16Y1 ................................................................................................. 47

Special Settings 68330 ......................................................................................................... 48

Restrictions 68330 48

SYStem.Option PreMap Premapper function 48


Special Settings 68331/332/334/335/336/339/376 ............................................................... 49

SYStem.CPU CPU modes 49

DIP Switches 68336/376 49


Special Settings 68340/341 .................................................................................................. 51

Restrictions 68340/341 51

SYStem.Option PreMap Premapper function 51

SYStem.Option TRANS DMA modes 51

SYStem.Option TRANSRD DMA modes 52


SYStem.Line/Option EPEB0 Flash program enable 53

SYStem.Option VPP Flash programming voltage 53

SYStem.Line/Option FASTREF PLL mode 54


SYStem.Line/Option FASTREF PLL mode 55

Exception Control ................................................................................................................ 56

eXception.Enable Exception control 56

Reset Line 57

HALT Line 59

BERR Line 60

BR Line 61

IRQ Lines (6833x,68HC16) 62

Mapping ................................................................................................................................. 63

MAP.BUS8 Bus width mapping 63

MAP.Onchipp Onchip peripherals 63

Memory Classes ................................................................................................................... 64

State Analyzer ....................................................................................................................... 65

Keywords for the Trigger Unit 65

General Keywords for the Trigger Unit 65

6833X Keywords for the Trigger Unit 66

68340 Keywords for the Trigger Unit 67

68HC16X Keywords for the Trigger Unit 67

68HC16Y Keywords for the Trigger Unit 67

68HC16Z Keywords for the Trigger Unit 68

68HC16ZA Keywords for the Trigger Unit 68

Keywords for the Display 69

Dequeueing 70

Port Analyzer ........................................................................................................................ 71

Keywords for the Port Analyzer 68332 71

Keywords for the Port Analyzer 68340 72


Keywords for the Port Analyzer 68HC16Z1 73

Keywords for the Port Analyzer 68HC16Y1 75

Keywords for the Port Analyzer 68HC16T3 76

Additional Trace Channels (MC68340) 77

Support .................................................................................................................................. 78

Compilers 78

3rd Party Tool Integrations 80

Realtime Operation Systems 81

Emulation Frequency ........................................................................................................... 82

Emulation Modules .............................................................................................................. 83

Module Overview 83

Order Information 84

Operating Voltage ................................................................................................................ 86

Physical Dimensions ........................................................................................................... 87

Adapter .................................................................................................................................. 98


ICE Emulator for MC6833X

Version 06-Nov-2019

For general informations about the In-Circuit Debugger refer to the “ICE User’s Guide” (ice_user.pdf). All general commands are described in “PowerView Command Reference” (ide_ref.pdf) and “General Commands and Functions”.

SP:0017BE \\MCC\mcc\sieve+36 ........... MIX EI

E::w.d.laddr/line code label mnemonic comment

571 flags[ k ] = FALSE;SP:0017BE 4212 clr.b (a2)

572 k += prime;SP:0017C0 D5C4 adda.l d4,a2 ; prime,a2SP:0017C2 D684 add.l d4,d3 ; prime,kSP:0017C4 7012 moveq #12,d0 ; #18,d0SP:0017C6 B083 cmp.l d3,d0 ; k,d0SP:0017C8 6CF4 bge $17BE

E::w.v.chain %r %m ast ast.left E::w.v.ref0x0 (0) (word = 0x0 NULL, flags = (1, 1, 1, 1, 1

count = 12346, k = 3left = 0x5200 (word = 0x0, count = 12, prime = 3right = 0x5600 (word = 0x0, count = 0, i = 0field1 = 1, count = 0field2 = 2), vint = 1

0x1 (1) (word = 0x0 NULL,count = 12,left = 0x5756 (word = 0x0, count = 34,right = 0x5680 (word = 0x0, count = 0,


WARNING

NOTE: Do not connect or remove probe from target while target power is ON.

Power up: Switch on emulator first, then targetPower down: Switch off target first, then emulator


Quick Start

General Information

Before debugging can be started, the emulator must be configured by hardware and software:

1. Check DIP-switch setting (chapter Configuration: DIP-Switches)

2. Create setup file (next)

Ready to run setup files for most standard compilers can be found on the software CD in the directory …/Demo/M68K/Compiler. All setup files are designed to run the emulator stand alone without target hardware.

The following description should make the initial setup (to run the emulator together with the target hardware) easier. It describes a typical setup with frequently used settings. It is recommended to use the programming language PRACTICE to create a batch file, which includes all necessary setup commands. PRACTICE files (*.cmm) can be created with the PRACTICE editor pedit (Command: PEDIT <file name>) or with any other text editor.

A basic setup file includes the following parts:

1. Set system options

2. Select dual port mode (optional)

3. Set mapper (optional)

4. Select frequency (optional)

5. Activate the emulator

6. Load application file (optional)

7. Initialize registers and chipselect units (optional)

8. Set breakpoints (optional)

9. Start application

10. Stop application (optional)

For the first step we will describe an example which requires a minimum of special emulator settings. This is a “best case” setting. Later we will describe a ”worst case” setting.


Best-case Setting

This target

• has no CPU soldered on the board

• uses all address lines A00..23

• uses all function code lines FC0..2

• uses all port E control lines (AS-, DS-, SIZ, DTACK)

• uses BR-, BG- and BGACK- line

• uses a clock generator


The system window controls the CPU specific setup. Please check this window very carefully and set

the appropriate options. Use the button in the main tool bar and click to the option check box (Command: HELP.PICK) to get online help in a pop up window.

2. Select dualport modes (optional)

Dualport allows access to emulation RAM, while emulation is running. This is necessary to display variables, set breakpoints or display the flag listings while the emulation is running. System.access selects how dualport access is done.

system.downsystem.resetsystem.option v33 onsystem.line modclk on

; switch the system down; all system settings to default; on: if 3.3 V module is used; select target clock configuration

system.access request ; request: BR-/BG- line is used; for dualport

?



The mapper controls the memory access of the CPU. This means the use of internal or external memory, the number of wait states, the bus width etc.

4. Select frequency (optional)

The CPU can be clocked by internal (emulator) or external (target). If the internal clock is used, the clock is provides by the VCO of the emulator. The setting of the internal clock is done by the VCO command.

The current CPU frequency can be displayed in the counter window (Command: Count).


When the emulator is activated the Background-Debug-Mode interface of the CPU is initialized. This interface allows access to user memory (data.dump, data.list) and registers and gives control to start and stop the emulation.

6. Load application file (optional)

Application can be loaded by various file formats. For information about the load command for your compiler see Compiler.

map.resetmap.mode fastmap.ram 0x000000--0x0fffffmap.ram 0x300000--0x3fffff

map.intern 0x0000000--0x00fffff

; reset mapper (all external); use fast mode; emulation RAM: use low 1MB; emulation RAM: use top 1MB

; memory: use low 1MB internal; use top 1MB external; use top 1MB for dualport

vco.clock 16.7 ; frequency: set to 16.7 MHz; (necessary if internal clock; used)

system.mode emulext ; system up: emulation external; (target, ext. clock); or: system.mode aloneint; (stand alone, int. clock)

data.load.ieee file.abs /nocode ; load application file; (symbols only)


7. Initialize registers and chipselect units (optional)

For correct data.list and data.dump after RESET it could be necessary to initialize chipselect units. This can be done in the PERipheral window or by data.set commands to the chipselect registers. Stackpointer and program counter should be initialized by hand if debugging is started at RESET until it is initialized by the program. Stack is used for the emulator break system.

8. Set breakpoints (optional)

There are several ways to set breakpoints (Command: Break.Set). Breakpoints can be displayed using the Break.List command. Information regarding HLL lines (for HLL breakpoints) is loaded automatically when a HLL file is loaded.

9. Start application

Application can be started with giving a break address. For example “go main” starts the application and stops at symbol main.

10. Stop application (optional)

Application can be breaked manually by using the Break command. If application executed a halt instruction the command Break.HALT should be used to terminate the application.

It is recommended to check the following chapters for all questions regarding the correct setup:

register.set pc 0x400register.set ssp 0x0fff0

; initialize program counter; initialize stack pointer to; allow; debugging from begin of program

breakpoint.set main /program

breakpoint.set counter /write

; set program break on function; main; set write break on variable; counter

go ; run application

break ; break application by hand


Worst-Case Setting

This target

• has a soldered CPU on the board (clip-over adaption)

• uses all chipselect lines, which means: address lines A19..23, function code lines FC0..2, BR-, BG- and BGACK- lines are not enabled.

• uses port E as port, which means: AS-, SIZ0..1 and DTACK are not enabled

• uses DS- line

• uses PLL clock mode

1. Set Module Hardware configuration

There are some special problems with this target configuration.

- Addresslines A19..23 are disabled, but the address information must be reconstructed for the emulator. Please read: Configuration: Address Recovery A19..A31.

- Except DS- all port-E lines are used as port, but the emulator needs the control line information of AS-, SIZE and DTACK. Please read: Configuration: Control Lines Recovery.

- Because of disabled address- and functioncode-lines some dip-switches on the module must be switched off: Please read: Configuration: DIP_Switches


Initialize system settings:

system.down ;

system.reset ; initialize system settings


Do special system settings:


4. Select dualport modes (optional).

5. Select clock mode (optional)


system.system.option once on ; set target CPU to tristate

system.option size off ; SIZ0,1 not enabled (port E)

system.option dsack off ; DTACK0,1 not enabled (port E)

system.option fcode off ; FCode not enabled (ChipSelect)

system.option showberr on ; toggle emulator window if; BusError detected

system.option wdelay on ; Write strobe delay because of; address reconstruction (GAL on; module)

system.option fastterm on ; Enable for CPU internal or; FastTermination cycles

system.option STBY ON ; power for CPU internal RAM

system.o resetext on ; get reset config from target

map.bus8 0x007d000--0x007efff ; mapping for 8Bit memory areas; because SIZE lines are disabled!

system.access halt ; select halt-dualport-mode.

system.clock 32kHz ; emulator clock for 32 kHz PLL; mode.

system.line MODCLK on ; get target MODCLK config

system.mode emulext ; system up: EmulExt;(target, ext. clock); if the target 32 kHz crystal does; not start to oscillate please use; the emulator 32 kHz clock; use command: system.mode EmulInt; (target, int. clock)


Now the CPU is UP. Before running program some registers must be initialized to be sure the system settings, address-recovery and control-lines-recovery works well.

DTACK- line is disabled so enable the CPU internal Bus-Monitor:

All chip selects must be initialized to be sure the Address-Recovery works well. Write-Only chip-selects should be configured for read/write to allow program download.

data.set sd:0x0fffa00 %w 42cf ; set SCIMCR, enable Bus-Monitor

data.set sd:0x0fffa21 %b 06 ; set SYPCR, enable Bus-Monitor and; disable Watchdog

data.set sd:0x0fffa44 %w 0x3f57 ; ChipSelectPar0

data.set sd:0x0fffa46 %w 0x3b5 ; ChipSelectPar1

data.set sd:0x0fffa48 %w 0x07data.set sd:0x0fffa4a %w 0x78b1

; ChipSelectBoot

data.set sd:0x0fffa4c %w 0x05data.set sd:0x0fffa4e %w 0x7030

; ChipSelect0

data.set sd:0x0fffa50 %w 0x3006data.set sd:0x0fffa52 %w 0x7870

; ChipSelect1

data.set sd:0x0fffa54 %w 0x3806data.set sd:0x0fffa56 %w 0x7870

; ChipSelect2

data.set sd:0x0fffa58 %w 0x1007data.set sd:0x0fffa5a %w 0x78b1

; ChipSelect3

data.set sd:0x0fffa5c %w 0x4005data.set sd:0x0fffa5e %w 0x3c71

; ChipSelect4

data.set sd:0x0fffa60 %w 0x4005data.set sd:0x0fffa62 %w 0x5c71

; ChipSelect5

data.set sd:0x0fffa64 %w 0x0ffd0data.set sd:0x0fffa66 %w 0x7c30

; ChipSelect6

data.set sd:0x0fffa68 %w 0x0fff8data.set sd:0x0fffa6a %w 0x2801

; ChipSelect7

data.set sd:0x0fffa6c %w 0x05000data.set sd:0x0fffa6e %w 0x7c31

; ChipSelect8

data.set sd:0x0fffa70 %w 0x3e04data.set sd:0x0fffa72 %w 0x3c71

; ChipSelect9

data.set sd:0x0fffa74 %w 0x7000data.set sd:0x0fffa76 %w 0x7b71

; ChipSelect10


Configure Port E and F pin-assignment registers

data.set sd:0x0fffa17 %b 0x010 ; Port E config

data.set sd:0x0fffa1f %b 0x0 ; Port F config


Troubleshooting

Hang-Up

If you are not able to stop the emulation, there may be some typically reasons:

Double Address Error

After a double address error the CPU is in halt state. Use the SYStem.Up command to start again. Double address errors normally occur when the stack pointer is out of memory.

No DTACK Signal This condition occurs, if no DTACK signal is generated and the bus monitor is not activated. External accesses may be limited by SYStem.TimeOut. Internal accesses should be limited by the bus monitor. However some bytes between the peripherals are not monitored and force a hang-up of the emulation system. When the DSACK lines of the chip are used as I/O pins the emulator can’t terminate bus cycles. This can lead to an 'debug port timeout' error, when an address range without internal DSACK is accessed. In this case the CPU internal bus monitor should be enabled.- Clear bit FRZBM (Freeze Bus Monitor enable) of register MCR (Module Configuration Register).- Set bit BME (Bus Monitor External enable) of register SYPCR (System Protection Register).

WATCHDOG In 68332/68HC16 type CPUs the watchdog is enabled on RESET. Don't forget to disable the Software Watchdog (SWE) before starting emulation.

Clock error The clock lines between the target and the oscillator replacement are kept as short as possible. But the 32 kHz oscillator circuit has a very high impedance and correct operation with a crystal in the target cannot be guaranteed. Using the internal 32 kHz clock is recommended in this case. Internal clock must be used, when working in ONCE (On-Circuit Emulation) mode.

Low Speed Low clock frequencies may slow down the speed of the serial debugging interface. If debug timeout errors occur, increase the value TimeDebug to 10ms.


Dualport Errors

To realize the dualport access (emulation memory) the BR-line of the CPU is used (Request Mode). If these lines are used as chip selects or i/o, it is possible to make the dualport access by controlling the input clock. This “Clock Steal” mode cannot be used when the chip-internal PLL is active. Dualport accesses by bus request are only allowed while no external request to the bus occurs and the CPU cycle is completed. If the emulation CPU is in RESET state the system controller may always access the emulation memory.

Dualport errors may occur by the following conditions:

1. The length of the CPU cycle is extended by wait cycles, so that the request timeout signal is generated.

2. External DMA requests (single cycles) are too long (Request Mode).

3. The BR, BG or BGACK lines are used as ports or chip selects in

4. Request mode (processors with SCIM require only the BR line).

5. Show cycle control bits in SIM/SCIM are set to '10'.

To solve problems with dualport errors first increase the SYStem.TimeReq value. Be sure that the SYStem.TimeOut value is longer than the access time limit. If it is not possible to solve the problem by changing these values, you must switch to DENIED mode. In this mode no access to memory is possible while running realtime emulation. The internal dualport access can increase the reaction time for external DMA requests. The performance reduction by the dualport access is typically 1% with some data windows (dual ported) on the screen and may be at max. 5% when using dynamic emulation memory.


FAQ

Debugging via VPN

Ref: 0307

The debugger is accessed via Internet/VPN and the performance is very slow. What can be done to improve debug performance?

The main cause for bad debug performance via Internet or VPN are low data throughput and high latency. The ways to improve performance by the debugger are limited:

In PRACTICE scripts, use "SCREEN.OFF" at the beginning of the scriptand "SCREEN.ON" at the end. "SCREEN.OFF" will turn off screenupdates. Please note that if your program stops (e.g. on error) without exe-cuting "SCREEN.OFF", some windows will not be updated.

"SYStem.POLLING SLOW" will set a lower frequency for target statechecks (e.g. power, reset, jtag state). It will take longer for the debugger torecognize that the core stopped on a breakpoint.

"SETUP.URATE 1.s" will set the default update frequency ofData.List/Data.dump/Variable windows to 1 second (the slowest possiblesetting).

Prevent unneeded memory accesses using "MAP.UPDATEONCE<address_range>" for RAM and "MAP.CONST <address_range>" forROM/FLASH. Address ranged with "MAP.UPDATEONCE" will read thespecified address range only once after the core stopped at a breakpoint ormanual break. "MAP.CONST" will read the specified address range onlyonce per SYStem.Mode command (e.g. SYStem.Up).


Target Power Supply Switch

Ref: 0103

Is there a simple way to control target power supply via the ICE to prevent problems after the ICE has been powered off?

Follow the sequence below.

If you own an output probe COUT8, connect it to the STROBE output con-nector.

Type PULSE2. and press F1. You will get the pin out of the output probeCOUT8. Pin 13 (OUT6) delivers +5 V after the emulator has finished its ini-tialization and 0 V if the emulator is powered off. This can be used to drivea relay via a transistor to switch the target power on and off automatically ifthe Pulse Generator is not used for other purposes. The schematic of theswitching unit can be found in the file TARGETC.CMM.

Additionally Pin 13 (OUT6) can be controlled by ICE commands.

Target power supply off. "PULSE2.P +" Target power supply on. "PULSE2.P -"

The following PRACTICE command file creates 3 buttons in the Toolbox for:

Target power on Target power off Target power off and QUIT.

To show the buttons automatically after starting the TRACE32 software, call the script with the DO command from system-settings.cmm in your TRACE32 system directory (create system-settings.cmm if it does not exist).

https://www.lauterbach.com/faq/targetc.cmm

Wrong Location after Break

Ref: 0030

Why is the location after break wrong?

Most emulators use some bytes of user stack for the break system. Therefore it is necessary to have valid stack, if single step or breakpoints are used.

68332

Clip-Over Adaption 68332/68HC16Z

Ref: 0004

Clip-Over Emulation on 68332/68HC16Z?

Clip-Over emulation is possible on 68332, 68HC16Z1 processors. However with some chips the switch-off voltage must be 9 V on the TSC pin. Older ICE-68332 modules must be changed (R932 47K).


https://www.lauterbach.com/faq/targetc.cmm

Basics

The emulation probe supports all Motorola CPUs with 16 bit bus and serial debug interface. A slot for the port analyzer allows tracing all peripheral ports in timing and state mode. A premapper supports full 32 bit mapping in 4 different storage classes.

The emulation system uses the integrated debug interface. Address lines, strobes and FC signals are not buffered to the target. Target system hardware errors may force malfunction of the emulator, but the emulation system is always able to start as the debugging is made via the serial debug interface.

The debugger interface is hardware based to enable fast download and debug control. However the memory access is much slower (ca. 20 KByte/sec.) than on other emulator systems. Download speed may be increased when using dualport access. Some signal lines may not be used in their alternate function. The CLKOUT signal and the AS and DS signals must be available to the emulator system (strobes are always available on processors with SCIM Module).

Using Chip-Select lines instead of address lines to decode the target memory may bring problems for mapping and program trace. This problem can be solved by software address translation or by a GAL circuit. The GAL can translate the Chip-Select signals back to address lines.

If some address lines are used as ports or chip selects, they must be disconnected from the emulation memory to avoid malfunction of the system. A set of switches on the probe disables address and FC lines.

The emulator runs with internal or external clock signals. The emulator system supports a high frequency clock as well as a fixed 32 kHz reference clock for the PLL system on chip.

QFP chips may be emulated on board without desoldering the chip. A special clip-over adapter connects emulator module and target system. The standard adapter shipped with each system is a PGA-like connection, which fits into the footprint of an AMP, or optional 3M/TEXTOOL socket. This connection is very reliable and cheap.

Port E,G,HPort Replacement

AddrFC SIZ CPU

EmulatorBUF

Target Debug Interface


Configuration: Address Recovery A19..A31

If the address lines of the CPU are configured to have no address line functionality (chip select, port), the emulator will still need the missing addresses, to avoid address decoding conflicts. The probe can use three different methods to accomplish this:

Address Recovery by Register Contents

The CPU generates chip selects for the target and an EPLD device translates them back to addresses for the emulation and breakpoint memory.

Some register contents have to be entered to the SYStem window:

- All Chip Select Base Registers (CSBARBT, CSBAR0...10)

- the register base address (07ff000,0fff000)

- all Chip Select Pin Assignment Registers (CSPAR0,1) and

- the Port E Pin Assignment Register.

With this information the emulator 'knows' which address- and chip-select lines are active. In conjunction with the base addresses it reconstructs the missing address lines.

Furthermore it reconstructs missing control lines like AS-, DS-, SIZ0 or SIZ1.

The register base address (SYStem.Option BASE) defines the reconstructed address for CPU internal accesses (register or internal RAM). CPU internal accesses only can be reconstructed if AS- and DS- are active!

Reconstruct Addresses from Chip Selects.

This is the pre-ferred solution!

Method 1:Some modules have special logic to download the chip select base register contents to reconstruct the missing address lines.

Method 2:For some modules a special PLD device has to be programmed by the user to reconstruct the missing address lines from the Chip Selects.

Address recreation by Software

Software based address translation is possible if only chip select CS6..10 are in use.

Generate Chip Selects by PLD

Program the CPU to generate addresses and generate the Chip Selects by an PLD device on the bottom of the Pod.


SYStem.Option CSBARx Chipselect base address

This value has to be set to the actual content of the CPU Chip-Select-Base-Register.

SYStem.Option CSPARx Chip select pin assignment register

This value has to be set to the actual content of the CPU pin-assignment-register.

SYStem.Option PEPAR Port E pin assignment register

This value has to be set to the actual content of the CPU port-e-pin-assignment-register.

Format: SYStem.Option CSBARBT <value>SYStem.Option CSBAR0..10 <value>

Format: SYStem.Option CSPAR0..1 <value>

Format: SYStem.Option PEPAR <value>


Address Recovery by PLD Logic

The CPU generates Chip Selects for the target and a GAL device translates them back to addresses for the emulation and breakpoint memory. The switches on the probe are left open and a PLD device converts the CS lines back to address lines. If the AS or DS pin is used as a port, the AS and DS signals can be regenerated also by this PLD. The option WDELAY must be activated, when DS synchronized chip selects are used.


Example for PLD Logic

GAL20V8/CS0 /CS1 /CS2 /CS3 /CS4 /CS5 /CS6 /CS7 /CS8 /CS9 /CS10 GND/ASIN /DSIN /DSOUT /ASOUT DSDEL A19 A20 A21 A22 A23 /CSBOOT VCC

IF(GND)DSOUT= GND ; set to tristate (close switch)

IF(GND)ASOUT= GND ; set to tristate (close switch)

IF(GND)A19= GND ; set to tristate (close switch)

IF(GND)A20= GND ; set to tristate (close switch)

A21= CS1 ; 200000

+ CS2 ; 300000

+ CS5 ; E00000

+ CS9 ; F00000

+ CS10

+ A21 * DSDEL

A22= CS3 ; C00000

+ CS4 ; D00000

+ CS5 ; E00000

+ CS9 ; F00000

+ CS10 ; F00000

++++++++++++++++++++ CS0- 1CS1- 2

++++++++++++++++++++ CS2- 3 22 A23CS3- 4 21 A22CS4- 5 20 A21

1 CS5- 6 19 A20CS6- 7 18 A19CS7- 8 17 N/C

1 CS8- 9 16 AS-CS9- 10 15 DS-CS10- 11AS- 13 > EmulatorDS- 14

CSBOOT- 23Top view


+ A22 * DSDEL

A23= CS3 ; C00000

+ CS4 ; D00000

+ CS5 ; E00000

+ CS9 ; F00000

+ CS10 ; F00000

+ A23 * DSDEL

DSDEL= DSIN

NOTE: Please use a 20V8-15ns PLD, DIL package. If the analyzer listing does not show the right reconstructed address lines, it might be useful to solder a capacity of 470pF in between pin 12 and pin 17 of the PLD to delay the signal DSDEL. This way all reconstructed address lines will be valid for a longer time after the CSx becomes inactive.


Example for PLD logic for 68340/68341

The CPU produces Chip Selects for the target and a GAL device translates them back to addresses for the emulation and breakpoint memory. The switches on the probe are left open and a PLD device converts the CS lines back to address lines.

GAL16V/CS0 /CS1 /CS2 /CS3 NC0 NC1 NC2 NC3 NC4 GNDNC5 A24 A25 A26 A27 A28 A29 A30 A31 VCC

A24= CS1 ; 1000000

+ CS2 ; 3000000

A25= CS2 ; 300000

+ CS3 ; 6000000

A26= CS3 ; 6000000

…

68341 68340

GAL 16V8

++++++++++++++++++++ CS0-/CS0- 1CS1-/CS1- 2

++++++++++++++++++++ CS2-/CS2- 3 19 A31switch CS3-/CS3- 4 18 A30

a24 ... a31 CS4-/gnd 5 17 A29CS5-/gnd 6 16 A28CS6-/gnd 7 15 A27

1 CS7-/gnd 8 14 A26CPU G gnd 9 13 A25

A gnd 11 12 A24L > Emulator

Top view


Software Based Address Recovery

The switches on the probe are left open and a standard PLD device converts the CS lines to the emulation memory bus and delays the strobes for correct timing. The translation can only be done with CS6 to CS10. The CS lines are used as regular address lines for the emulation memory. The memory must be mapped to the resulting memory address. The MMU command is used to build an translation table between logical address and Chip-Select address (the address that is seen on the bus). The option WDELAY must be activated, when DS synchronized chip selects are used.

The following example uses CS6 and CS7 lines to decode two 16-bit EPROMs:

data.set 0x0fffa48 %w 0x0data.set 0x0fffa4a %w 0x0data.set 0x0fffa64 %w 0x1data.set 0x0fffa66 %w 0x78b0data.set 0x0fffa68 %w 0x21data.set 0x0fffa6a %w 0x78b0data.set 0x0fffa46 %w 0x15f

; disable CSBOOT

; CS6 from 0x0--0x1fff

; CS7 from 0x2000--0x3fff

; enable CS6 and CS7

map.ram 0x100000--0x101ffffmap.ram 0x82000--0x83fffmap.intern

; map for CS6; map for CS7; internal emulation memory

y.resmmu.resmmu.c 0x0--0x1fff 0x100000--0x101fff mmu.c 0x2000--0x3fff 0x82000--0x83fff mmu.on

; CS6 address translation; (CS6=0,CS7=1) => (A19=0,A20=1); CS7 address translation; (CS6=1,CS7=0) => (A19=1,A20=0); activate translation

data.load.i mcc.abs /nil /nc /nmregister.set sp 0x3800register.set pc main


Chip Select Replacement by PLD logic

An other solution to the chip select problem is to program all address pins to their address function and generate the CS-signals by a GAL or PAL on the bottom part of the probe. The Layout of this socket is made in a way, that when using no GAL, inputs and output may be connected by a zero-ohm resistor network. If some lines are not used as chip select signals, the GAL must be programmed to tristate output and inputs and outputs should be connected by a short wire soldered on the GAL. The pin function must be programmed as an address line. The advantage of this solution is the higher possible emulation speed.

++++++++++++++++++++ DS- 1AS- 2

++++++++++++++++++++ FC0 3 22 FC0 CS3-GAL FC1 4 21 FC1 CS4-

FC2 5 20 FC2 CS5-A19 6 19 A19 CS6-

1 A20 7 18 A20 CS7-A21 8 17 A21 CS8-

1 A22 9 16 A22 CS9-A23 10 15 A23 CS10-R/W 11A00 13 OUTSIZ0 14SIZ1 23

Bottom view


; Example for address decoder MC68332

/DS /AS FC0 FC1 FC2 A19 A20 A21 A22 A23 /WRITE GNDA00 SIZ0 /CS10 /CS9 /CS8 /CS7 /CS6 /CS5 /CS4 /CS3 SIZ1 VCC

;------------------------------------------------------------; CS3 Upper F80000H..FFFFFFH

CS3= /A00 * A23 * A22 * A21 * A20 * A19 * AS

;-------------------------------------------------------------; CS4 Lower F80000H..FFFFFFHCS4= A00 * A23 * A22 * A21 * A20 * A19 * AS + /A00 * SIZ1 * A23 * A22 * A21 * A20 * A19 * AS

;-----------------------------------------------------------; CS5 00000H..7FFFFH

CS5= /A23 * /A22 * /A21 * /A20 * /A19 * AS

;-------------------------------------------------------------; CS6 not used

IF(GND)CS6= GND

;-------------------------------------------------------------; CS7 not used

IF(GND)CS7= GND

;-------------------------------------------------------------; CS8 80000H..7FFFFH

CS8= /A23 * /A22 * /A21 * /A20 * A19 * AS

;-------------------------------------------------------------; CS9 Lower 200000H..2FFFFFH

CS9= A00 * /A23 * /A22 * A21 * /A20 * AS + /A00 * SIZ1 * /A23 * /A22 * A21 * /A20 * AS

;------------------------------------------------------------; CS10 Upper 200000H..2FFFFFH

CS10= /A00 * /A23 * /A22 * A21 * /A20 * AS

;------------------------------------------------------------; end


Configuration: Control Lines Recovery

Some control lines of the CPU are required by the emulator. If they are configured for alternate pin functions the information on the pin must still be available to the emulator. There are three different solutions available

Function Codes have alternate Pin Function

When the function code lines have alternate pin function, the DIP-Switches 6, 7 and 8 must be opened and the command SYStem.Option FCode OFF selected. This informs the emulator, that function code lines are not available.

Port-E Control Lines Recovery for SCIM Modules

On probes with integrated port replacement these lines can be used without restriction, as they are driven by the port replacement.

Use CPU internal- oremulator-resources for work around.

• CPU bus monitor for DTACK replacement• MAP.BUS8 for SIZ replacement.

Reconstruct pin-function by hard-ware or PLD logic.

Solution for AS-, DS-, SIZ0, SIZ1.

Generate port func-tion by a port replacement.

Solution for AS-, DS-, SIZ0, SIZ1. Program the CPU to generate control signals and generate the port function by a port replacement on the module.


Port-E Control Lines Recovery for SIM Modules

DTACK Lines have alternate Pin Function

To prevent hang up conditions the CPU internal bus monitor should be enabled.

• Clear bit FRZBM (Freeze Bus Monitor enable) of register MCR (Module Configuration Register)

• Set bit BME (Bus Monitor External enable) of register SYPCR (System Protection Register)

• Set SYStem.Option DTACK to OFF

AS- has alternate Pin Function

Modules which are equipped with the Address recovery by register contents logic automatically will reconstruct the missing AS- functionality. Show cycles will not work with this configuration. The SYStem.Option WDELAY must be set to ON.

For all other modules where the DS- line is available, it can be connected to the AS- line by connecting pins 15 and 16 together on the socket on top of the emulation pod. DIP-Switch #9 must be opened. Show cycles will not work with this configuration. The SYStem.Option WDELAY must be activated.

DS- has alternate Pin Function

Modules which are equipped with the Address recovery by register contents logic automatically will reconstruct the missing DS- functionality. Show cycles will not work with this configuration. The SYStem.Option WDELAY must be set to ON.

For all other modules where the AS- line is available, it can be connected to the DS- line by connecting pins 15 and 16 together on the socket on top of the emulation pod. DIP-Switch #10 must be opened. Show cycles will not work with this configuration. The SYStem.Option WDELAY must be activated.


SIZ0 and/or SIZ1 have alternate Pin Function

When the external memory is either 8 bit or 16 bit read-only memory, the emulator can work without size lines. In this case use the command SYStem.Option SIZE OFF to turn off the size information. The command MAP.BUS8 must be used to mark all 8 bit wide memory areas.

If external 16 bit RAMs have to be supported, the size information is necessary. As the data bus is only 16 bits wide, SIZ1 can be generated from SIZ0 and vice versa.

Modules which are equipped with the Address Recovery by register contents logic automatically will reconstruct the missing SIZ line.

For all other modules:

• To generate SIZ0 from SIZ1 open pin 11 of the AC04 on the pod and connect the pin to pin 12.

• To generate SIZ1 from SIZ0 open pin 13 of the AC04 on the pod and connect the pin to pin 10.

• SIZ0,1 can be generated by a PLD logic from the Chip-Select information. See Address Recovery by PLD logic

AS, DS, SIZ0, SIZ1 Port Replacement

An alternative to reconstruct the strobes and size lines from the Chip-Selects is to use an special port replacement of the emulator. In this case the CPU is programmed to generate the required strobes and the lost I/O ports are replaced by an extra port on the emulation probe.

Following command configure the port replacement:


SYStem.Line AS/DS/SIZ Port replacement

Enable port replacement if Line is switched OFF. The port replacement becomes active if AS, DS, SIZ0 or SIZ1 is switched off in the SYStem window. The port replacement is only active for the switched off lines. When activated, the target line is connected directly to the CPU. When off, the line from the target is connected to a port replacement unit on the probe.

SYStem.Option PRBASE Peripheral address

Defines the base address of the port replacement unit for the AS, DS, SIZ0 and SIZ1 lines.

The address of the port is adjusted by this command. PRBASE must be outside the internal register area and has to be aligned to a 4 KByte boundary. The whole 4 K address range is reserved for the port replacement. The PortDataRegister is located at address PRBASE+1, PRBASE+5 and is mirrored all 4 bytes. The PortDataDirectionRegister is located at address PRBASE+3, PRBASE+7 and is also mirrored to all 4 bytes.

Bit 7 = PE7/SIZ1

Bit 6 = PE6/SIZ0

Bit 5 = PE5/AS-

Bit 4 = PE4/DS-

Care must be taken if DSACK0,1 are switched off! In this case PRBASE must be set to an address where the chipselect logic creates a DTACK! This means the port replacement takes 4 KByte of a chipselect address range which no more can be used as standard RAM or ROM!

Care must be taken if SIZ0,1 are switched off! In this case there might be problems with word or byte accesses to the port replacement. Please try.

In the case of port replacement the processor line is connected to the emulator and the line from the target is connected to the port replacement. The software must be modified to access the address of the port replacement instead of the internal registers of the CPU. There should be mapped an acknowledge (MAP.A PRBASE++0fffh) for the address range of the port replacement if there is no CPU internal generated one. All other port E3..0 bits are still located at their original address in the CPU internal register range.

Format: SYStem.Line AS [ON | OFF]SYStem.Line DS [ON | OFF]SYStem.Line SIZ0 [ON | OFF]SYStem.Line SIZ1 [ON | OFF]

Format: SYStem.Option PRBASE <address>


Configuration: DIP-Switches

Some modules have DIP-Switch on the top of the probe to disconnect address and function code lines which are configured for alternate pin function.

Each address line, which has an alternate pin function, must be switched OFF! The missing address lines can be reconstructed by the Address Recovery by PLD logic method.

All function code lines must be switched OFF if one or more lines have alternate pin function! The SYStem.Option FCode must be set to OFF.

If AS- or DS- is configured for alternate pin function and(!) the missing functionality is reconstructed by a PLD logic the appropriate switch has to be set to OFF. See Control Lines Replacement.

For processors with CPU16 core the (internal) address lines A20 to A23 follow A19. When compilers generate symbols with A20 to A23 set, this logical addresses must be mapped to the lower 1 MBytes physical addresses by a MMU translation:

Switch

12345678

910

CS

CS6CS7CS8CS9CS10CS3CS4CS5

6833x

A19A20 A21A22A23FC0FC1FC2

AS-DS-

68340/41

A24A25A26A27A28A29A30A31

68HC16

A19openopenopenopenFC0FC1FC2

AS-DS-

mmu.create 0x0f80000--0x0ffffff 0x80000--0x0fffffmmu.on


General SYStem Settings and Restrictions

General Restrictions

There are several restrictions when working with ICE-332:

Strobes The AS- and DS-pin should not be used as I/O port. A port replacement is available for the AS and DS lines. The strobes can be recreated also from the chip selects by the GAL on top of the probe. The CLKOUT signal should not be switched off. The analyzer will not work if it is switched off. The SIZ and DTACK pins are not necessary for the emulator function, but if not used the command SYStem.Option SIZE OFF should be set to inform the emulator system. If DTACK pins have other functions, switch off the DTACK option field.

FTERM FTERM cycles are very fast memory cycles, too fast for the synchronous breakpoint system. With frequencies over 17 MHz it is not possible to use FTERM bus cycles and hardware program breakpoints. Zero wait state operation is possible with software breakpoints and fast emulation memory. Fast termination write cycles are not supported by the emulation memory.

Show Cycles Show cycles are very fast memory cycles. At 16.7 MHz they are 120ns wide, which is too fast for the SA120 analyzer, the HA120 analyzer is fast enough. Setting breakpoints to show cycles requires fast breakpoint memory (requirements like for FTERM cycles).

Transparent Mode The 68340 probe doesn't support transparent write modes. The data buffer from CPU is activated on write and blocks the data bus.

DMA Function Code

On DMA cycles (68340) the FC3 bit should always be set to one. Otherwise the program breakpoint system will not work correctly.

Program Access with 8-Bit bus with-out FC lines

The second opfetch (odd byte) cannot be identified as program or data access. The emulator assumes always a program access, to allow program breakpoints. For normal operations this behavior is transparent to the user. The display in the analyzer window will show the correct access class by looking to the context of the access.

Program Execution in Onchip RAM

Program breakpoints and single stepping don't work when executing code in the Standby RAM of the 68332/68HC16.

Synchronous and Asynchronous Breaks (CPU16)

When an asynchronous breakpoint (i.e. stop by trigger) occurs two byte after an active synchronous breakpoint (Program, Spot or Hll) the PC value can be two too less. This is because the CPU16 core gives no information about the reason for entering the BDM state (either BKPT line or BDM instruction).


Byte Access to Pro-gram Memory (CPU16)

The BDM interface on the CPU16 allows only word accesses to the program memory (SP: memory class). Non aligned reads will also include the byte before or after the location and make a word access. Byte writes will perform a read operation and write the modified word to the memory.

Side Effects of PER window

Reading some status registers while single stepping can cause different program behavior. The read of the SCSR register will mark the status bits of this register to be cleared with the next SCDR access.


Emulation Modes

The emulations head can stay in 6 modes. The modes are selected by the SYStem.Up or the SYStem.Mode command.

In active mode, the power of the target is sensed and by switching down the target the emulator changes to RESET mode. The probe is not supplied by the target. When running without target, the target voltage is simulated by an internal pull-up resistor. The command SYStem.Up in Stand-alone doesn't work correctly. Use SYStem.Mode AloneInt to select correct emulation mode.

Format: SYStem.Mode <mode>

<mode>: ResetDown | ResetUpAloneInt | AloneExtEmulInt | EmulExt

Reset Down Target is down, all drivers are in tristate mode.

Reset Up Target has power, drivers are logically in inactive state, but not tristate.

Alone Internal Probe is running with internal clock, DTACK signals are generated by the emulator system.

Alone External Probe is running with external clock, DTACK signals are generated by the emulator.

Emulation Internal Probe is running with internal clock, no DTACK signals are generated.

Emulation External Probe is running with external clock, no DTACK signals are generated.

E::w.syssystem Mode Clock TimeReq Option OptionDown RESet VCO 1.000ms Size TestClock

Up Analyser Low TimeOut FCode ShowBERRMonitor Mid 50.000us ShowTrace DMATRACE

RESet ResetDown High TimeDebug ShowBreak DMATRANSResetUp AUTO 1.000ms RamWait DSACK

reset NoProbe VCO*2 TraceWait TESTRESetOut AloneInt VCO/100 Line FastTerm STBY

AloneExt 32KHZ BusReq ONCEcpu-type EmulInt ClkSteal MODCLK PreMapM68340 EmulExt BKPT ResetExt

16.7 MHz Access Line ADDR ResetModeNodelay FFFFFFFF FF00

ClkSteal Request

Denied


SYStem.Access Dualport modes

SYStem.Option BASE Peripheral address

Defines the base address of the internal peripherals. This value is used by the PER command to display the internal registers.

Furthermore this value defines the address which is reconstructed by the 'Address Recovery by register contents' logic at CPU internal accesses.

Format: SYStem.Access <option>

<option>: RequestClkStealDeniedHalt

Request This is the default method accessing memory in realtime. It works only on if the bus request/bus grant function is enabled. If these pins are changed to alternate function, dualport access will not work correctly. Probes with SCIM Module have an integrated port replacement and require only the BR line.

ClkSteal This method enables dualport accesses by stopping the clock for some cycles. The clock source must be set to clock steal (see Clock Modes) and the internal VCO generates the clock. It is not possible to run this access mode with external clock signals or with 32 kHz clock sources (PLL system active). If dualport access is required and the Request mode cannot be used, the software for the periodic timer and the software watchdog must be modified to use the direct clock input.

Denied No dualport access allowed. On realtime emulation all windows, which need dualport access, are frozen. Breakpoints cannot be set while realtime emulation is running.

Halt This method uses the CPU's HALT pin to get the bus for dualport access. It should be used if Request mode and ClkSteal mode cannot be used.

Format: SYStem.Option BASE <address>


SYStem.BdmClock BDM clock speed

Either the clock frequency divided by 4 or 8 is used as the BDM clock or a fixed clock rate. The fixed clock rate must be used when the operation frequency is very slow or the clock is turned off.

SYStem.Clock Clock modes

Format: SYStem.BdmClock <rate>

<rate>: 4 | 8 | <fixed>

<fixed>: 1000. … 10000000.

Format: SYStem.Clock <option>

<option>: VCOHighMidLowAuto32KHZVCO/100VCO*2ClkSteal

VCO Variable frequency 1 … 35 MHz

Low, Mid, High 2.5, 5.0 or 10.0 MHz

Auto Automatic frequency select in order to the setting on MODCLK field. If MODCLK is low, the VCO is selected (Direct Input). Otherwise the 32 kHz fixed frequency signal is used to support the clock input (PLL reference clock).

32KHZ frequency fixed to 32 kHz.

VCO/100 VCO frequency divided by 100.

VCO*2 Doubled VCO frequency.

ClkSteal VCO Clock for clocksteal dualport mode. See also SYStem.Access.


SYStem.CPU CPU operating mode: 68HC16Y1/68396 only

Selects the operating mode.

Expanded: 16 bit expanded mode, portreplacement switched off

PortE: 16 bit expanded mode, port E portreplacement switched on

8Bit: 8 bit expanded mode, port E,H portreplacements switched on

Single: Single chip mode, port A,B,E,G,H port replacements switched on

SYStem.Line ADDR Address mask

This mask is used for internal dualport access to supply correct address mirrors. Set bits in the mask indicate, that the address bit is used.

SYStem.Line BKPT External BKPT input

Enables the BKPT input from the target to stop emulation asynchronously.

Format: SYStem.CPU <mode>

<mode>: ExpandedPortE8bitSingle

Format: SYStem.Line ADDR <mask>

system.line address 0x000fffffh ; only address lines A0..A19 are used

Format: SYStem.Line BKPT [ON | OFF]


SYStem.Option DMA modes

External DMA circuits and the IDMA circuit on the target CPU work in the same way: both request the main CPU with the BR signal. In realtime emulation the emulation CPU is stopped and the DMA can get control of the bus. When emulation is stopped, no BG signal is generated and the DMA is waiting till realtime emulation is started.

The DMA accesses make also writes to emulation memory. On read access to internal mapped memory the data information is driven to the target system. Be sure that there is no memory to avoid bus conflicts.

SYStem.Option DSACK DSACK mode

Switch ON if the cpu-dtack-line has dtack functionality.

The DTACK lines may be used normally. In this mode WAIT mapping is possible. In the other way the DTACK control system is disabled. The DTACK pins are directly connected to the target system.

See 'Hang-Up conditions'!

Format: SYStem.Line BusReq [ON | OFF]

Format: SYStem.Option DMATRACE [ON | OFF]

Format: SYStem.Option DMATRANS [ON | OFF]

SYStem.Line Bus-Req

This option allows DMA access without running realtime emulation. External DMA circuits are not stopped on breakpoints.

SYStem.Option DMATRACE

DMA cycles may be traced and trigger system is also active on DMA cycles.

SYStem.Option DMATRANS

The DMA accesses make also writes to emulation memory. On read access to internal mapped memory the data information is driven to the target system. Be sure that there is no memory to avoid bus conflicts.

Format: SYStem.Option DSACK [ON | OFF]


SYStem.Option FastTerm Fast termination cycles

This option must be used when the system uses fast termination cycles.

SYStem.Option FCode FCODE pins

Switch OFF if not all CPU function-code lines have function-code functionality.

The FC0..FC2 lines may be used normally or as ports. If the lines are used as ports or chip selects, this option must be turned off and the three switches on the probe must be opened.

SYStem.Option LIMITDP Dualport access limitation

Limit dualport access rate for clock steal mode.

Format: SYStem.Option FastTerm [ON | OFF]

Format: SYStem.Option FCode [ON | OFF]

Format: SYStem.Option LIMITDP [ON | OFF]

ON In clock steal mode the performance reduction is limited to 1%

OFF No limitation on dualport access rate.


SYStem.Line/Option MODCLK PLL mode

Enable pll mode. The MODCLK input line defines if the CLK input is direct or a 32 kHz reference signal for the PLL. If the SYStem.Line is activated, the line will be connected to the target PIN. If the target PIN is connected directly to supply, this line must be switched off, when the clock mode needs to be changed.

The SYStem.Option selects the value supplied by the emulator through an 100 K resistor.

For 68375/68396:

SYStem.Line/Option VCCSYN PLL mode

SYStem.Option ONCE On-circuit emulation

Set to ON when using the Clip-Over-Adapter with QFP-Packages. The CPU chip on the target board is set to tristate on RESET by setting the TSC (TriStateControl) pin to VCC * 1.6. The TSC pin should be connected to VCC via a resistor. If the pin voltage is less than 7 V an error message occurs. An emulation mode with internal clock must be used (EmulInt or AloneInt). For some derivatives this command is not necessary and locked.

Format: SYStem.Option MODCLK [ON | OFF]SYStem.Line MODCLK [ON | OFF]

Format: SYStem.Option VCCSYN [ON | OFF]

Format: SYStem.Option ONCE [ON | OFF]

MODCLK Target <> <> MODCLK CPU

[100-K] < SYStem.Option MODCLK

SYStem.Line MODCLK

MODCLK Target <> 1 <> MODCLK CPUMUX

SYS.Option MODCLK <> 0

SYStem.Line MODCLK


SYStem.Option RamWait Wait state for memory

Inserts one additional wait state in all cycles.

SYStem.Option ResetMode, ResetExt Reset vector

The CPU32/CPU16 processors are checking the data bus on reset in order to set internal registers. In standalone mode or if no option ResetExt is selected, the value of ResetMode defines the state of the data bus when the reset line becomes inactive.

SYStem.Option ShowBreak/ShowTrace Show cycles

Show cycles are CPU access cycles to internal RAM or peripherals. This cycles generate no strobe signals to the external bus, until the bits SHEN0 and SHEN1 in the MCR register are set.

ShowTrace enables the analyzer and trigger features for Show Cycles.

ShowBreak enables the breakpoint memory for Show Cycles.

As show cycles need only 2 clock states either the emulation memory and trace memory must be fast or the clock frequency should not exceed 12.5 MHz. Synchronous PROGRAM breakpoints will not work in internal memory, as there is no access to the CPU bus possible.

Format: SYStem.Option RamWait [ON | OFF]

Format: SYStem.Option ResetMode <vector>

Format: SYStem.Option ResetExt [ON | OFF]

Format: SYStem.Option ShowBreak [ON | OFF]

Format: SYStem.Option ShowTrace [ON | OFF]

NOTE: Don't use the combination 01 if in Request mode (dualport)


SYStem.Option ShowBERR Show buserror cycles

Displays bus errors received when reading memory by the BDM display. The data values will toggle between 0 and 0xff to show a bus error. When turned off, the emulator will report the Bus Error. The feature will work only when the bus monitor of the 683xx SIM Module is not frozen.

SYStem.Option Size SIZE pins

Switch OFF if the CPU SIZE lines have no SIZE functionality!

The SIZE lines may be used normally or as ports. If the lines are used as ports, this option must be turned off. The bus size is then determined by the mapping system (command MAP.BUS8).

SYStem.Option STBY Standby voltage

SYStem.Option TEST TEST mode

Enable CPU test mode.

Format: SYStem.Option ShowBERR [ON | OFF]

Format: SYStem.Option Size [ON | OFF]

Format: SYStem.Option STBY [ON | OFF]

ON The STBY pin is always supplied even if the target power is off.

OFF Internal RAM data are lost if target power is off.

Format: SYStem.Option TEST [ON | OFF]


SYStem.Option TestClock Clock error check

Enable clock error check.

SYStem.Option TraceWait Wait state for memory

One additional wait state is inserted whenever two memory accesses take place back-to-back. This function is necessary in order to ensure that the SA120 analyzer works properly when the minimum time between two cycles is less than150ns (68332 at 20 MHz). Loss in performance is minimal, only a few percent.

SYStem.Option VFPEx Flash programming voltage

Supplies the FLASH programming voltages. The option can be used to program the internal FLASH memories in standalone mode (see also the FLASH command group in the Flash Programming Manual).

SYStem.Option WDELAY Write strobe delay

Delays the write strobe. This option must be used, when addresses or strobes for the emulator are generated by DS synchronized chip selects of the CPU.

Format: SYStem.Option TestClock [ON | OFF]

ON The clock test circuit is active. Clock fails will be detected by the emulator system. The emulator changes to reset state.

OFF No clock check. The EXOFF function (MCR register) may be used, but no trace of program and data is possible.

Format: SYStem.Option TraceWait [ON | OFF]

Format: SYStem.Option VFPE1 [ON | OFF]SYStem.Option VFPE2 [ON | OFF]SYStem.Option VFPE3 [ON | OFF]

Format: SYStem.Option WDELAY [ON | OFF]


SYStem.RESetOut Peripheral reset

In stand-alone mode the user must reset the target CPU by the SYStem.RESetOut command.

SYStem.TimeDebug Timeout for debug-interface

The serial debug interface signals Debug Error if the CPU didn't response within this time.

Format: SYStem.RESetOut

Format: SYStem.TimeDebug <time>

<time>: 1…260.ms


Special Settings 68HC16T3/Z1

Special Settings 68HC16X1

Special Settings 68HC16Y1

Address Lines A19..23

This modules uses the Address Recovery by PLD Logic method to reconstruct disabled address lines. Please have a look to this chapter for additional information.

Port-E Control Lines

This modules requires some port E control lines. Please have a look to Configuration: Port-E Control Lines recovery, especially for SIM modules.

DIP-Switches This modules has DIP-Switches to cut some CPU signals from the emulator bus interface. See DIP-Switches.


This module uses the Address Recovery by register contents method to reconstruct disabled address lines. Please have a look to this chapter for additional information.


Control lines are enabled always. No special setting is needed! See Port-E Control Lines recovery for SCIM modules.







Special Settings 68330

Restrictions 68330

SYStem.Option PreMap Premapper function

Enable premapper. This function is only needed when address lines A24 to A31 are used for addressing memory. Switch OFF if not used to speed-up memory access.


This module does not support address recovery!

Control Lines Control lines are enabled always. No special setting is needed!

DIP-Switches This modules has DIP-Switches to cut address lines A24..31 from the emulator bus interface. See DIP-Switches.

ClockMode JumperSettings

There are two jumpers on the module for VDDSYN and XFC. The setting should be done according to your target requirements.Crystal Mode: VDDSYN--VCC, XFC--NCExt.Clock Mode: VDDSYN--GND, XFC--GNDExt.Clock PLL: VDDSYN--VCC, XFC--NC

MODCK setting is done with the command SYStem.Option MODCK ON/OFF

Format: SYStem.Option PreMap [ON | OFF]

Attention: This option must be switched on before any Map.Pre command is done!


Special Settings 68331/332/334/335/336/339/376

SYStem.CPU CPU modes

Selects the emulated processor type. This function is only required to distinguish pin compatible processors in the same emulation module.

DIP Switches 68336/376

There are dip switches in between the module’s PCBs. Please disconnect the top- from the bottom-PCB and do the following switch setting:




This modules requires some port E control lines. Please have a look to Configuration: Port-E Control Lines recovery, especially for SIM modules.


Format: SYStem.CPU <mode>

<mode>: 6833168332

68336 68376

Switch 1 ON OFF

Switch 2 ON OFF

Switch 3 OFF ON

Switch 4 OFF ON

Switch 5..8 don’t care don’t care






This module requires some port E control lines. Please have a look to Configuration: Port-E Control Lines recovery, especially for SIM modules.


Special Settings 68340/341

Restrictions 68340/341

SYStem.Option PreMap Premapper function

Enable premapper. Is needed when emulating 68330, 68340 or 68341 processors and the address lines A24 to A31 are used for addressing memory or generating chip-select signals. Switch off if not used to speed-up memory access.

SYStem.Option TRANS DMA modes

This option enables Single-Address DMA for Channel 1 and/or 2..



Control Lines Control lines are enabled always. No special setting is needed!

DIP-Switches This modules has DIP-Switches to cut address lines A24..31 from the emulator bus interface. See DIP-Switches.

DMA Modes This CPUs include a DMA controller. The emulator supports Dual-Address DMA without restrictions, without any special system settings needed. Single-Address DMA is just supported for READ DMA!

Format: SYStem.Option PreMap [ON | OFF]

Attention: This option must be switched on before any Map.Pre command is done!

Format: System.Option TRANS1/2 [ON | OFF]


SYStem.Option TRANSRD DMA modes

This option defines the read transfer direction for Single-Address DMA for Channel 1 and/or 2.

If OFF: Target memory --> Emulation mem

If ON: Emulation mem --> Target memory.

Format: System.Option TRANSRD1/2 [ON | OFF]



SYStem.Line/Option EPEB0 Flash program enable

If SYStem.Line is set to ON, the EPEB0 pin will be connected to the target PIN. If the SYStem.Line is set to OFF the SYStem.Option selects the value which is supplied to EPEB0.

SYStem.Option VPP Flash programming voltage

Supplies the FLASH programming voltages. The option can be used to program the internal FLASH memories in standalone mode (see also the FLASH command group in the Flash Programming Manual).






Format: SYStem.Option EPEB0 [ON | OFF]SYStem.Line EPEB0 [ON | OFF]

Format: SYStem.Option VPP [ON | OFF]


SYStem.Line/Option FASTREF PLL mode

The FASTREF input line defines the slow or fast reference PLL mode.

If the SYStem.Line is activated, the line will be connected to the target PIN. If the target PIN is connected directly to supply, this line must be switched off, when PLL mode needs to be changed.


Format: SYStem.Option FASTREF [ON | OFF]SYStem.Line FASTREF [ON | OFF]

FASTREF Target <> <> FASTREF CPU

[4.7-K] < SYStem.Option FASTREF

SYStem.Line FASTREF



SYStem.Line/Option FASTREF PLL mode

The FASTREF input line defines the slow or fast reference PLL mode.

If the SYStem.Line is activated, FASTREF line will be connected to the target PIN. If the target PIN is connected directly to supply, this line must be switched off, when PLL mode needs to be changed.






Format: SYStem.Option FASTREF [ON | OFF]SYStem.Line FASTREF [ON | OFF]

FASTREF Target <> <> FASTREF CPU

[100-K] < SYStem.Option FASTREF

SYStem.Line FASTREF


Exception Control

eXception.Enable Exception control

Format: eXception.Enable ON

Format: eXception.Enable OFF

Format: eXception.Activate OFF

Format: eXception.Enable OFF

Format: eXception.Trigger ON

Format: eXception.Trigger OFF

Format: eXception.Trigger Pulse ON/OFF

Enable ON Enable all exception lines.

Enable OFF Disable all exception lines.

Activate OFF Deactivate all exception lines.

Pulse OFF Disable all pulse exceptions.

Trigger ON Enable trigger on all exception lines.

Trigger OFF Disable trigger on exception lines.

Trigger Pulse Enable trigger on eXception.pulse.

E::w.xexception Activate Enable Trigger Puls Puls

OFF OFF OFF OFF OFF Single ON CpuReset ON ON CpuReset Width

RESet PerReset RESet RESet PerReset 1.000usHalt Halt CpuReset Halt PERiod

BusReq BusReq Halt BusReq 0.000 BusErr BusReq

BusErrPuls


Reset Line

The reset line (input and output) is controlled by a bridge with analog switches and diodes.

Format: SYStem.RESetOut

Format: eXception.Enable Reset [ON | OFF]

Format: eXception.Activate PerReset [ON | OFF]

Format: eXception.Activate CpuReset [ON | OFF]

Format: eXception.Pulse PerReset [ON | OFF]

Format: eXception.Pulse CpuReset [ON | OFF]

Format: eXception.Trigger CpuReset [ON | OFF]

RESET input

VCC VCC

2.7k 2.7kRESET- S2 RESET-Target Emulation CPU

S3S1 S4

GND GND

S1 Reset Target X.Activate PerResetX.Puls PerReset

S2 Reset Out SYStem.RESetOutRunning

S3 Reset In X.Enable Reset

S4 Internal Reset Emulator ControlX.Activate CpuResetX.Puls CpuReset


Enable Reset Enables the Reset line.

Activate PerReset Activates the Target Reset line.

Activate CpuReset Activates the CPU Reset line.

Pulse PerReset Force a pulse to the Target Reset line.

Pulse CpuReset Force a pulse to the CPU Reset line.

Trigger CpuReset Enable trigger on Reset.


HALT Line

Format: eXception.Enable Halt [ON | OFF]

Format: eXception.Activate Halt [ON | OFF]

Format: eXception.Pulse Halt [ON | OFF]

Format: eXception.Trigger Halt [ON | OFF]

Enable Halt Enables HALT line.

Activate Halt Activates the Halt line.

Pulse Halt Force a pulse to the CPU Halt line.

Trigger Halt Enable trigger on Halt.

VCC VCC

2.7k 2.7kHALT- S5 HALT-Target Emulation CPU

S6S7

GND

S5 HALT Out Running

S6 HALT In X.Enable HALT

S7 Internal Halt Emulator ControlX.Activate HALTX.Puls HALT


BERR Line

Format: eXception.Enable BusErr [ON | OFF]

Format: eXception.Trigger BusErr [ON | OFF]

Enable BErr Enables BERR line.

Trigger BErr Enable trigger on BERR.

VCC

22kBERR-Target >=1

X.Enable X.Puls- & BERR- CPUSTART-


BR Line

Format: eXception.Enable BusReq [ON | OFF]

Format: eXception.Activate BusReq [ON | OFF]

Format: eXception.Pulse BusReq [ON | OFF]

Format: eXception.Trigger BusReq [ON | OFF]

Enable BusReq Enables BusRequest line.

Activate BusReq Activates the BusReq line.

Pulse BusReq Force a pulse to the BusReq line.

Trigger BusReq Enable trigger on BusReq.

VCC

22kBR-Target >=1

X.Enable X.Puls- & BR- CPUDualport-


IRQ Lines (6833x,68HC16)

Format: eXception.Enable IRQ1 [ON | OFF]...eXception.Enable IRQ7 [ON | OFF]

Enable IRQ Enables all interrupt lines.

Enable INTx Enables interrupt line.

VCC VCCanalog

100k switch 100kIRQx- IRQx-Target CPU

Enable IRQx


Mapping

MAP.BUS8 Bus width mapping

Every block in the address space of the CPU has either an 8 or 16 bit bus width. The emulator breakpoint and trace system need this information in realtime in order to work correctly. On setting up the emulator system all areas are defined with 16 bit bus width as default.

The MAP.RESet command sets the bus width definition to 16 bit.

MAP.Onchipp Onchip peripherals

To set the bus driver direction correctly when other bus masters are accessing the internal peripherals (SLVEN = 1) the address range of the peripheral area must be mapped.

Format: MAP.BUS8 [<range>]

Format: MAP.NOBUS8 [<range>]

map.bus8 0x0--0x0fffff ; maps first 1 MB block for 8 bit

map.nobus8 ; remaps all to 16 bit

Format: MAP.Onchipp [<range>]

Format: MAP.NoOnchipp [<range>]

map.o 0x0fff000++0x0fff ; maps the upper 4K block for; external master access


Memory Classes

Memory Class Description

FC0 Function-Code 0

FC1 USER-DATA

UD USER-DATA

FC2 USER-PROGRAM

UP USER-PROGRAM

FC3 Function-Code 3

FC4 Function-Code 4

FC5 SUPERVISOR-DATA

SD SUPERVISOR-DATA

FC6 SUPERVISOR-PROGRAM

SP SUPERVISOR-PROGRAM

FC7 Function-Code 7

CPU CPU Function-Code

U User

S Supervisor

D Data

P Program

C Memory access by CPU

E Emulation memory access (can be combined)

A Absolute (physical) memory access (can be combined)


State Analyzer

Keywords for the Trigger Unit

General Keywords for the Trigger Unit

Input Event Meaning Analyzer Hardware

ECC8 HAC HA120 SA120

BYTE Byte transfer X X

CPU, FC7 Interrupt acknowledge X X X

Data Data access (UD or SD) X X X

DMACycle DMA cycle X X

FC0 Function code 0 X X X

FC1,UserData User data area X X X

FC2,UserProgram

User program area X X X



FC5,SupervisorData

Supervisor data area X X X

FC6,SupervisorProgram

Supervisor program area X X X

FC7, CPU Interrupt acknowledge X X X

IACK Interrupt acknowledge(FC7 and Read)

X X X

LONG Double word transfer X X

NMI, IR7 Interrupt request 7 or NMI X X

PORT Input line from port analyzer X X

Program Program access (UP or SP) X X X

Read CPU read cycle X X X

ReadData Data access read (Read and Data)

X X X

Supervisor Supervisor program or data access (SP or SD)

X X X


6833X Keywords for the Trigger Unit

SupervisorData, FC5

Supervisor data area X X X

SupervisorProgram, FC6

Supervisor program area X X X

TimeOut DTACK Timeout X

TRIPLE 3 byte transfer X X

User User program or data access(UP or UD)

X X

UserData, FC1 User data area X X X

UserProgram,FC1

User program area X X X

SIZ0 X X

SIZ1 X X

WORD Word transfer X X

Write CPU write cycle X X X

WriteData Data access write(Write and Data)

X X X



AutoVECtor Reading interrupt vector from table (AVEC line active)

X X

C0..C7 Port C Bit 0..7 X X

CS3..CS10 Chip select 3..10 X X


68340 Keywords for the Trigger Unit

68HC16X Keywords for the Trigger Unit

68HC16Y Keywords for the Trigger Unit



B0..B7 Port B Bit 0..7 X X


DMA DMA cycle from CPU X X

MODCLK X X

IRQ3, IRQ5, IRQ6, IRQ7

Interrupt request 3,5,6,7 X X




X X

CS3,CS5,CS6,CS10

Chip select 3,5,6,10 X X

ECLK X X




X X

CS3,CS5..CS10

Chip select 3,5..10 X X


68HC16Z Keywords for the Trigger Unit

68HC16ZA Keywords for the Trigger Unit

For not CPU-specific keywords, see non-declarable input variables in “ICE/FIRE Analyzer Trigger Unit Programming Guide” (analyzer_prog.pdf).




X X

C3..C6 Port C Bit 3..6 X X





X X



Keywords for the Display

AAddress Absolute (physical) address

WR Write line

DMA DMA cycle between this and last rec.

DMAT Transparent DMA access

IR Interrupt request level

IPL.0 Interrupt request line 0



SIZE Bus transfer size

SIZE.0 SIZ0 signal

SIZE.1 SIZ1 signal

DSACK Bus size

DSACK.0 DSACK0 line

DSACK.1 DSACK1 line

BR Bus request

BG Bus grant

BGACK Bus grant acknowledge

BERR Bus access error

AVEC AVEC line

AS Address strobe line

RMC RMC cycle

HALT Halt cycle

RES Reset cycle

C0..C7 Port C (only 6833x,68HC16)

B0..B7 Port B (only 68340)

Wait Number of inserted wait cycles,

for more than 6 a 'X' appears.


Dequeueing

The disassembled lines in the analyzer are displayed prior to the resulting data cycles. This dequeueing fails for commands which have not a constant number of data cycles.

Problems with prefetches:

• short forward conditional branches to addresses already prefetched


Port Analyzer

Keywords for the Port Analyzer 68332

FC0 FCx lines (or chip selects)

FC1

FC2

A19..A23 Address lines (or chip selects)

BR BusRequest

BG BusGrant

BGACK BusGrantAck

HALT Halt-Line

RESET Reset-Line

AS Address Strobe

BERR BERR-Input

AVEC AVEC line

RMC RMC line

DSACK0 Data Strobe Ack 0

DSACK1 Data Strobe Ack 1

SIZ0 Size Output

SIZ1 Size Output

T2CLK TPU Clock

TP0..TP15 TPU Port 0..15

PCS0..PCS3 Peripheral Chip Select

SCLK Serial Clock

MISO Master In Slave Out

MOSI Master Out Slave In

RXD RX Data

TXD TX Data

MODCLK MODCLK pin

IRQ1..IRQ7 Interrupt Request Lines

BNK0..BNK7 Bank Probe


Keywords for the Port Analyzer 68340

MODCLK MODCLK line

CS1..CS3 Chip selects

IRQ3 Interrupt Request 3




BR Busrequest

BG BusGrant

BGACK BusGrantAck

HALT Halt-Line

RESET Reset-Line

AS Address Strobe

BERR BERR-Input

RMC Read-Modify-Write

DMA DMA lines

DREQ1 DMA Request 1

DACK1 DMA Acknowledge 1

DONE1 DMA Done 1

DREQ2 DMA Request 2

DACK2 DMA Acknowledge 2

DONE2 DMA Done 2

SIO SIO lines

RXDA RX Data A

TXDA TX Data A

CTSA CTS A

TXRDYA TX Ready A

RTSA RTS A

RXDB RX Data B

TXDB TX Data B

CTSB CTS B

TXRDYB TX Ready B

RTSB RTS B

TIMER Timer lines

TGATE1 Timer Gate 1


Keywords for the Port Analyzer 68HC16Z1

TIN1 Timer In 1

TOUT1 Timer Out 1

TGATE2 Timer Gate 2

TIN2 Timer In 2

TOUT2 Timer Out 2

A0 Port A0

IACK1..IACK7 Interrupt Acknowledge Signals

X0..X9 External Trace Inputs


CS All chips selects


BR BusRequest

BG BusGrand

BGACK BusGrantAck

HALT Halt-Line

RESET Reset-Line

AS Address Strobe

BERR BERR-Input

AVEC AVEC line

ICOC Timer Unit lines

IC1..IC4 Input Compare 1..4

OC1..OC4 Output Compare 1..4

ADA Analog/Digital Converter

ADA0..ADA7 Input lines

PCS0..PCS3 Peripheral Chip Selects

SCLK Serial Clock



RXD RX Data

TXD TX Data

MODCLK MODCLK pin



PCLK Clock Input

PAI PAI line

PWMA PWM line

PWMB PWM line

SIZ0 Size Output

SIZ1 Size Output



Keywords for the Port Analyzer 68HC16Y1



BR Busrequest

BG BusGrand

BGACK BusGrantAck

HALT Halt-Line

RESET Reset-Line

AS Address Strobe

BERR BERR-Input

AVEC AVEC line

TPU TPU lines

TP0..TP15

SCLK Serial Clock



RXDA, RXDB RX Data

TXDA, TXDB TX Data

MODCLK MODCLK pin

IRQ1 .. IRQ7 Interrupt Request Lines

DSACK0 DSACK line

DSACK1 DSACK line

SIZ0 Size Output

SIZ1 Size Output



Keywords for the Port Analyzer 68HC16T3



BR Busrequest

BG BusGrand

BGACK BusGrantAck

HALT Halt-Line

RESET Reset-Line

AS Address Strobe

BERR BERR-Input

AVEC AVEC line

TPU TPU lines

TP0..TP15

PCS0..PCS3 Peripheral Chip Selects

SCLK Serial Clock



RXD RX Data

TXD TX Data

FASTREF FASTREF pin


DSACK0 DSACK line

DSACK1 DSACK line

SIZ0 Size line

SIZ1 Size line



Additional Trace Channels (MC68340)

9 7 5 3 110 8 6 4 2

1 Port.X02 Port.X13 Port.X24 Port.X35 Port.X46 Port.X57 Port.X68 Port.X79 Port.X8

10 Port.X9


Support

Compilers

Language Compiler Company Option Comment

ADA ALSYS-ADA IEEE limited support (IEEE)

ADA TELESOFT-ADA Telesoft IEEE limited support (IEEE)

ASM RTOS IEP GmbH SYM/LOC Source level debugging

ASM ASM68K Mentor Graphics Corporation

IEEE Source level debugging

ASM VERSADOS-ASM NXP Semiconductors VERSADOS symbols onlyASM OS-9-ASSEMBLER Radisys Inc. ROF Source level

debuggingASM AS68 TASKING IEEEC HP-64000-C HP no type/locals infoC ORGANON CAD-UL

ElectronicServices GmbH

BOUND

C C68K Cosmic Software COSMICC GNU-C GNU Compiler

CollectionELF/DWARF

C GNU-C GNU Compiler Collection

COFF

C GNU-C GNU Compiler Collection

ELF/DWARF

C GREEN-HILLS-C Greenhills Software Inc. COFFC ICC68K Introl Corporation ICOFFC MCC Mentor Graphics

CorporationIEEE

C HT-68K Microchip Technology Inc.

HITECH

C HICROSS-68K NXP Semiconductors HICROSSC CC68K NXP Semiconductors COFFC ULTRA-C Radisys Inc. ROF OS/9 compilersC OS/9-C Radisys Inc. ROFC CROSSCODE-C SDSI SDSC SCC68K Sierra COFFC SUN3-CC Oracle Corporation DBXC ICC68K TASKING COFFC ICC68K TASKING IEEEC TT-68K TASKING IEEE


C TCC68K TASKING AOUT only source and syms

C TEKTRONIX-C Tektronix COMFORC D-CC Wind River Systems IEEEC D-CC Wind River Systems ELF/DWARFC++ ORGANON-C++ CAD-UL

ElectronicServices GmbH

BOUND

C++ GNU-C++ GNU Compiler Collection

DBX

C++ GNU-C++ GNU Compiler Collection

ELF/DWARF

C++ CCC68K Mentor Graphics Corporation

IEEE

C++ HICROSS-68K NXP Semiconductors HICROSSC++ CODEWARRIOR NXP Semiconductors ELF/DWARFC++ CROSSCODE-C++ SDSI SDSC++ D-C++ Wind River Systems ELF/DWARFMODULA MOD68K Introl Corporation ICOFFMODULA MCS2 Multichannelsystems

GmbHCOFF

MODULA MCDS NXP Semiconductors MCDSPASCAL MPC Mentor Graphics

CorporationIEEE

PEARL RTOS IEP GmbH SYM/LOC no type/locals info


C CX68HC16 Cosmic Software COSMICC ICC6816 IAR Systems AB UBROFC ICC68HC16 Introl Corporation ICOFFC HICROSS-68HC16 NXP Semiconductors HICROSS



3rd Party Tool Integrations

CPU Tool Company Host

WINDOWS CE PLATF. BUILDER

- Windows

CODE::BLOCKS - -C++TEST - WindowsADENEO -X-TOOLS / X32 blue river software GmbH WindowsCODEWRIGHT Borland Software

CorporationWindows

CODE CONFIDENCE TOOLS

Code Confidence Ltd Windows

CODE CONFIDENCE TOOLS

Code Confidence Ltd Linux

EASYCODE EASYCODE GmbH WindowsECLIPSE Eclipse Foundation, Inc WindowsRHAPSODY IN MICROC IBM Deutschland GmbH WindowsRHAPSODY IN C++ IBM Deutschland GmbH WindowsCHRONVIEW Inchron GmbH WindowsLDRA TOOL SUITE LDRA Technology, Inc. WindowsUML DEBUGGER LieberLieber Software

GmbHWindows

SIMULINK The MathWorks Inc. WindowsATTOL TOOLS MicroMax Inc. WindowsVISUAL BASIC INTERFACE

Microsoft Corporation Windows

LABVIEW NATIONAL INSTRUMENTS Corporation

Windows

TPT PikeTec GmbH WindowsCANTATA QA Systems Ltd WindowsRAPITIME Rapita Systems Ltd. WindowsTESSY Razorcat Development

GmbHWindows

DA-C RistanCASE WindowsTRACEANALYZER Symtavision GmbH WindowsECU-TEST TraceTronic GmbH WindowsUNDODB Undo Software LinuxTA INSPECTOR Vector Windows


Realtime Operation Systems

VECTORCAST UNIT TESTING

Vector Software Windows

VECTORCAST CODE COVERAGE

Vector Software Windows

68K OS68 DEBUGGER Enea OSE Systems -68K SDT CMICRO IBM Deutschland GmbH Windows68K DIAB RTA SUITE Wind River Systems Windows

Company Product Comment

PTC AdaWorld ARTKKadakProducts Ltd. AMXOracle Corporation ChorusOSCMX Systems Inc. CMX-RTXSynopsys, Inc MQX 2.40 and 2.50, 3.6

MTOS-UXMentor Graphics Corporation

Nucleus PLUS

Radisys Inc. OS-9Enea OSE Systems OSE Classic (OS68)Enea OSE Systems OSE Delta 4.x and 5.x

RealTime Craft (XEC68k)Quadros Systems Inc. RTXC 3.2IBM Corp. SDT-Cmicro- uCLinux Kernel Version 2.4 and 2.6, 3.xMentor Graphics Corporation

VRTX32

Mentor Graphics Corporation

VRTXmc

Mentor Graphics Corporation

VRTXsa

Wind River Systems VxWorks 5.x and 6.x

CPU Tool Company Host


Emulation Frequency

The emulation probe is designed for running with CPU's up to 25 MHz. The max. speed is limited by the memory speed and the wait states used for memory access.

Module CPU F-W0-15

F-W0-35

S-W0-15

S-W0-35

S-W1-15

S-W1-35

DRAM

LA-6755 MC68376 20.0+ 20.0+ 20.0+ 17.9 20.0+ 20.0+


Emulation Modules

Module Overview

MC68330 ET144-QF63 3.0..3.6VLA-6753

MC68331 ET132-QS03LA-6751

MC68332 ET132-QS03

MC68334 ET132-QS03LA-6752

MC68F333 ET160-QF07LA-6754

MC68336 ET160-QF07

MC68376 ET160-QF07LA-6755

MC68340 PGALA-6760

MC68340 PGA 3.0..3.6VLA-6761

MC68341 ET144-QF63LA-6762

MC68338 ET144-QF63LA-6756

MC68HC16X1 ET100-QF49LA-6773

MC68HC16Z ET132-QS03LA-6770

MC68HC16Y1 ET160-QF07

MC68HC916Y1 ET160-QF07LA-6771

LA-6750


Order Information

Order No. Code Text

LA-6750 ICE-68332 ICE-68332 Base Module

LA-6753 M-MC68330-3.3V Module MC68330 3.3VLA-6751 M-MC68331 Module MC68331LA-6752 M-MC68332 Module MC68332 (331/334/335)LA-6892 ET-68332-144-S ET144-Surface Mountable Adapter for MC68332LA-6893 68332-EYA-144 YAMAICHI-Adapter ET132 to ET144 for MC68332LA-6749 M-MC68332-3.3V Module MC68332 3.3VLA-6754 M-MC68333 Module MC68F333LA-6755 M-MC68336 Module MC68336LA-6763 M-MC68376 Module MC68376LA-6757 M-MC68396 Module MC68396LA-6760 M-MC68340-PGA/QFP Module MC68340 PGA/QFPLA-6761 M-MC68340-PGA-V Module MC68340 PGA 3.3VLA-6762 M-MC68341-QFP Module MC68341LA-6756 M-MC68338 Module MC68338ET-1012 ET-68340-S-CQFP PGA to CQFP 68340 Surface Mountable AdapterET-1013 ET-68340-C 68340 PGA to QFP Clip-Over AdapterET-1014 ET-68340-S-TQFP PGA to TQFP 68340 Surface Mountable Adapter

LA-6773 M-MC68HC16-X1 Module MC68HC16-X1LA-6770 M-MC68HC16-Z1 Module MC68HC16-Z1LA-6774 M-MC68HC16-Z1-3.3V Module MC68HC16-Z1 3.3VET-1016 68HC16Z1-S-PQFP QFP132 to TQFP144 68HC16Z1 Surf. Mount. AdaptLA-6771 M-MC68HC16-Y1 Module MC68HC16-Y1LA-6772 M-MC68HC16-T3 Module MC68HC16-T3

Additional OptionsLA-7710 BDM-68K BDM Debugger for 68K (ICD)LA-7712 BDM-HC16 BDM Debugger for 68HC16 (ICD)ET-1095 ET144-CET-QF10 Clip Over Adapter for ET144-QF10TO-1300 ET144-ETO-QF10 Emul. Adapter for T0 socket ET144-QF10YA-1094 ET144-EYA-QF10 Emul. Adapter for YAMAICHI socket ET144-QF10YA-1111 ET144-EYA-QF63 Emul. Adapter for YAMAICHI socket ET144-QF63ET-1090 ET144-SET-QF10 Surface Mountable Adapter for ET144-QF10TO-1301 ET144-STO-QF10 Emul. Adapter TO-surface mount. ET144-QF10ET-1062 ET160-CET-QF07 Clip-Over Adapter for ET160-QF07TO-1320 ET160-ETO-QF07 Emul. Adapter for T0 socket ET160-QF07YA-1061 ET160-EYA-QF07 Emul. Adapter for YAMAICHI socket ET160-QF07LA-1064 ET160-FP160-L Adapter for Footprint AMP/3M socketsLA-1063 ET160-FP160-R Adapter for Footprint AMP/3M socketsET-1060 ET160-SET-QF07 Surface Mountable Adapter for ET160-QF07


TO-1321 ET160-STO-QF07 Emul. Adapter TO-surface mount. ET160-QF07LA-7510 MON-68K ROM Monitor for 68K on ESILA-6450 PA64 Port AnalyzerLA-2812L SIMULATOR-68K-FL 1 User Float. Lic. TRACE32 68K SimulatorYA-1159 YA-SOCKET-QF63 YAMAICHI Socket ET144-QF63

Order No. Code Text


Operating Voltage

No other voltage ranges available !


Physical Dimensions

Dimension

LA-6753 M-MC68330-3.3V

cable (350)

71

37

13

9

96107

SIDE VIEW

74

18

9

TOP VIEW (all dimensions in mm)

PIN 1


LA-6751 M-MC68331LA-6752 M-MC68332LA-6749 M-MC68332-3.3VLA-6770 M-MC68HC16-Z1LA-6774 M-MC68HC16-Z1-3.3V

LA-6892 ET-68332-144-S

Dimension

cable (350)

76

37

13

7

102112

SIDE VIEW

Female Connectors

74

11

8


1


LA-6893 68332-EYA-144

Dimension

1717

69

6 10

13

9

SIDE VIEW

1

7

7

17

17

TOP VIEW


LA-6754 M-MC68333LA-6755 M-MC68336LA-6763 M-MC68376

Dimension

cable (400)

75

37

13

7

102

112

SIDE VIEW

(333)

Female connectors76

7

6


1


LA-6760 M-MC68340-PGA/QFPLA-6761 M-MC68340-PGA-V

Dimension

cable (350)67

68340

37

13

9

PGA

92103

SIDE VIEW

A1

76

20

9

PGA144

TOP VIEW (all dimension in mm)


LA-6762 M-MC68341-QFP

Dimension

cable (400)

66

38

14

92102

SIDE VIEW

7

77


PIN 1

1314


LA-6756 M-MC68338

Dimension

cable

83

37

13

7

108

118

SIDE VIEW

78

7

5


1


ET-1012 ET-68340-S-CQFP

ET-1013 ET-68340-C

ET-1014 ET-68340-S-TQFP

Dimension

20

SIDE VIEW

..........::::::::::::: :::

::: ::::::....:::::::::::::


SIDE VIEW

..........::::::::::::: :::

::: ::::::....:::::::::::::



LA-6758 M-MC68375

LA-6764 BGA217-AI-68375

LA-6759 M-MC68371

LA-6773 M-MC68HC16-X1

ET-1016 68HC16Z1-S-PQFP

Dimension

cable (400)

86

37

13

7

112

122

SIDE VIEW

79

8

6


PIN 1


LA-6771 M-MC68HC16-Y1

LA-6772 M-MC68HC16-T3

Dimension

cable (400)

76

68HC16Y1

37

13

7

102

112

SIDE VIEW

Female connectors 74

6

7


PIN 1


LA-6757 M-MC68396

Dimension

cable

86

37

13

7

111

122

SIDE VIEW

79

8

7


1


Adapter

Socket CPU Adapter

ET160-QF07

MC68376

ET-1060 ET160-SET-QF07Surface Mountable Adapter for ET160-QF07

ET160-QF07

MC68376

YA-1061 ET160-EYA-QF07Emul. Adapter for YAMAICHI socket ET160-QF07

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:: :::: :::: :::: :: ::::::::::::::


6

66

SIDE VIEW

8

66

11

11



ET160-QF07

MC68376

ET-1062 ET160-CET-QF07Clip-Over Adapter for ET160-QF07

Socket CPU Adapter

900

250

2400

2800100

11

ALL DIMENSIONS IN1/1000 INCH

ET160-QF07 CLIP


ET160-QF07

MC68376

LA-1063 ET160-FP160-RAdapter for Footprint AMP/3M sockets

Socket CPU Adapter

9

66

SIDE VIEW

8

66

13

13


TARGET


ET160-QF07

MC68376

LA-1064 ET160-FP160-LAdapter for Footprint AMP/3M sockets

Socket CPU Adapter

9

66

SIDE VIEW

8

66

13

13


TARGET
