RF Signal Processor for CD Players

DescriptionThe CXA2581N is an RF signal processing IC for

compact disc players.

Features• Wide band RF signal processing• RF system VCA circuit• RF system equalizer (supports CAV mode)• Supports pickups with built-in RF summing

amplifier• Low current consumption mode (EQ Pass mode)• RW/ROM switching mode• Center error amplifier• Output DC level shift circuit• TE balance adjustment function

Functions• RF AC summing amplifier, equalizer, VCA• RF DC summing amplifier• Focus error amplifier• Tracking error amplifier• Center error amplifier• Automatic power control• VC buffer amplifier (analog block, digital block)

Absolute Maximum Ratings• Supply voltage VCC 7 V• Storage temperature Tstg –65 to +150 °C• Allowable power dissipation

PD 620 mW

Operating Conditions• Operating supply voltage range

VCC – GND 3.4 to 5.5 V(0V ≤ Vcc – DVcc < 2V)

Note) Care should be taken for the operating voltage. See page 18.

• Operating temperature Topr –30 to +85 °C

– 1 –E98739B06-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license byany implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating theoperation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXA2581N

30 pin SSOP (Plastic)

Pin Configuration

1 2 3 4 5 6 7 9 1211

20 192224252627282930

8 10 1413

18 172123

15

16

LD PD

EQ

_IN

AC

_SU

M

GN

D A B D

SWFC E

DV

C

DV

CC

RF

AC

DC

_OF

ST

RF

DC

I

RF

DC

O

VC

RF

C

VF

C

BS

T

VC

C

TE

_BA

L

CE

RF

G

CE

I

FE

I

TE

FE

– 2 –

CXA2581N

Block Diagram

DVCC

ACSUM

APC

ACVCA

EQ

VC

VC

VC

RW/ROM

EQ_ON/OFF

VOFST DVC

DVCC

RW/ROM

VCRW/ROM

RW/ROM

RW/ROM

VC

DVCC

25

15

30

29

28

17

16

26242334

6

7

8

9

10

19

18

DVC

DVCCDVC

VC

VC

VOFST

DVC

DVC

VCC

VOFST

B

C

A

D

A

B

C

D

F

E

SW

PD

LD

VC

C

GN

D

VC

DV

C

DVCC

CE

CEI

TE

TE_BAL

FE

FEI

RFDCO

RFDCI

RFAC

VF

C

RF

C

RF

G

BS

T

EQ

_IN

AC

_SU

M

DC_OFST

VCRW/ROM

21

145

20

13VC

VCC

APC-OFF (Hi-Z)RW/ROM(H/L)

2722

1

2

12

11

gm

gm

RW/ROM

VOFST

– 3 –

CXA2581N

Pin Description

Pin No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

LD

PD

EQ_IN

AC_SUM

GND

A

B

C

D

E

F

SW

DVCC

DVC

RFAC

FE

FEI

TE

TE_BAL

CE

CEI

VCC

RFG

BST

VFC

RFC

VC

RFDCO

RFDCI

DC_OFST

APC amplifier output.

APC amplifier input.

RFAC system VCA block and EQ block input.

RFAC system RF SUM output.

GND.

A signal input.

B signal input.

C signal input.

D signal input.

E signal input.

F signal input.

Mode switching signal input.

DVCC.

DVC output.

RFAC signal output.

Focus error signal output.

FE amplifier virtual ground.

Tracking error signal output.

TE balance adjustment.

Center error signal output.

CE amplifier virtual ground.

VCC.

RFAC system VCA block low frequency gain adjustment.

EQ boost level adjustment.

EQ cut-off frequency adjustment.

EQ cut-off frequency adjustment.

VC voltage output.

RFDC signal output.

RFDC amplifier virtual ground.

RFDC signal output offset adjustment.

O

I

I

O

I

I

I

I

I

I

I

I

I

O

O

O

I

O

I

O

I

I

I

I

I

I

O

O

I

I

Symbol I/O Description

– 4 –

CXA2581N

Pin Description

Pin No.

Symbol I/O Equivalent circuit Description

110k

1k

2

55k20k

20k

3 1.2k

1.1k

VC

1.1k

5k5k

VC

1.6k1.6k

4

1

2

3

4

O

I

I

O

LD

PD

EQ_IN

AC_SUM

5 GND

APC amplifier output.

APC amplifier input.

Equalizer circuit input.

RFAC summing amplifieroutput.

— — GND.

– 5 –

CXA2581N

Pin No.

Symbol I/O Equivalent circuit Description

47k

VC

47k

15k

30k

100µA

100µA

100µA

6

100µA7

8

9

10

11

VC

200k

200k

200k12

VC

14150k

150k 25

6 IA

7 IB

8 IC

9 ID

RF summing amplifier andfocus error amplifier input.

10 IE

Tracking error amplifier input.

11 IF

12 ISWCD-ROM/RW switching input.RW when connected to VCC,ROM when connected to GND.

14 ODVC(DVCC + GND)/2 voltageoutput.

13 — —DVCC Digital power supply.

– 6 –

CXA2581N

Pin No.

Symbol I/O Equivalent circuit Description

151002mA

15 ORFAC RFAC amplifier output.

17 IFEI

Focus error amplifier gainadjustment. The gain isadjusted by the externalresistance value connectedbetween this pin and Pin 16.

50k 124

VC16

12417

16 OFE Focus error amplifier output.

19 ITE_BALTracking error E and F gainbalance adjustment.

20k18

19

20k

20k

VC

18 OTE Tracking error amplifier output.

21 ICEI

Center error amplifier gainadjustment.The gain is adjusted by theexternal resistance valueconnected between this pinand Pin 20.

50k 124

VC20

12421

20 OCE Center error amplifier output.

– 7 –

CXA2581N

22 — —VCC VCC. (AVCC)

Pin No.

Symbol I/O Equivalent circuit Description

20k

VC23

100µA

50µA

20k

VC24

20k

VC25

100µA

1241.0V

26

27150k

150k 25

23 IRFGSets the RFAC low frequencygain.

24 IBSTInput for adjusting theequalizer circuit boost level.

25 IVFC

Input for adjusting theequalizer circuit boostfrequency with the controlvoltage.

26 IRFC

Input for adjusting theequalizer circuit boostfrequency with externalresistance.

27 OVC (VCC + GND)/2 voltageoutput.

– 8 –

CXA2581N

Pin No.

Symbol I/O Equivalent circuit Description

VC

2k

124

1mA

28

29

124

VC

10k

124

24k

15k

30

28 ORFDC RFDC amplifier output.

29 IRFDCI

RFDC amplifier gainadjustment.The gain is adjusted by theexternal resistance valueconnected between this pinand Pin 28.

30 IDC_OFST RFDC amplifier offset control.

– 9 –

CXA2581N

Description of Functions

• RFAC

The RF signal input by connecting capacitance to the EQ_IN pin is equalized, arithmetically amplified and then

output from the RFAC pin.

ACSUM

EQ

RW/ROMBST = VCC

6

7

8

9

A

B

C

D

RFG

EQ_IN

AC_SUM

RF

262524

VFC

RFC

5.1k

BST

VCC

4

3

23

15 RFACAmp

0.1µ

The EQ can be bypassed by connecting the BST control pin (Pin 24) to VCC.

In this case only the EQ block enters sleep mode and low power consumption mode (slim mode) is activated.

The low frequency gain is the same value as for EQ ON mode.

If RF (summing signal) is present at the pickup output pin, input the addition output signal to EQ_IN (Pin 3)

coupled by capacitance.

When using a pickup without a summing output function, perform addition with the AC SUM block and then

input the signal to EQ_IN (Pin 3) coupled by capacitance.

RW/ROM switching is done by the VCA block, so either input method can be used without problem.

The RW gain is 12dB higher than the ROM gain.

Low frequency gainAC_SUM: 13dB (both ROM/RW)VCA to RFAC ROM: 0dB

RW: 12dB

VC – 1 VC VC + 1

Vcnt[V]

8

0

–8

Gain [dB]VCA variable range

The VCA low frequency gain can be adjusted by the RFG

(Pin 23) voltage.

The control voltage vs. low frequency gain characteristics

are shown in the graph to the right.

The RFAC pin (Pin 15) is an NPN transistor emitter follower output.

The maximum drive current is approximately 2mA.

If the load capacitance distorts the output waveform, connect resistance between Pin 15 and GND to increase

the drive current.

– 10 –

CXA2581N

• EQ

VCC VC

EQ CNT

RFC

LPFLPF

HPF Amp

VC

26 VFC

fc

In

BoostOut

25 BST 24

The diagram to the left shows the EQ internal blockdiagram.The EQ consists of a combination of HPF and LPF.The HPF and LPF transmittance is the Bessel function.The boost gain can be adjusted by adjusting the HPFgain.The boost frequency is adjusted by the RFC externalresistance value and the VFC control voltage value.

RFC resistance value: The cut-off frequency fo of eachfilter is adjusted by the Pin 26external resistance value.The VFC voltage can be variedusing this fo as the reference.

VFC voltage: fo can be changed by the voltage appliedto Pin 25.

The boost gain can be adjusted by the BST pin controlvoltage.The control characteristics are shown in the graph below.

The cut-off frequency control characteristics areshown in the graph below.

VC – 1.0 VC

Pin 24 (BST) voltage

VC + 1.0

Vcnt[V]

8dB

0dB

Boost Gain [dB]

VC – 1.0 VC

Pin 25 (VFC) voltage

VC + 1.0

Vcnt[V]

1.5fo

fo

0.5fo

fc [Hz]

• APC (Automatic Power Control)

When the laser diode is driven by a constant current, the optical power output has extremely large negativetemperature characteristics. Therefore, the current must be controlled to maintain the monitor photo diodeoutput at a constant level. This control is performed by the APC function.

2PD1 LD

10k55k

10k

1.25V

56k

56k

VCC

10k1k

– 11 –

CXA2581N

• Focus Error

The signals input to the A and C pins and the B and D pins are arithmetically amplified and the focus errorsignal is output.This circuit has RW/ROM switching and offset addition functions.

VC

RW

100k23.5k

30k

ROM

A

DVC

VOFST

6

FEI 17 FE16

30kC 8

30kB

30k

47k

200k

47k

50k

100k

200k

7

D

ROM

RW

ROM

RW

9

124124

FE = Gain (B + D) – (A + C) Low frequency gain ROM: 16dB

RW: 28dB

Cut-off frequency fc (typ.) ROM: 300kHzRW: 300kHz

• Tracking Error

The signals input to the E and F pins are arithmetically amplified and the tracking error signal is output.This circuit has RW/ROM switching and offset addition functions.

DVCC

ROM RW

10

18

DVC

F VC

VOFSTROM

RW

VC

ETE

TE_BAL

11

gm

gm

19

20k20k

20k

10k

10k

31.5k 125.5k

20k

63k

251k

63k ROM

RW251k

TE = Gain (F – E)

Low frequency gain ROM: 16dBRW: 28dB

TE balance adjustmentF – E low frequency gain = ±6dB

External resistance value vs. Low frequency gain

Resistance value [Ω]10k

22

16

12.5

20k 30k

Low frequencygain [dB]

– 12 –

CXA2581N

• VC Buffer

This outputs the VC ((1/2) VCC) voltage.

The maximum output current is approximately ±3mA.

Use this voltage as the analog block VC voltage.

• DVC Buffer

This outputs the 1/2 DVCC voltage.

The maximum output current is approximately ±3mA.

Use this voltage as the digital block VC voltage.

The output DC voltage of each block is level shifted

using the DVC voltage as the reference.

2725

VC

40k

40k

VCC

1425

DVC

40k

40k

DVCC

• RFDC

The signals input to the A, B, C and D pins are added, amplified and the RFDC signal is output. RW/ROM

switching and low frequency gain adjustment are possible.

VC

RW

96k24k

15k

ROM

A

VCVC

6

30

RFDCI 29 RFDCO2815kB 7

15kC

15k

2.4k

3.3k

10k

2k

5.1k

40k8

D

ROM

RW

ROM

RW9

124124

RFDC = Gain (A + B + C + D)Low frequency gain ROM: 17.5dB

RW: 29.5dBfc (Typ) ROM: 20MHz

RW: 5MHzThe gain can be adjusted by the external resistance connected between Pins 28 and 29.The output voltage offset can be adjusted by controlling the Pin 30 voltage.

– 13 –

CXA2581N

• Center Error

The signals input to the A and D pins and the B and C pins are arithmetically amplified and the center errorsignal is output.RW/ROM switching, low frequency gain adjustment and offset adjustment are possible.

VC

RW

48k12k

30k

ROM

A

DVC

VOFST

6CEI 21 CE20

30kD 9

30kB

30k

24k

96k

24k

50k

200k

96k

7

C

ROM

RW

ROM

RW

8

The (B + C) – (A + D) signal is arithmetically amplified.Low frequency gain ROM: 16dB

RW: 28dB

Cut-off frequency fc (typ.)ROM: 200kHzRW: 200kHz

• Output Offset Shift

The RFDC, FE, TE and CE output DC voltages are level shifted to the digital VC voltage (DVC).The reference voltage of this IC is the VC voltage, and only the output reference voltage changes.The maximum output voltage of each output signal should be kept to the digital VCC voltage (DVCC) or less inorder to protect the DSP_IC.

DVCVOFST

40k

40k

VC

VC

40k40k

The VC and DVC voltages are arithmetically amplified andoutput as the VOFST voltage.The VOFST voltage serves as the level shift referencevoltage, and is distributed to each block.

• SW

This controls the laser (APC) on/off, active/sleep mode, and RW/ROM mode switching.Switching is controlled by the voltage applied to the SW pin.

12 SWSW RW/ROM

Active/Sleep

APC_ON/OFF

The VC buffer is always in active mode even if it enters sleep mode.In the function block, MODE_SW is always set to active mode.

ItemControl voltage

VCC

VC or Hi-Z

GND

ON

OFF

ON

Active

Sleep

Active

RW

—

ROM

APC Active/Sleep RW/ROM

SW high/low condition

High: VC + 1V to Vcc

Low: VC – 1V to GND

– 14 –

CXA2581N

Mea

sure

-m

ent N

o.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Curre

nt co

nsum

ption

(Acti

ve, E

Q On

)

Curre

nt co

nsum

ption

(Acti

ve, E

Q Of

f)

Curre

nt co

nsum

ption

(DVC

C)

Curre

nt co

nsum

ption

(Slee

p)

SU

M o

ffset

vol

tage

SU

M lo

w fr

eque

ncy

gain

SU

M fr

eque

ncy

resp

onse

SUM

max

imum

out

put v

olta

ge H

SUM

max

imum

out

put v

olta

ge L

Offs

et v

olta

ge R

OM

Offs

et v

olta

ge R

W

Low

frequ

ency

gai

n RO

M_m

in

Low

frequ

ency

gai

n RO

M_c

nt

Low

frequ

ency

gai

n RO

M_m

ax

Low

freq

uenc

y ga

in R

W_m

in

Low

freq

uenc

y ga

in R

W_c

nt

Low

freq

uenc

y ga

in R

W_m

ax

Low

freq

uenc

y ga

in E

Q_o

ff

Freq

uenc

y re

spon

se M

in_L

Freq

uenc

y re

spon

se M

in_H

Freq

uenc

y re

spon

se E

Q_O

FF

Max

imum

out

put v

olta

ge H

Max

imum

out

put v

olta

ge L

Icc_

Aeqo

n

Icc_

Aeqo

ff

Icc_

Dvcc

Icc_

Slp

ACSU

M_Of

st

Gsu

m

Fsum

Vsum

_H

Vsum

_L

AC_O

fstRO

M

AC_O

fstRW

Gac

_RO

M1

Gac

_RO

M2

Gac

_RO

M3

Gac

_RW

1

Gac

_RW

2

Gac

_RW

3

Gac

_EQ

off

Fac_

Min

L

Fac_

Min

H

Fac_

EQof

f

Vac_

H

Vac_

L

O O O O O O O O O O O O

O O

O O O O

O O O O

O O O O

O O O O

Hi-Z O O O O

0.1V

p-p

0.1V

p-p

1.4V

p-p

0.8V

p-p

0.3V

p-p

0.35

Vp-p

0.2V

p-p

75m

Vp-p

0.8V

p-p

0.3V

p-p

0.3V

p-p

0.3V

p-p

100k

Hz

10M

Hz

100k

Hz

100k

Hz

100k

Hz

50kH

z

50kH

z

50kH

z

100k

Hz

10M

Hz

30M

Hz

20M

Hz

0V 70m

V

70m

V

0.4V

–0.4

V

0V 1.2V

–1.2

V

0V0V –1.0

V

0V 1.0V

–1.0

V

0V 1.0V 0V

0V 1.7V 0V 1.7V 0V 1.7V 0V

0V –1.0

V

1.0V 0V

0V22 22 13 22 4 4 4 4 4 15 15 15 15 15 15 15 15 15 15 15 15 15 15

Pin

cur

rent

Pin

cur

rent

Pin

cur

rent

Pin

cur

rent

Pin

vol

tage

20 lo

g (V

out/V

in)

20 lo

g (V

out/V

in)–

Gsu

m

Pin

volta

ge –

ACSU

M_O

fst

Pin

volta

ge –

ACSU

M_O

fst

Pin

vol

tage

Pin

vol

tage

20 lo

g (Vo

ut/Vin

) – G

ac_R

OM2

20 lo

g (Vo

ut/Vin

)

20 lo

g (Vo

ut/Vin

) – G

ac_R

OM2

20 log

(Vout

/Vin) –

Gac_R

W2– G

ac_RO

M2

20 lo

g (Vo

ut/Vin

) – G

ac_R

OM2

20 log

(Vout

/Vin) –

Gac_R

W2– G

ac_RO

M2

20 lo

g (Vo

ut/Vin

)

20 lo

g (Vo

ut/Vin

) – G

ac_R

OM2

20 lo

g (Vo

ut/Vin

) – G

ac_R

OM2

20 lo

g (Vo

ut/Vin

) – E

Qoff

Pin

volta

ge –

AC_

Ofs

tRO

M

Pin

volta

ge –

AC_

Ofs

tRO

M

30 15 0.2 3

–1.2

11 –2.5

1.4

–0.5

–0.8

–0.8

–11

–3 5 –11 9 5 –2 2 2

–0.5

0.8

–1.1

50 30 0.5 5

–0.7

13 –0.5

1.6

–0.3

–0.3

–0.3 –8 0 8 –8 12 8 0 5 5 2.5 1

–0.9

70 45 0.8 8

–0.2

15 0.5

1.7

–0.1

0.2

0.2

–5 3 11 –5 15 11 2 8 8 5.5

1.2

–0.7

mA

mA

mA

mA V dB dB V V V V dB dB dB dB dB dB dB dB dB dB V V

Func

-

tion

Mea

sure

men

t ite

mS

ymbo

lS

witc

h co

nditi

ons

Bia

s co

nditi

ons

S1S2

S3S4

S5S6

S7S8

S9S1

0S1

1S1

2V

1am

plitu

deV1

frequ

ency

E1

E2

E3

E4

E5

E6

0VE7

Mea

sure

-

men

t pin

Mea

sure

men

t

cond

ition

sM

in.

Typ.

Max

.Uni

t

RFAC SUM RFAC EQ

Ele

ctri

cal C

har

acte

rist

ics

(VC

C=

1.7

V, V

EE

= –

1.7V

, DV

CC

= 1

.7V

, DV

EE

= –

1.7V

)

– 15 –

CXA2581N

Mea

sure

-m

ent N

o.

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Offs

et v

olta

ge R

OM

Offs

et v

olta

ge R

W

Low

freq

uenc

y ga

in R

OM

Low

freq

uenc

y ga

in R

W

Freq

uenc

y re

spon

se R

OM

Freq

uenc

y re

spon

se R

W

Max

imum

out

put v

olta

ge H

Max

imum

out

put v

olta

ge L

Offs

et v

olta

ge 1

Offs

et v

olta

ge R

OM

Offs

et v

olta

ge R

W

Low

freq

uenc

y ga

in R

OM

1

Low

freq

uenc

y ga

in R

OM

2

Low

freq

uenc

y ga

in R

W1

Low

freq

uenc

y ga

in R

W2

Freq

uenc

y re

spon

se R

OM

1

Freq

uenc

y re

spon

se R

OM

2

Freq

uenc

y re

spon

se R

W1

Freq

uenc

y re

spon

se R

W2

Max

imum

out

put v

olta

ge H

Max

imum

out

put v

olta

ge L

DC_O

fstRO

M

DC_O

fstRW

Gdc

_RO

M

Gdc

_RW

Fdc_

ROM

Fdc_

RW

Vdc_

H

Vdc_

L

DC_O

fst1

FE_O

fstRO

M

FE_O

fstRW

Gfe

_RO

M1

Gfe

_RO

M2

Gfe

_RW

1

Gfe

_RW

2

Ffe_

ROM

1

Ffe_

ROM

2

Ffe_

RW1

Ffe_

RW2

Vfe_

H

Vfe_

L

O O O O O O O O O O O

O O O O O O O O O O O

O O O O O O O O O O O

O O O O O O O O O O O

O O O O O O O O

50m

Vp-p

12.5

mVp

-p

50m

Vp-p

12.5

mVp

-p

0.1V

p-p

0.1V

p-p

25m

Vp-p

25m

Vp-p

0.1V

p-p

0.1V

p-p

25m

Vp-p

25m

Vp-p

100k

Hz

100k

Hz

20M

Hz

5MH

z

1kH

z

1kH

z

1kH

z

1kH

z

300k

Hz

300k

Hz

300k

Hz

300k

Hz

0V 0.3V

–0.3

V

0V 0.3V

0.3V

0V0V

0V0V

0V –0.5

V

0V

28 28 28 28 28 28 28 28 28 16 16 16 16 16 16 16 16 16 16 16 16

Pin

vol

tage

Pin

vol

tage

20 lo

g (Vo

ut/Vin

)

20 lo

g (Vo

ut/Vin

) – G

dc_R

OM

20 lo

g (Vo

ut/Vin

) – G

dc_R

OM

20 log

(Vout

/Vin) –

Gdc_R

W – G

dc_RO

M

Pin

vol

tage

Pin

vol

tage

Pin

vol

tage

Pin

vol

tage

Pin

vol

tage

20 lo

g (Vo

ut/Vin

)

20 lo

g (Vo

ut/Vin

)

20 lo

g (Vo

ut/Vin

) – G

fe_RO

M1

20 lo

g (Vo

ut/Vin

) – G

fe_RO

M2

20 lo

g (Vo

ut/Vin

) – G

fe_RO

M1

20 lo

g (Vo

ut/Vin

) – G

fe_RO

M2

20 log

(Vout

/Vin) –

Gfe_R

W1– G

fe_RO

M1

20 log

(Vout

/Vin) –

Gfe_R

W2– G

fe_RO

M2

Pin

vol

tage

Pin

vol

tage

–150

–150

14.5

10 –3.5

–4.5

0.6

–1.7

–0.7

–150

–150

12.5

12.5

10 10 –5.5

–5.5

–5.5

–5.5

1.3

–1.7

0 0

17.5

12 –0.5

–1.5

0.8

–1.5

–0.6 0 0

15.5

15.5

12 12 –2.5

–2.5

–2.5

–2.5

1.5

–1.5

150

150

20.5

14 0.5

–0.5 1

–1.3

–0.5

150

150

18.5

18.5

14 14 0.5

0.5

0.5

0.5

1.7

–1.3

mV

mV

dB dB dB dB V V V mV

mV

dB dB dB dB dB dB dB dB V V

Func

-

tion

Mea

sure

men

t ite

mS

ymbo

lS

witc

h co

nditi

ons

Bia

s co

nditi

ons

S1S2

S3S4

S5S6

S7S8

S9S1

0S1

1S1

2V

1am

plitu

deV1

frequ

ency

E1

E2

E3

E4

E5

E6

0VE7

Mea

sure

-

men

t pin

Mea

sure

men

t

cond

ition

sM

in.

Typ.

Max

.Uni

t

RFDC FE

– 16 –

CXA2581N

Mea

sure

-m

ent N

o.

45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Offs

et v

olta

ge R

OM

Offs

et v

olta

ge R

W

Low

freq

uenc

y ga

in R

OM

1

Low

freq

uenc

y ga

in R

OM

2

Low

freq

uenc

y ga

in R

W1

Low

freq

uenc

y ga

in R

W2

Freq

uenc

y re

spon

se R

OM

1

Freq

uenc

y re

spon

se R

OM

2

Freq

uenc

y re

spon

se R

W1

Freq

uenc

y re

spon

se R

W2

Bal

ance

gai

n 1

Bal

ance

gai

n 2

Max

imum

out

put v

olta

ge H

Max

imum

out

put v

olta

ge L

Offs

et v

olta

ge R

OM

Offs

et v

olta

ge R

W

Low

freq

uenc

y ga

in R

OM

1

Low

freq

uenc

y ga

in R

OM

2

Low

freq

uenc

y ga

in R

W1

Low

freq

uenc

y ga

in R

W2

Freq

uenc

y re

spon

se R

OM

1

Freq

uenc

y re

spon

se R

OM

2

Freq

uenc

y re

spon

se R

W1

Freq

uenc

y re

spon

se R

W2

Max

imum

out

put v

olta

ge H

Max

imum

out

put v

olta

ge L

TE_O

fstRO

M

TE_O

fstRW

Gte

_RO

M1

Gte

_RO

M2

Gte

_RW

1

Gte

_RW

2

Fte_

ROM

1

Fte_

ROM

2

Fte_

RW1

Fte_

RW2

Gte

1

Gte

2

Vte_

H

Vte_

L

CE_O

fstRO

M

CE_O

fstRW

Gce

_RO

M1

Gce

_RO

M2

Gce

_RW

1

Gce

_RW

2

Fce_

ROM

1

Fce_

ROM

2

Fce_

RW1

Fce_

RW2

Vce_

H

Vce_

L

O O O O O

O O O O O

O O O O O

O O O O O

O O O O O O O

O O O O O O O

O O O O O O O O O O

0.1V

p-p

0.1V

p-p

25m

Vp-p

25m

Vp-p

0.1V

p-p

0.1V

p-p

25m

Vp-p

25m

Vp-p

0.1V

p-p

0.1V

p-p

0.1V

p-p

0.1V

p-p

25m

Vp-p

25m

Vp-p

0.1V

p-p

0.1V

p-p

25m

Vp-p

25m

Vp-p

1kH

z

1kH

z

1kH

z

1kH

z

100k

Hz

100k

Hz

100k

Hz

100k

Hz

1kH

z

1kH

z

1kH

z

1kH

z

1kH

z

1kH

z

200k

Hz

200k

Hz

200k

Hz

200k

Hz

0V 0.6V

0.6V 0V 0.5V

0.5V

0V0V

0V0V

0V18 18 18 18 18 18 18 18 18 18 18 18 18 18 20 20 20 20 20 20 20 20 20 20 20 20

Pin

vol

tage

Pin

vol

tage

20 lo

g (Vo

ut/Vin

)

20 lo

g (Vo

ut/Vin

)

20 lo

g (Vo

ut/Vin

) – G

te_RO

M1

20 lo

g (Vo

ut/Vin

) – G

te_RO

M2

20 lo

g (Vo

ut/Vin

) – G

te_RO

M1

20 lo

g (Vo

ut/Vin

) – G

te_RO

M2

20 log

(Vout

/Vin) –

Gte_R

W1– G

te_RO

M1

20 log

(Vout

/Vin) –

Gte_R

W2– G

te_RO

M2

E, F

gai

n di

ffere

nce

E, F

gai

n di

ffere

nce

Pin

vol

tage

Pin

vol

tage

Pin

vol

tage

Pin

vol

tage

20 lo

g (Vo

ut/Vin

)

20 lo

g (Vo

ut/Vin

)

20 lo

g (Vo

ut/Vin

) – G

ce_R

OM1

20 lo

g (Vo

ut/Vin

) – G

ce_R

OM2

20 lo

g (Vo

ut/Vin

) – G

ce_R

OM1

20 lo

g (Vo

ut/Vin

) – G

ce_R

OM2

20 log

(Vout

/Vin) –

Gce_R

W1– G

ce_RO

M1

20 log

(Vout

/Vin) –

Gce_R

W2– G

ce_RO

M2

Pin

vol

tage

Pin

vol

tage

–200

–500 13 13 10 10 –3.2

–3.2

–3.5

–3.5 4 –8 1.3

–1.7

–150

–150

12.5

12.5

10 10 –3.8

–3.8

–3.8

–3.8

1.15

–1.7

0 0 16 16 12 12 –1.2

–1.2

–1.5

–1.5 6 –6 1.5

–1.5 0 0

15.5

15.5

12 12 –2.3

–2.3

–2.3

–2.3

1.35

– 1.5

200

500

19 19 14 14 0.8

0.8

0.5

0.5 8 –4 1.7

–1.3

150

150

18.5

18.5

14 14 –0.8

–0.8

–0.8

–0.8

1.55

–1.3

mV

mV

dB dB dB dB dB dB dB dB dB dB V V mV

mV

dB dB dB dB dB dB dB dB V V

Func

-

tion

Mea

sure

men

t ite

mS

ymbo

lS

witc

h co

nditi

ons

Bia

s co

nditi

ons

S1S2

S3S4

S5S6

S7S8

S9S1

0S1

1S1

2V

1am

plitu

deV1

frequ

ency

E1

E2

E3

E4

E5

E6

0V 1.0V

–1.0

V

0VE7

Mea

sure

-

men

t pin

Mea

sure

men

t

cond

ition

sM

in.

Typ.

Max

.Uni

t

TE CE

– 17 –

CXA2581N

Mea

sure

-m

ent N

o.

71 72 73 74 75 76 77

Out

put v

olta

ge 1

Out

put v

olta

ge 2

Out

put v

olta

ge 3

AP

C O

FF v

olta

ge

Max

imum

out

put c

urre

nt

Out

put v

olta

ge

Out

put v

olta

ge

Vap

c1

Vap

c2

Vap

c3

Vap

c_of

f

Iapc

_max

Vav

c

Vdv

c

O

O O O O O

Hi-Z

O

0V0V 0V

0V0V

0V0V

1, 2 1 1 1 1 27 14

Inpu

t at w

hich

outp

ut vo

ltage

= 0

V

Pin

vol

tage

Pin

vol

tage

Pin

vol

tage

Pin

vol

tage

Pin

vol

tage

Pin

vol

tage

0 0.5

–1 1.4

–0.5

5

–100

–100

150

0.75

–0.7

5

1.6

–0.1

5

0 0

300 1

–0.5

1.7

0.25

100

100

mV V V V V mV

mV

Func

-

tion

Mea

sure

men

t ite

mS

ymbo

lS

witc

h co

nditi

ons

Bia

s co

nditi

ons

S1S2

S3S4

S5S6

S7S8

S9S1

0S1

1S1

2V

1am

plitu

deV1

frequ

ency

E1

E2

E3

E4

E5

E6

0VE7

Mea

sure

-

men

t pin

Mea

sure

men

t

cond

ition

sM

in.

Typ.

Max

.Uni

t

Vapc

1 +

20m

V

Vapc

1 –

20m

V

APC AVC DVC

– 18 –

CXA2581N

1 2 3 4 5 6 7 9 1211

20 192224252627282930

8 10 1413

18 172123

15

16

LD PD

EQ

_IN

AC

_SU

M

GN

D

A B D SW

FC E DV

C

DV

CC

RF

AC

DC

_OF

ST

RF

DC

I

RF

DC

O

VC

RF

C

VF

C

BS

T

VC

C

TE

_BA

L

CE

RF

G

CE

I

FE

I

TE

FE

E6 E5 E4 E3 E75.1k 5.1k

10k 200k 10k

10k20k20k

10k

10k 100k 10k

VCC

S12

VCC

DVCCVEE

VEEVCCVCCVEE

S11S10S9S8S7S6S5S3S2S1

S4

V1

0.1µ

E1

E20.8mA

Notes on Supply Voltage

2.5

6.5

6

5.5

5

4.5

43

DVcc (Pin 13) [V]

VCC voltage value at which the waveform is clipped when DVCC is fixed

Vcc

(P

in 2

2) [V

]

3.52

The voltage difference between VCC (Pin 22) and DVCC (Pin 13) should be kept to the value shown in the graph

above or less.

Example) When DVCC = 2.5V

From the graph, VCC = 4.5V

Therefore, VCC should be from 3.4 to 4.5V.

(3.4V is the minimum operating voltage for the IC.)

Electrical Characteristics Measurement Circuit

– 19 –

CXA2581N

LDDrive

1 2 3 4 5 6 7 9 12

20 192224252627282930

8 1413

18 172123

15

16

LD PD

EQ

_IN

AC

_SU

M

GN

D

A B D SW

FC E DV

C

DV

CC

RF

AC

DC

_OF

ST

RF

DC

I

RF

DC

O

VC

RF

C

VF

C

BS

T

VC

C

TE

_BA

L

CE

RF

G

CE

I

FE

I

TE

FE

VCRFDCOUT VCC

DVCC

CEOUT

TEOUT

FEOUT

DVCRFACOUT

MODEControl

FEDCBAPD IN

RF SUM RF SUM inputs the signal when A, B, Cand D are added by the front and PD.

0.1µ

1110

0.1µ

ACSUM

APC

ACVCA

EQ

VC

VC

RW/ROM

EQ_ON/OFF

VOFST DVC

DVCC

RW/ROM

VC

DVCC

25

15

30

29

28

17

16

26242334

6

7

8

9

DVC

DVCC

VC

VC

VOFST

DVC

DVC

VCC

VOFST

B

C

A

D

F

E

SW

PD

LD

VCC GND VC

VCCGNDVC

DVC

DVCC

CE

CEI

FEFE

RFDC

RFAC

FEI

RFDCO

RFDCI

RFAC

VF

C

RF

C

RF

G

VCCVCC

<CXA2581N>

<DSP>BS

T

EQ

_IN0.1µ

AC_SUM

DC_OFST

VCRW/ROM

21

14

20

13VC

APC-OFF (Hi-Z)RW/ROM(H/L)

F

E

<OP>

1

2

12

A

B

C

D

A

B

C

D

5 2722

VCA

ABCD

RF

VC

TE

CE

VCC

VC

B

VC

C

VC

D

VC

F

VC

E

VC

DVCC

RW/ROM

RW/ROM

RW/ROM

VOFST

VC

VC

19

18

DVC

TE

TE_BAL

gm

gm11

10

0.1µ

Application Circuits

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility forany problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 20 –

CXA2581N

Characteristics Graphs

EQ Rfc resistance value vs. Frequency response

[MHz]

Vbst = VC, Vfc = VC8

[dB

]

7

6

5

4

3

2

1

0

0.1 1

Rfc = 100kΩ

Rfc = 20kΩ Rfc = 5.1kΩ

10 100

–1

–2

RF DC frequency response

[MHz]

RW

38

[dB

]

35

32

29

26

23

20

17

14

0.1 1

ROM

10 100

11

8

FE frequency response

[MHz]

RW

34

[dB

]

31

28

25

22

19

16

13

10

0.01 0.1

ROM

1 10

7

4

RF AC frequency response

[MHz]

AC SUM

EQ_PassRW mode

EQ_PassROM mode

24

[dB

]

21

18

15

12

9

6

3

0

0.1 1 10 100

–3

–6

EQ Vfc vs. frequency response

[MHz]

Rfc = 20kΩVfc = –1V

Rfc = 20kΩVfc = 0V Rfc = 20kΩ

Vfc = 1V

8

[dB

]

7

6

5

4

3

2

1

0

0.1 1 10 100

–1

–2

EQ boost voltage vs. Frequency response

[MHz]

Vfc = VC12

[dB

]

10

8

6

4

2

0

–2

–4

0.1 1

Rfc = 100kΩVboost = 1.0V

Rfc = 100kΩVboost = 0V

Rfc = 5.1kΩVboost = 1.0V

Rfc = 5.1kΩVboost = 0V

Rfc = 100kΩVboost = –1.0V

Rfc = 5.1kΩVboost = –1.0V

10 100

–6

–8

Vbst = VC

– 21 –

CXA2581N

TE frequency response

[MHz]

RW

35

[dB

]

32

29

26

23

20

17

16

13

0.01 0.1

ROM

1 10

10

7

APC I/O characteristics

VPD – Input voltage [V]

5.5

VLD

– O

utpu

t vol

tage

[V]

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

0.05 0.1 0.15 0.2 0.25

1.0

0.5

CE frequency response

[MHz]

RW

34

[dB

]

31

28

25

22

19

16

13

10

0.01 0.1

ROM

1 10

7

4

Vcc = 5.5V

Vcc = 3.4V

– 22 –

CXA2581N

Package Outline Unit: mm

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN

SOLDER/PALLADIUM

42/COPPER ALLOY

30PIN SSOP (PLASTIC)

∗ 9.7 ± 0.1

∗5.6

± 0

.1

0.650.22 – 0.05

30

1 15

16

1.25+ 0.2– 0.1

7.6

± 0.

2

0.15+ 0.05– 0.02

0.1 ± 0.1

0.5

± 0.

2

0° to 10°

A

DETAIL A

SSOP-30P-L01

SSOP030-P-0056

0.1g

NOTE: Dimension “∗ ” does not include mold protrusion.

PLATING

0.10

0.13 M

+ 0.1

NOTE : PALLADIUM PLATINGThis product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).

Sony Corporation

This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.