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AT24C64D IC-Compatible (2-Wire) Serial EEPROM 64-Kbit (8,192 x 8)
Features
Low-Voltage and Standard-Voltage Operation: VCC = 1.7V to 5.5V
Internally Organized as 8,192 x 8 (64K) I2C-compatible (2-Wire) Serial Interface
100 kHz Standard mode, 1.7V to 5.5V 400 kHz Fast mode, 1.7V to 5.5V 1 MHz Fast Mode Plus (FM+), 2.5V to 5.5V
Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol WriteProtect Pin for Full Array Hardware Data Protection 32-byte Page Write Mode:
Partial page writes allowed Random and Sequential Read Modes SelfTimed Write Cycle (5 ms maximum) ESD Protection > 4,000V High Reliability:
Endurance: 1,000,000 write cycles Data retention: 100 years
Green Package Options (Lead-free/Halide-free/RoHS compliant) Die Sale Options: Wafer Form and Bumped Wafers
Packages
8-lead SOIC, 8-lead TSSOP, 8-pad UDFN, 8-ball VFBGA, 8-pad XDFN and 4ball/6ball WLCSP
2018 Microchip Technology Inc. Datasheet DS20005937A-page 1
Table of Contents
Features.......................................................................................................................... 1
Packages.........................................................................................................................1
1. Package Types (not to scale).................................................................................... 4
2. Pin Descriptions.........................................................................................................52.1. Ground......................................................................................................................................... 52.2. Device Addresses (A0, A1, A2)....................................................................................................52.3. Serial Data (SDA).........................................................................................................................52.4. Serial Clock (SCL)........................................................................................................................62.5. Write-Protect (WP)....................................................................................................................... 62.6. Device Power Supply................................................................................................................... 6
3. Description.................................................................................................................73.1. System Configuration Using 2-Wire Serial EEPROMs ................................................................73.2. Block Diagram..............................................................................................................................8
4. Electrical Characteristics........................................................................................... 94.1. Absolute Maximum Ratings..........................................................................................................94.2. DC and AC Operating Range.......................................................................................................94.3. DC Characteristics....................................................................................................................... 94.4. AC Characteristics......................................................................................................................104.5. Electrical Specifications..............................................................................................................11
5. Device Operation and Communication....................................................................135.1. Clock and Data Transition Requirements...................................................................................135.2. Start and Stop Conditions.......................................................................................................... 135.3. Acknowledge and No-Acknowledge...........................................................................................145.4. Standby Mode............................................................................................................................ 145.5. Software Reset...........................................................................................................................15
6. Memory Organization.............................................................................................. 166.1. Device Addressing..................................................................................................................... 16
7. Write Operations......................................................................................................177.1. Byte Write...................................................................................................................................177.2. Page Write..................................................................................................................................177.3. Acknowledge Polling.................................................................................................................. 187.4. Write Cycle Timing..................................................................................................................... 197.5. Write Protection..........................................................................................................................19
8. Read Operations..................................................................................................... 218.1. Current Address Read................................................................................................................218.2. Random Read............................................................................................................................ 21
AT24C64D
2018 Microchip Technology Inc. Datasheet DS20005937A-page 2
8.3. Sequential Read.........................................................................................................................22
9. Device Default Condition from Microchip................................................................ 23
10. Packaging Information.............................................................................................2410.1. Package Marking Information.....................................................................................................24
11. Revision History.......................................................................................................32
The Microchip Web Site................................................................................................ 33
Customer Change Notification Service..........................................................................33
Customer Support......................................................................................................... 33
Product Identification System........................................................................................34
Microchip Devices Code Protection Feature................................................................. 34
Legal Notice...................................................................................................................35
Trademarks................................................................................................................... 35
Quality Management System Certified by DNV.............................................................36
Worldwide Sales and Service........................................................................................37
AT24C64D
2018 Microchip Technology Inc. Datasheet DS20005937A-page 3
1. Package Types (not to scale)8-Lead SOIC/TSSOP
(Top View)
A0 1
2
3
4
8
7
6
5
A1
A2
GND
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-Ball VFBGA(Top View)
SDA
A2
6-Ball WLCSP(1)(Top View)
SCL
VCC
GND WP
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-Pad UDFN/XDFN(Top View)
1
2
3
4
8
7
6
5
VCC
SCL
4-Ball WLCSP(1)(Top View)
GND
SDA
A2A1
B1 B2
B1
B2
B3
A1
A2
A3
Note:1. For use of the 4ball and 6ball WLCSP packages, refer to Device Addressing for details about
setting the A2, A1, and A0 hardware address bits.
AT24C64DPackage Types (not to scale)
2018 Microchip Technology Inc. Datasheet DS20005937A-page 4
2. Pin DescriptionsThe descriptions of the pins are listed in Table 2-1.
Table 2-1.Pin Function TableName 8Lead
SOIC8LeadTSSOP
8PadUDFN(1)
8PadXDFN
8BallVFBGA
4BallWLCSP(2)
6BallWLCSP(2)
Function
A0 1 1 1 1 1 Address InputA1 2 2 2 2 2 Address InputA2 3 3 3 3 3 B3 Address Input
GND 4 4 4 4 4 A2 B2 GroundSDA 5 5 5 5 5 B2 B1 Serial DataSCL 6 6 6 6 6 B1 A1 Serial Clock
WP(3) 7 7 7 7 7 A2 Write-ProtectVCC 8 8 8 8 8 A1 A3 Device Power
Supply
Note: 1. The exposed pad on the UDFN package can be connected to GND or left floating.2. For use of the 4ball and 6ball CSP packages, refer to Device Addressing for details about setting
the A2, A1, and A0 hardware address bits.3. If the WP pin is not driven, it is internally pulled down to GND. In order to operate in a wide variety
of application environments, the pulldown mechanism is intentionally designed to be somewhatstrong. Once these pins are biased above the CMOS input buffers trip point (~0.5 x VCC), thepulldown mechanism disengages. Microchip recommends connecting these pins to a known statewhenever possible. Since the WLCSP has no WP pin, the write protection feature is not offered onthe WLCSP.
2.1 GroundThe ground reference for the power supply. GND should be connected to the system ground.
2.2 Device Addresses (A0, A1, A2)The A0, A1, and A2 pins are device address inputs that are hard-wired (directly to GND or to VCC) forcompatibility with other AT24C devices. When the pins are hard-wired, as many as eight devices may beaddressed on a single bus system. A device is selected when a corresponding hardware and softwarematch is true. If these pins are left floating, the A0, A1, and A2 pins will be internally pulled down to GND.However, due to capacitive coupling that may appear in customer applications, Microchip recommendsalways connecting the address pins to a known state. When using a pull-up resistor, Microchiprecommends using 10 k or less.
2.3 Serial Data (SDA)The SDA pin is an opendrain bidirectional input/output pin used to serially transfer data to and from thedevice. The SDA pin must be pulledhigh using an external pullup resistor (not to exceed 10 k in value)and may be wireORed with any number of other opendrain or opencollector pins from other devices onthe same bus.
AT24C64DPin Descriptions
2018 Microchip Technology Inc. Datasheet DS20005937A-page 5
2.4 Serial Clock (SCL)The SCL pin is used to provide a clock to the device and to control the flow of data to and from thedevice. Command and input data present on the SDA pin is always latched in on the rising edge of SCL,while output data on the SDA pin is clocked out on the falling edge of SCL. The SCL pin must either beforced high when the serial bus is idle or pulled high using an external pullup resistor.
2.5 Write-Protect (WP)The Write-Protect input, when connected to GND, allows normal write operations. When WP is connecteddirectly to VCC, all write operations to the protected memory are inhibited.
If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitivecoupling that may appear in customer applications, Microchip recommends always connecting the WPpins to a known state. When using a pullup resistor, Microchip recommends using 10 k or less.Table 2-2.Write-Protect
WP Pin Status Part of the Array Protected
At VCC Full Array
At GND Normal Read/Write Operations
2.6 Device Power SupplyThe VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages mayproduce spurious results and should not be attempted.
AT24C64DPin Descriptions
2018 Microchip Technology Inc. Datasheet DS20005937A-page 6
3. DescriptionThe AT24C64D provides 65,536 bits of Serial Electrically Erasable and Programmable Read-OnlyMemory (EEPROM) organized as 8,192 words of 8 bits each. The devices cascading feature allows up toeight devices to share a common 2wire bus. The device is optimized for use in many industrial andcommercial applications where lowpower and lowvoltage operation are essential. The devices areavailable in spacesaving 8lead JEDEC SOIC, 8lead TSSOP, 8pad UDFN, 8pad XDFN, 8ball VFBGAand 4ball/6ball WLCSP packages. All packages operate from 1.7V to 5.5V.
3.1 System Configuration Using 2-Wire Serial EEPROMs
I2C Bus Master:Microcontroller
Slave 0AT24CXXX
VCC
WP
SDA
SCL
A0
A1
A2
GND
VCC
GND
SCL
SDA
WP
RPUP(max) = tR(max)
0.8473 x CL
RPUP(min) = VCC - VOL(max)
IOL
Slave 1AT24CXXX
VCC
WP
SDA
SCL
A0
A1
A2
GND
Slave 7AT24CXXX
VCC
WP
SDA
SCL
A0
A1
A2
GND
VCC
AT24C64DDescription
2018 Microchip Technology Inc. Datasheet DS20005937A-page 7
3.2 Block Diagram
1 page
StartStop
Detector
GND
A2
MemorySystem Control
Module
High-VoltageGeneration Circuit
Data & ACK Input/Output Control
Address Registerand Counter
Write Protection
Control
DOUT
DIN
HardwareAddress
ComparatorVCC
WP
SCL
SDA
Power-on Reset
Generator
EEPROM Array
Column Decoder
Row
Dec
oder
Data Register
A1
A0
AT24C64DDescription
2018 Microchip Technology Inc. Datasheet DS20005937A-page 8
4. Electrical Characteristics
4.1 Absolute Maximum RatingsTemperature under bias -55C to +125C
Storage temperature -65C to +150C
Voltage on any pin with respect to ground -1.0V to +7.0V
VCC 6.25V
DC output current 5.0 mA
ESD protection >4 kV
Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage tothe device. This is a stress rating only and functional operation of the device at these or any otherconditions above those indicated in the operational sections of this specification are not implied.Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
4.2 DC and AC Operating RangeTable 4-1.DC and AC Operating Range
AT24C64D
Operating Temperature (Case) Industrial Temperature Range -40C to +85C
VCC Power Supply Low Voltage Grade 1.7V to 5.5V
4.3 DC CharacteristicsTable 4-2.DC Characteristics
Parameter Symbol Minimum Typical(1) Maximum Units Test Conditions
Supply Voltage VCC1 1.7 5.5 V
Supply Current ICC1 0.4 1.0 mA VCC = 5.0V, Read at 400 kHz
Supply Current ICC2 2.0 3.0 mA VCC = 5.0V, Write at 400 kHz
Standby Current ISB1 1.0 A VCC = 1.7V, VIN = VCC or GND
6.0 A VCC = 5.0V, VIN = VCC or GND
Input LeakageCurrent
ILI 0.10 3.0 A VIN = VCC or GND; VCC = 5.0V
Ouput LeakageCurrent
ILO 0.05 3.0 A VOUT = VCC or GND;VCC = 5.0V
Input Low Level VIL -0.6 VCC x 0.3 V Note 2
Input High Level VIH VCC x 0.7 VCC + 0.5 V Note 2
AT24C64DElectrical Characteristics
2018 Microchip Technology Inc. Datasheet DS20005937A-page 9
Parameter Symbol Minimum Typical(1) Maximum Units Test Conditions
Output Low Level VOL1 0.2 V VCC = 1.7V, IOL = 0.15 mA
Output Low Level VOL2 0.4 V VCC = 3.0V, IOL = 2.1 mA
Note:
1. Typical values characterized at TA = +25C unless otherwise noted.2. This parameter is characterized but is not 100% tested in production.
4.4 AC CharacteristicsTable 4-3.AC Characteristics(1, 2)
Parameter Symbol 1.7V 2.5V, 5.0V Units
Min. Max. Min. Max.
Clock Frequency, SCL fSCL 400 1000 kHz
Clock Pulse Width Low tLOW 1300 500 ns
Clock Pulse Width High tHIGH 600 400 ns
Noise Suppression Time(3) tI 100 50 ns
Clock Low to Data Out Valid tAA 50 900 50 450 ns
Bus Free Time between Stop andStart(3)
tBUF 1300 500 ns
Start Hold Time tHD.STA 600 250 ns
Start Setup Time tSU.STA 600 250 nsData In Hold Time tHD.DAT 0 0 ns
Data In Setup Time tSU.DAT 100 100 nsInputs Rise Time(3) tR 300 300 ns
Inputs Fall Time(3) tF 300 100 ns
Stop Set-up Time tSU.STO 600 250 ns
Data Out Hold Time tDH 50 50 ns
Write Cycle Time tWR 5 5 ms
25C, Page Mode, 3.3V Endurance(3) 1,000,000 WriteCycles
Note:1. Applicable over recommended operating range from: TA = -40C to +85C, VCC = 1.7V to 5.5V,
CL = 100 pF (unless otherwise noted).2. AC measurement conditions:
RPUP (SDA bus line pull-up resistor to VCC): 1.3 k (1000 kHz), 4 k (400 kHz), 10 k(100 kHz)
AT24C64DElectrical Characteristics
2018 Microchip Technology Inc. Datasheet DS20005937A-page 10
Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: 50 ns Input and output timing reference voltages: 0.5 x VCC
3. This parameter is ensured by characterization and is not 100% tested.
Figure 4-1.Bus Timing
SCL
SDA In
SDA Out
tFtHIGH
tLOW tLOW
tR
tDHtAA tBUF
tSU.STOtSU.DATtHD.DATtHD.STAtSU.STA
4.5 Electrical Specifications
4.5.1 Power-up Requirements and Reset BehaviorDuring a power-up sequence, the VCC supplied to the AT24C64D should monotonically rise from GND tothe minimum VCC level as specified in Table 4-1 with a slew rate no faster than 0.1 V/s.
4.5.1.1 Device ResetTo prevent inadvertent write operations or any other spurious events from occurring during a powerupsequence, the AT24C64D includes a Power-on Reset (POR) circuit. Upon powerup, the device will notrespond to any commands until the VCC level crosses the internal voltage threshold (VPOR) that brings thedevice out of Reset and into Standby mode.
The system designer must ensure the instructions are not sent to the device until the VCC supply hasreached a stable value greater than or equal to the minimum VCC level. Additionally, once the VCC isgreater than or equal to the minimum VCC level, the bus master must wait at least tPUP before sending thefirst command to the device. See Table 4-4 for the values associated with these powerup parameters.Table 4-4.Power-up Conditions(1)
Symbol Parameter Min. Max. Units
tPUP Time required after VCC is stable before the device can accept commands 100 s
VPOR Power-on Reset Threshold Voltage 1.5 V
tPOFF Minimum time at VCC = 0V between power cycles 1 ms
Note:1. These parameters are characterized but they are not 100% tested in production.
If an event occurs in the system where the VCC level supplied to the AT24C64D drops below themaximum VPOR level specified, it is recommended that a full power cycle sequence be performed by firstdriving the VCC pin to GND, waiting at least the minimum tPOFF time, and then performing a new power-upsequence in compliance with the requirements defined in this section.
AT24C64DElectrical Characteristics
2018 Microchip Technology Inc. Datasheet DS20005937A-page 11
4.5.2 Pin CapacitanceTable 4-5.Pin Capacitance(1)
Symbol Test Condition Max. Units Conditions
CI/O Input/OutputCapacitance (SDA)
8 pF VI/O = 0V
CIN Input Capacitance (A0,A1, A2 and SCL)
6 pF VIN = 0V
Note:1. This parameter is characterized but is not 100% tested in production.
4.5.3 EEPROM Cell Performance CharacteristicsTable 4-6.EEPROM Cell Performance Characteristics
Operation Test Condition Min. Max. Units
WriteEndurance(1)
TA = 25C,VCC (min.) < VCC < VCC (max.) Byte orPage Write mode
1,000,000 Write Cycles
Data Retention(2) TA = 55C, VCC(min.) < VCC < VCC(max.)
100 Years
Note: 1. Write endurance performance is determined through characterization and the qualification process. 2. The data retention capability is determined through qualification and is checked on each device in
production.
AT24C64DElectrical Characteristics
2018 Microchip Technology Inc. Datasheet DS20005937A-page 12
5. Device Operation and CommunicationThe AT24C64D operates as a slave device and utilizes a simple I2C-compatible 2-wire digital serialinterface to communicate with a host controller, commonly referred to as the bus master. The masterinitiates and controls all read and write operations to the slave devices on the serial bus, and both themaster and the slave devices can transmit and receive data on the bus.
The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data (SDA). TheSCL pin is used to receive the clock signal from the master, while the bidirectional SDA pin is used toreceive command and data information from the master as well as to send data back to the master. Datais always latched into the AT24C64D on the rising edge of SCL and always output from the device on thefalling edge of SCL. Both the SCL and SDA pin incorporate integrated spike suppression filters andSchmitt Triggers to minimize the effects of input spikes and bus noise.
All command and data information is transferred with the Most Significant bit (MSb) first. During buscommunication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data havebeen transferred, the receiving device must respond with either an Acknowledge (ACK) or aNo-Acknowledge (NACK) response bit during a ninth clock cycle (ACK/NACK clock cycle) generated bythe master. Therefore, nine clock cycles are required for every one byte of data transferred. There are nounused clock cycles during any read or write operation, so there must not be any interruptions or breaksin the data stream during each data byte transfer and ACK or NACK clock cycle.
During data transfers, data on the SDA pin must only change while SCL is low, and the data must remainstable while SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stopcondition will occur. Start and Stop conditions are used to initiate and end all serial bus communicationbetween the master and the slave devices. The number of data bytes transferred between a Start and aStop condition is not limited and is determined by the master. In order for the serial bus to be idle, boththe SCL and SDA pins must be in the logic-high state at the same time.
5.1 Clock and Data Transition RequirementsThe SDA pin is an open-drain terminal and therefore must be pulled high with an external pullup resistor.SCL is an input pin which can either be driven high or pulled high using an external pullup resistor. Dataon the SDA pin may change only during SCL low time periods. Data changes during SCL high periodswill indicate a Start or Stop condition as defined below. The relationship of the AC timing parameters withrespect to SCL and SDA for the AT24C64D are shown in the timing waveform in Figure 4-1. The ACtiming characteristics and specifications are outlined in AC Characteristics.
5.2 Start and Stop Conditions
5.2.1 Start ConditionA Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is at astable logic 1 state and will bring the device out of Standby mode. The master uses a Start condition toinitiate any data transfer sequence; therefore, every command must begin with a Start condition. Thedevice will continuously monitor the SDA and SCL pins for a Start condition but will not respond unlessone is detected. Refer to Figure 5-1 for more details.
5.2.2 Stop ConditionA Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stablein the logic 1 state.
AT24C64DDevice Operation and Communication
2018 Microchip Technology Inc. Datasheet DS20005937A-page 13
The master can use the Stop condition to end a data transfer sequence with the AT24C64D which willsubsequently return to Standby mode. The master can also utilize a repeated Start condition instead of aStop condition to end the current data transfer if the master will perform another operation. Refer to Figure 5-1 for more details.
5.3 Acknowledge and No-AcknowledgeAfter every byte of data is received, the receiving device must confirm to the master that it hassuccessfully received the data byte by responding with what is known as an Acknowledge (ACK). AnACK is accomplished by the transmitting device first releasing the SDA line at the falling edge of theeighth clock cycle followed by the receiving device responding with a logic 0 during the entire high periodof the ninth clock cycle.
When the AT24C64D is transmitting data to the master, the master can indicate that it is done receivingdata and wants to end the operation by sending a logic 1 response to the AT24C64D instead of an ACKresponse during the ninth clock cycle. This is known as a No-Acknowledge (NACK) and is accomplishedby the master sending a logic 1 during the ninth clock cycle, at which point the AT24C64D will releasethe SDA line so the master can then generate a Stop condition.
The transmitting device, which can be the bus master or the Serial EEPROM, must release the SDA lineat the falling edge of the eighth clock cycle to allow the receiving device to drive the SDA line to a logic 0to ACK the previous 8bit word. The receiving device must release the SDA line at the end of the ninthclock cycle to allow the transmitter to continue sending new data. A timing diagram has been provided in Figure 5-1 to better illustrate these requirements.
Figure 5-1.Start Condition, Data Transitions, Stop Condition, and Acknowledge
SCL
SDA
SDAMust BeStable
SDAChangeAllowed
SDAChangeAllowed
AcknowledgeValid
StopConditionStart
Condition
1 2 8 9
SDAMust BeStable Acknowledge Window
The transmitting device (Master or Slave) must release the SDA line at this point to allow
the receiving device (Master or Slave) to drive the SDA line low to ACK the previous 8-bit word.
The receiver (Master or Slave)must release the SDA line at
this point to allow the transmitter to continue sending new data.
5.4 Standby ModeThe AT24C64D features a lowpower Standby mode which is enabled when any one of the followingoccurs:
A valid power-up sequence is performed (see Power-up Requirements and Reset Behavior). A Stop condition is received by the device unless it initiates an internal write cycle (see Write
Operations). At the completion of an internal write cycle (see Write Operations). An unsuccessful match of the device type identifier or hardware address in the device address byte
occurs (see Device Addressing).
AT24C64DDevice Operation and Communication
2018 Microchip Technology Inc. Datasheet DS20005937A-page 14
The bus master does not ACK the receipt of data read out from the device; instead it sends aNACK response. (see Read Operations).
5.5 Software ResetAfter an interruption in protocol, power loss, or system Reset, any 2wire device can be protocol reset byclocking SCL until SDA is released by the EEPROM and goes high. The number of clock cycles until SDAis released by the EEPROM will vary. The software Reset sequence should not take more than ninedummy clock cycles. Once the software Reset sequence is complete, new protocol can be sent to thedevice by sending a Start condition followed by the protocol. Refer to Figure 5-2 for an illustration.
Figure 5-2.Software Reset
SCL 9
Device is
8321
SDA
Dummy Clock Cycles
SDA ReleasedSoftware Resetby EEPROM
In the event that the device is still non-responsive or remains active on the SDA bus, a power cycle mustbe used to reset the device (see Power-up Requirements and Reset Behavior).
AT24C64DDevice Operation and Communication
2018 Microchip Technology Inc. Datasheet DS20005937A-page 15
6. Memory OrganizationThe AT24C64D is internally organized as 256 pages of 32 bytes each.
6.1 Device AddressingAccessing the device requires an 8bit device address byte following a Start condition to enable thedevice for a read or write operation. Since multiple slave devices can reside on the serial bus, each slavedevice must have its own unique address so the master can access each device independently.
The Most Significant four bits of the device address byte is referred to as the device type identifier. Thedevice type identifier 1010' (Ah) is required in bits 7 through 4 of the device address byte (Table 6-1).Following the 4-bit device type identifier are the hardware slave address bits, A0, A1, and A2. These bitscan be used to expand the address space by allowing up to eight Serial EEPROM devices on the samebus. These hardware slave address bits must correlate with the voltage level on the correspondinghardwired input pins A0, A1, and A2. The A0, A1, and A2 pins use an internal proprietary circuit thatautomatically biases the pin to a logic 0 state if the pin is allowed to float. In order to operate in a widevariety of application environments, the pulldown mechanism is intentionally designed to be somewhatstrong. Once the pin is biased above the CMOS input buffer's trip point (~0.5 x VCC), the pulldownmechanism disengages. Microchip recommends connecting the A0, A1, and A2 pin to a known statewhenever possible.
When utilizing the 6ball WLCSP package, the A1 and A0 pins are not available and are internally pulledto ground; therefore, the A1 and A0 device address bits must always be set to a logic 0' condition tocommunicate with the device. This condition is shown in Table 6-1.
When utilizing the 4-ball WLCSP package, the A2, A1, and A0 pins are not available and are internallypulled to ground; therefore, the A2, A1 and A0 device address bits must always be set to a logic 0'condition to communicate with the device. This condition is depicted in Table 6-1.
The eighth bit (bit 0) of the device address byte is the Read/Write Select bit. A read operation is initiated ifthis bit is high and a write operation is initiated if this bit is low.
Upon the successful comparison of the device address byte, the AT24C64D will return an ACK. If a validcomparison is not made, the device will NACK and return to a standby state.
Table 6-1.Device Addressing
Package Device Type Identifier Hardware Address Bits R/W Select
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SOIC, TSSOP, UDFN,XDFN and VFBGA
1 0 1 0 A2 A1 A0 R/W
4-ball WLCSP 1 0 1 0 0 0 0 R/W6-ball WLCSP 1 0 1 0 A2 0 0 R/W
6.1.1 Data SecurityThe AT24C64D has a hardware data protection scheme that allows the user to writeprotect the wholememory when the WP pin is at VCC. The 4ball WLCSP does not include a WP pin, and therefore no writeprotection is possible in this package only.
AT24C64DMemory Organization
2018 Microchip Technology Inc. Datasheet DS20005937A-page 16
7. Write OperationsAll write operations for the AT24C64D begin with the master sending a Start condition, followed by adevice address byte with the R/W bit set to logic 0, and then by the word address bytes. The datavalue(s) to be written to the device immediately follow the word address bytes.
7.1 Byte WriteThe AT24C64D supports the writing of a single 8bit byte. Selecting a data word in the AT24C64Drequires a 13bit word address.Upon receipt of the proper device address and word address bytes, the EEPROM will send anAcknowledge. The device will then be ready to receive the first 8bit data word. Following receipt of the8bit data word, the EEPROM will respond with an Acknowledge. The addressing device, such as a busmaster, must then terminate the write operation with a Stop condition. At that time, the EEPROM willenter an internally selftimed write cycle which will be completed within tWR while the data word is beingprogrammed into the nonvolatile EEPROM. All inputs are disabled during this write cycle, and theEEPROM will not respond until the write is complete.
Figure 7-1.Byte Write
SCL
SDA
Start Conditionby Master
Device Address Byte First Word Address Byte
MSB MSB
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 1 0 A2 A1 A0 0 0
Second Word Address Byte Data Word
Stop Conditionby Master
MSB MSB
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
D7 D6 D5 D4 D3 D2 D1 D0 0
X X X A12 A11 A10 A9 A8 0
ACKfrom Slave
ACKfrom Slave
ACKfrom Slave
ACKfrom Slave
A7 A6 A5 A4 A3 A2 A1 A0 0
7.2 Page WriteA page write operation allows up to 32 bytes to be written in the same write cycle, provided all bytes arein the same row of the memory array (where address bits A12 through A5 are the same). Partial pagewrites of less than 32 bytes are also allowed.
A page write is initiated the same way as a byte write, but the bus master does not send a Stop conditionafter the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first dataword, the bus master can transmit up to thirty one additional data words. The EEPROM will respond withan ACK after each data word is received. Once all data to be written has been sent to the device, the busmaster must issue a Stop condition (Figure 7-2) at which time the internally self-timed write cycle willbegin.
The lower five bits of the word address are internally incremented following the receipt of each data word.The higher order address bits are not incremented and retain the memory page row location.
AT24C64DWrite Operations
2018 Microchip Technology Inc. Datasheet DS20005937A-page 17
Page write operations are limited to writing bytes within a single physical page, regardless of the numberof bytes actually being written.
When the incremented word address reaches the page boundary, the address counter will rollover to thebeginning of the same page. Nevertheless, creating a rollover event should be avoided as previouslyloaded data in the page could become unintentionally altered.
Figure 7-2.Page Write
SCL
SDA
Start Conditionby Master ACK
from SlaveACK
from Slave
Device Address Byte First Word Address Byte
MSB MSB
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 1 0 A2 A1 A0 0 0 X X X A12 A11 A10 A9 A8 0
ACKfrom Slave
ACKfrom Slave
Stop Conditionby MasterACK
from Slave
Second Word Address Byte Data Word (n) Data Word (n+x), max of 32 without rollover
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
A7 A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0MSB MSB MSB
7.3 Acknowledge PollingAn Acknowledge Polling routine can be implemented to optimize timesensitive applications that wouldprefer not to wait the fixed maximum write cycle time (tWR). This method allows the application to knowimmediately when the Serial EEPROM write cycle has completed, so a subsequent operation can bestarted.
Once the internally selftimed write cycle has started, an Acknowledge Polling routine can be initiated.This involves repeatedly sending a Start condition followed by a valid device address byte with the R/Wbit set at logic 0. The device will not respond with an ACK while the write cycle is ongoing. Once theinternal write cycle has completed, the EEPROM will respond with an ACK, allowing a new read or writeoperation to be immediately initiated. A flowchart has been included below in Figure 7-3 to better illustratethis technique.
Figure 7-3.Acknowledge Polling Flow Chart
Did the device
ACK?
Send any Write
protocol
Send Stop
condition to initiate the
write cycle
Send Start condition followed
by a valid Device Address
byte with R/W = 0
Proceed to next Read or
Write operation
NO
YES
AT24C64DWrite Operations
2018 Microchip Technology Inc. Datasheet DS20005937A-page 18
7.4 Write Cycle TimingThe length of the selftimed write cycle (tWR) is defined as the amount of time from the Stop condition thatbegins the internal write operation to the Start condition of the first device address byte sent to theAT24C64D that it subsequently responds to with an ACK.
Figure 7-4 has been included to show this measurement. During the internally selftimed write cycle, anyattempts to read from or write to the memory array will not be processed.
Figure 7-4.Write Cycle Timing
tWRStop
ConditionStart
Condition
Data Word n
ACKD0SDA
StopCondition
SCL 8 9
ACK
First Acknowledge from the deviceto a valid device address sequence afterwrite cycle is initiated. The minumum tWR
can only be determined throughthe use of an ACK Polling routine.
9
7.5 Write ProtectionThe AT24C64D utilizes a hardware data protection scheme that allows the user to writeprotect the entirememory contents when the WP pin is at VCC (or a valid VIH). No write protection will be set if the WP pinis at GND or left floating. The 4ball WLCSP version of the device does not include any write protectionfeatures.
Table 7-1.AT24C64D Write-Protect Behavior
WP Pin Voltage Part of the Array Protected
VCC Full Array
GND None Write Protection Not Enabled
The status of the WP pin is sampled at the Stop condition for every byte write or page write commandprior to the start of an internally selftimed write operation. Changing the WP pin state after the Stopcondition has been sent will not alter or interrupt the execution of the write cycle. The WP pin state mustbe valid with respect to the associated setup (tSU:WP) and hold (tHD:WP) timing as shown in Figure 7-5below. The WP setup time is the amount of time that the WP state must be stable before the Stopcondition is issued. The WP hold time is the amount of time after the Stop condition that the WP mustremain stable.
If an attempt is made to write to the device while the WP pin has been asserted, the device willAcknowledge the device address, word address, and data bytes but no write cycle will occur when theStop condition is issued, and the device will immediately be ready to accept a new read or writecommand.
AT24C64DWrite Operations
2018 Microchip Technology Inc. Datasheet DS20005937A-page 19
Figure 7-5.Write-Protect Setup and Hold Timing
SCL
SDA IN
1 2 7 8 9
D7 D6 D1 D0
WP
tSU.WP
Stop Conditionby Master
Data Word Input Sequence Page/Byte Write Operation
ACK by Slave
tHD.WP
AT24C64DWrite Operations
2018 Microchip Technology Inc. Datasheet DS20005937A-page 20
8. Read OperationsRead operations are initiated the same way as write operations with the exception that the Read/WriteSelect bit in the device address byte must be a logic '1'. There are three read operations:
Current Address Read Random Address Read Sequential Read
8.1 Current Address ReadThe internal data word address counter maintains the last address accessed during the last read or writeoperation, incremented by one. This address stays valid between operations as long the VCC ismaintained to the part. The address rollover during read is from the last byte of the last page to the firstbyte of the first page of the memory.
A current address read operation will output data according to the location of the internal data wordaddress counter. This is initiated with a Start condition, followed by a valid device address byte with theR/W bit set to logic 1. The device will ACK this sequence and the current address data word is seriallyclocked out on the SDA line. All types of read operations will be terminated if the bus master does notrespond with an ACK (it NACKs) during the ninth clock cycle, which will force the device into Standbymode. After the NACK response, the master may send a Stop condition to complete the protocol, or it cansend a Start condition to begin the next sequence.
Figure 8-1.Current Address Read
SCL
SDA
Device Address Byte Data Word (n)
Start Conditionby Master ACK
from SlaveNACK
from Master
Stop Conditionby Master
MSB MSB1 0 1 0 A2 A1 A0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
8.2 Random ReadA random read begins in the same way as a byte write operation does to load in a new data wordaddress. This is known as a dummy write sequence; however, the data byte and the Stop condition ofthe byte write must be omitted to prevent the part from entering an internal write cycle. Once the deviceaddress and word address are clocked in and acknowledged by the EEPROM, the bus master mustgenerate another Start condition. The bus master now initiates a current address read by sending a Startcondition, followed by a valid device address byte with the R/W bit set to logic 1. The EEPROM will ACKthe device address and serially clock out the data word on the SDA line. All types of read operations willbe terminated if the bus master does not respond with an ACK (it NACKs) during the ninth clock cycle,which will force the device into Standby mode. After the NACK response, the master may send a Stopcondition to complete the protocol, or it can send a Start condition to begin the next sequence.
AT24C64DRead Operations
2018 Microchip Technology Inc. Datasheet DS20005937A-page 21
Figure 8-2.Random Read
SCL
SDA
Start Conditionby Master
Device Address Byte First Word Address Byte
MSB MSB
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 1 0 A2 A1 A0 0 0
Dummy Write
Start Conditionby Master
Device Address Byte Data Word (n)
Stop Conditionby Master
MSB MSB
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 1 0 A2 A1 A0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1
X X X A12 A11 A10 A9 A8 0
ACKfrom Slave
ACKfrom Slave
ACKfrom Slave
NACKfrom Master
Second Word Address Byte
MSB
A7 A6 A5 A4 A3 A2 A1 A0 0
ACKfrom Slave
8.3 Sequential ReadSequential reads are initiated by either a current address read or a random read. After the bus masterreceives a data word, it responds with an Acknowledge. As long as the EEPROM receives an ACK, it willcontinue to increment the word address and serially clock out sequential data words. When the maximummemory address is reached, the data word address will roll-over and the sequential read will continuefrom the beginning of the memory array. All types of read operations will be terminated if the bus masterdoes not respond with an ACK (it NACKs) during the ninth clock cycle, which will force the device intoStandby mode. After the NACK response, the master may send a Stop condition to complete theprotocol, or it can send a Start condition to begin the next sequence.
Figure 8-3.Sequential Read
SCL
SDA
Start Conditionby Master ACK
from SlaveACK
from Master
Device Address Byte Data Word (n)
MSB MSB
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 1 0 A2 A1 A0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0
ACKfrom Master
NACKfrom Master
Stop Conditionby MasterACK
from Master
Data Word (n+1) Data Word (n+2) Data Word (n+x)
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 1MSB MSB MSB
AT24C64DRead Operations
2018 Microchip Technology Inc. Datasheet DS20005937A-page 22
9. Device Default Condition from MicrochipThe AT24C64D is delivered with the EEPROM array set to logic 1, resulting in FFh data in all locations.
AT24C64DDevice Default Condition from Microchip
2018 Microchip Technology Inc. Datasheet DS20005937A-page 23
10. Packaging Information
10.1 Package Marking Information
AT24C64D: Package Marking Information
Catalog Number Truncation
AT24C64D Truncation Code ###: 64D
Date Codes Voltages
YY = Year Y = Year WW = Work Week of Assembly % = Minimum Voltage 16: 2016 20: 2020 6: 2016 0: 2020 02: Week 2 M: 1.7V min17: 2017 21: 2021 7: 2017 1: 2021 04: Week 4 18: 2018 22: 2022 8: 2018 2: 2022 ... 19: 2019 23: 2023 9: 2019 3: 2023 52: Week 52
Country of Origin Device Grade Atmel Truncation
CO = Country of Origin H or U: Industrial Grade AT: Atmel ATM: Atmel ATML: Atmel
Lot Number or Trace Code
NNN = Alphanumeric Trace Code (2 Characters for Small Packages)
8-lead SOIC
YYWWNNN###% COATMLHYWW
8-lead TSSOP
YYWWNNN###%COATHYWW ###
NNN
8-pad XDFN
8-pad UDFN
###H%NNN
2.0 x 3.0 mm Body
4 and 6-ball WLCSP
2.35 x 3.73 mm Body
8-ball VFBGA
1.8 x 2.2 mm Body
Note 2: Package drawings are not to scale
Note 1: designates pin 1
%U###NNN
###UWNNN
AT24C64DPackaging Information
2018 Microchip Technology Inc. Datasheet DS20005937A-page 24
10.1.1 8S1 8-Lead JEDEC SOIC
19AT24C16D [DATASHEET]Atmel-8906F-SEEPROM-AT24C16D-Datasheet_012017
12. Packaging Information
12.1 8S1 8-lead JEDEC SOIC
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 0.25 A 1.75
b 0.31 0.51 C 0.17 0.25 D 4.90 BSC E 6.00 BSC E1 3.90 BSC
e 1.27 BSC L 0.40 1.27 0 8
E
1
N
TOP VIEW
C
E1
END VIEW
Ab
L
A1
e
D
SIDE VIEW
8S1 H
3/6/2015
Notes: This drawing is for general information only.Refer to JEDEC Drawing MS-012, Variation AAfor proper dimensions, tolerances, datums, etc.
8S1, 8-lead (0.150 Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) SWB
Note: For the most current package drawings, please see the Microchip Packaging Specification locatedat http://www.microchip.com/packaging.
AT24C64DPackaging Information
2018 Microchip Technology Inc. Datasheet DS20005937A-page 25
http://www.microchip.com/packaging10.1.2 8X 8-lead TSSOP
AT24C16D [DATASHEET]Atmel-8906F-SEEPROM-AT24C16D-Datasheet_012017
20
12.2 8X 8-lead TSSOP
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A - - 1.20
A1 0.05 - 0.15
A2 0.80 1.00 1.05
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
b 0.19 0.25 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
C 0.09 - 0.20
Side View
End ViewTop View
A2
A
L
L1
D
1
E1
N
b
Pin 1 indicatorthis corner
E
e
Notes: 1. This drawing is for general information only.Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gateburrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.Inter-lead Flash and protrusions shall not exceed 0.25mm (0.010in) per side.
4. Dimension b does not include Dambar protrusion.Allowable Dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8X E
2/27/14
8X, 8-lead 4.4mm Body, Plastic ThinShrink Small Outline Package (TSSOP) TNR
C
A1
Note: For the most current package drawings, please see the Microchip Packaging Specification locatedat http://www.microchip.com/packaging.
AT24C64DPackaging Information
2018 Microchip Technology Inc. Datasheet DS20005937A-page 26
http://www.microchip.com/packaging10.1.3 8MA2 8-Pad UDFN
21AT24C16D [DATASHEET]Atmel-8906F-SEEPROM-AT24C16D-Datasheet_012017
12.3 8MA2 8-pad UDFN
DRAWING NO. REV. TITLE GPC
8MA2 H
11/2/15
8MA2, 8-pad 2 x 3 x 0.6mm Body, ThermallyEnhanced Plastic Ultra Thin Dual Flat No-LeadPackage (UDFN)
YNZ
COMMON DIMENSIONS(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTEA 0.50 0.55 0.60
A1 0.0 0.02 0.05
A2 - - 0.55
D 1.90 2.00 2.10
D2 1.40 1.50 1.60
E 2.90 3.00 3.10
E2 1.20 1.30 1.40
b 0.18 0.25 0.30 3
C 0.152 REF
L 0.35 0.40 0.45
e 0.50 BSC
K 0.20 - -
TOP VIEW
SIDE VIEW
BOTTOM VIEW
C
E
Pin 1 ID
D
8
7
6
5
1
2
3
4
A
A1
A2
D2
E2
e (6x)
L (8x)
b (8x)
Pin#1 ID
K
1
2
3
4
8
7
6
5
Notes: 1. This drawing is for general information only. Refer to Drawing MO-229, for proper dimensions, tolerances,datums, etc.
2. The Pin #1 ID is a laser-marked feature on Top View.3. Dimensions b applies to metallized terminal and is
measured between 0.15 mm and 0.30 mm from theterminal tip. If the terminal has the optional radius onthe other end of the terminal, the dimension shouldnot be measured in that radius area.
4. The Pin #1 ID on the Bottom View is an orientationfeature on the thermal pad.
C
Note: For the most current package drawings, please see the Microchip Packaging Specification locatedat http://www.microchip.com/packaging.
AT24C64DPackaging Information
2018 Microchip Technology Inc. Datasheet DS20005937A-page 27
http://www.microchip.com/packaging10.1.4 8U2-1 8-Ball VFBGA
23AT24C64D [DATASHEET]Atmel-8850D-SEEPROM-AT24C64D-Datasheet_052015
13.8 8U2-1 8-ball VFBGA
DRAWING NO. REV. TITLE GPC
8U2-1 G
6/11/13
8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
GWW
COMMON DIMENSIONS(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.81 0.91 1.00A1 0.15 0.20 0.25 A2 0.40 0.45 0.50 b 0.25 0.30 0.35 D 2.35 BSC E 3.73 BSC e 0.75 BSC e1 0.74 REF d 0.75 BSCd1 0.80 REF
2. Dimension 'b' is measured at the maximum solder ball diameter.1. This drawing is for general
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
Notes:
A
d 0.08 C
C
f 0.10 C
A1
A2
b
j n 0.15 m C A Bj n 0.08 m C
A
(4X)d 0.10
B
A1 BALL PAD CORNER
D
E
SIDE VIEWTOP VIEW
e
(e1)
d
2 1
D
C
B
A
A1 BALL PAD CORNER
(d1)
8 SOLDER BALLS
BOTTOM VIEW
Note: For the most current package drawings, please see the Microchip Packaging Specification locatedat http://www.microchip.com/packaging.
AT24C64DPackaging Information
2018 Microchip Technology Inc. Datasheet DS20005937A-page 28
http://www.microchip.com/packaging10.1.5 8ME1 8-Pad XDFN
19AT24C64D [DATASHEET]Atmel-8850D-SEEPROM-AT24C64D-Datasheet_052015
13.4 8ME1 8-pad XDFN
GPC DRAWING NO. REV. TITLE
COMMON DIMENSIONS(Unit of Measure = mm)
DTP
SYMBOL MIN NOM MAX NOTE
0.001.702.100.15
0.26
AA1DEbe
e1L
1.802.200.20
0.40 TYP1.20 REF
0.30
0.400.051.902.300.25
0.35End View
8ME1 B
9/10/2012
8ME1, 8-pad (1.80mm x 2.20mm body) Extra Thin DFN (XDFN)
Top View
6 57
43
E
D
8
1 2
PIN #1 ID
0.10
0.15
b
L
b
e
PIN #1 ID
e1
A1
A
Side View
Note: For the most current package drawings, please see the Microchip Packaging Specification locatedat http://www.microchip.com/packaging.
AT24C64DPackaging Information
2018 Microchip Technology Inc. Datasheet DS20005937A-page 29
http://www.microchip.com/packaging10.1.6 4U-12 4-Ball WLCSP
AT24C64D [DATASHEET]Atmel-8850D-SEEPROM-AT24C64D-Datasheet_052015
22
13.7 4U-12 4-ball WLCSP
DRAWING NO. REV. TITLE GPC
4U-12 B
2/14/18
4U-12, 4-ball, 2x2 Array, 0.40mm Pitch Wafer Level Chip Scale Package (WLCSP) with BSC GVF
COMMON DIMENSIONS(Unit of Measure = mm)
SYMBOL MIN TYP MAX NOTE
A 0.260 0.295 0.330
A1 0.080 0.095 0.110
A2 0.160 0.175 0.190
A3 0.025 REF 3
D Contact Microchip for details
d1 0.400 BSC
E Contact Microchip for details
e1 0.400 BSC
b 0.170 0.185 0.200
PIN ASSIGNMENT MATRIX
BOTTOM VIEWTOP VIEW
SIDE VIEW
1 2
A
B
VCC
SDA
GND
SCL
d1
e1E
A2
A1
A
k 0.075 C
-C-
B
A
2 1
B
A
1 2
A3
Note: 1. Dimensions are NOT to scale.2. Solder ball composition is 95.5Sn-4.0Ag-0.5Cu.3. Product offered with Back Side Coating (BSC)
SEATING PLANE
b (4X)
vd0.015 Cd0.05 C A B
d
m
m
k 0.015 (4X)
A
BD
A1 CORNER A1 CORNER
Note: For the most current package drawings, please see the Microchip Packaging Specification locatedat http://www.microchip.com/packaging.
AT24C64DPackaging Information
2018 Microchip Technology Inc. Datasheet DS20005937A-page 30
http://www.microchip.com/packaging10.1.7 6U-2 6-Ball WLCSP
AT24C64D [DATASHEET]Atmel-8850D-SEEPROM-AT24C64D-Datasheet_052015
20
13.5 6U-2 6-ball WLCSP
DRAWING NO. REV. TITLE GPC
6U-2 C
5/6/15
6U-2, 6-ball, 2x3 Array, 0.40mm pitch Wafer Level Chip Scale Package (WLCSP) with BSC GMK
COMMON DIMENSIONS(Unit of Measure = mm)
SYMBOL MIN TYP MAX NOTE
A 0.260 0.295 0.330
A1 0.080 0.095 0.110
A2 0.160 0.175 0.190
A3 0.025 REF 3
D Contact Microchip for details
d1 0.40 BSC
E Contact Microchip for details
e1 0.40 BSC
b 0.170 0.185 0.200
TOP VIEW
SIDE VIEW
BOTTOM SIDE
PIN ASSIGNMENT MATRIX
Note: 1. Dimensions are NOT to scale.2. Solder ball composition is 95.5Sn-4.0Ag-0.5Cu.3. Product offered with Back Side Coating (BSC)
A
B
1 2 3
B
A
123
D
E
d1
e1
A
B
1 2 3
VCCWPSCL
A2GNDSDA
d b
A
B
C
v d 0.015m Cd 0.05m C A B
k 0.015 C
k 0.075 C
A1 CORNER A1 CORNER
A1
SEATING PLANE
A3A2 A
Note: For the most current package drawings, please see the Microchip Packaging Specification locatedat http://www.microchip.com/packaging.
AT24C64DPackaging Information
2018 Microchip Technology Inc. Datasheet DS20005937A-page 31
http://www.microchip.com/packaging11. Revision History
Atmel Document 8805 Revision A (June 2013)Initial document release.
Atmel Document 8805 Revision B (December 2014)Added the AT24C64DMAHME product offering. Updated the 8X, 8MA2, 5U2, and 8U21 packageoutline drawings and the ordering information.
Atmel Document 8805 Revision C (February 2015)Updated the 6ball and 5ball WLCSP package outline drawings to reflect offering of product withbackside coating.
Atmel Document 8805 Revision D (May 2015)Added the 4ball WLCSP, AT24C64DU2UM0BT option. Updated the 8S1 package drawing.
Revision A (February 2018)Updated to the Microchip template. Microchip DS20005937A replaces Atmel document 8805. UpdatedPackage Marking Information. Removed the 5ball WLCSP detail and ordering code. Updated PackageDrawing 4U-12. Updated Product ID System. Updated the Software Reset section. Added ESD rating.Removed lead finish designation. Updated trace code format in package markings. Updated sectioncontent throughout for clarification. Added a figure for System Configuration Using 2Wire SerialEEPROMs. Added POR recommendations section.
AT24C64DRevision History
2018 Microchip Technology Inc. Datasheet DS20005937A-page 32
The Microchip Web Site
Microchip provides online support via our web site at http://www.microchip.com/. This web site is used asa means to make files and information easily available to customers. Accessible by using your favoriteInternet browser, the web site contains the following information:
Product Support Data sheets and errata, application notes and sample programs, designresources, users guides and hardware support documents, latest software releases and archivedsoftware
General Technical Support Frequently Asked Questions (FAQ), technical support requests,online discussion groups, Microchip consultant program member listing
Business of Microchip Product selector and ordering guides, latest Microchip press releases,listing of seminars and events, listings of Microchip sales offices, distributors and factoryrepresentatives
Customer Change Notification Service
Microchips customer notification service helps keep customers current on Microchip products.Subscribers will receive e-mail notification whenever there are changes, updates, revisions or erratarelated to a specified product family or development tool of interest.
To register, access the Microchip web site at http://www.microchip.com/. Under Support, click onCustomer Change Notification and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support.Local sales offices are also available to help customers. A listing of sales offices and locations is includedin the back of this document.
Technical support is available through the web site at: http://www.microchip.com/support
AT24C64D
2018 Microchip Technology Inc. Datasheet DS20005937A-page 33
http://www.microchip.com/http://www.microchip.com/http://www.microchip.com/supportProduct Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Product Family24C = Standard I2C-compatible
Serial EEPROM
Device Density
Shipping Carrier Option
Device Grade or Wafer/Die Thickness
Package Option
64= 64 Kilobit
B = Bulk (Tubes)T = Tape and Reel, Standard Quantity OptionE = Tape and Reel, Extended Quantity Option
Operating VoltageM = 1.7V to 5.5V
H or U = Industrial Temperature Range (-40C to +85C)
11 = 11mil Wafer Thickness
SS = JEDEC SOICX = TSSOPMA = 2.0mm x 3.0mm UDFNME = 1.5mm x 2.0mm XDFNU = 6-ball, 2x3 Grid Array, WLCSPU2 = 4-ball, 2x2 Grid Array, WLCSPC = VFBGAWWU = Wafer Unsawn
A T 2 4 C 6 4 D - S S H M x x - B
Device Revision
Product Variation xx = Applies to select packages only.
Examples
Device Package PackageCode
Shipping Carrier Option Device Grade
AT24C64DSSHMB SOIC 8S1 Bulk (Tubes) IndustrialTemperature (-40C
to +85C)AT24C64DSSHMT SOIC 8S1 Tape and ReelAT24C64DXHMT TSSOP 8X Tape and ReelAT24C64DMAHMT UDFN 8MA2 Tape and ReelAT24C64DMAHME UDFN Extended Qty. Tape and ReelAT24C64DMEHMT XDFN 8ME1 Tape and ReelAT24C64DCUMT VFBGA 8U 21 Tape and ReelAT24C64DUUM0BT WLCSP 6U2 Tape and ReelAT24C64DU2UM0BT WLCSP 4U12 Tape and Reel
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
AT24C64D
2018 Microchip Technology Inc. Datasheet DS20005937A-page 34
Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the
market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of
these methods, to our knowledge, require using the Microchip products in a manner outside theoperating specifications contained in Microchips Data Sheets. Most likely, the person doing so isengaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their
code. Code protection does not mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving thecode protection features of our products. Attempts to break Microchips code protection feature may be aviolation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your softwareor other copyrighted work, you may have a right to sue for relief under that Act.
Legal Notice
Information contained in this publication regarding device applications and the like is provided only foryour convenience and may be superseded by updates. It is your responsibility to ensure that yourapplication meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORYOR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITSCONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE.Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in lifesupport and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend,indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resultingfrom such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectualproperty rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings,BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo,Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA,SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks ofMicrochip Technology Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLightLoad, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of MicrochipTechnology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom,chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController,dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit SerialProgramming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi,motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, OmniscientCode Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REALICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
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Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA aretrademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary ofMicrochip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies. 2018, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-2680-6
Quality Management System Certified by DNV
ISO/TS 16949Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and waferfabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in Californiaand India. The Companys quality system processes and procedures are for its PIC MCUs and dsPIC
DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory andanalog products. In addition, Microchips quality system for the design and manufacture of developmentsystems is ISO 9001:2000 certified.
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AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPECorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200Fax: 480-792-7277Technical Support:http://www.microchip.com/supportWeb Address:www.microchip.comAtlantaDuluth, GATel: 678-957-9614Fax: 678-957-1455Austin, TXTel: 512-257-3370BostonWestborough, MATel: 774-760-0087Fax: 774-760-0088ChicagoItasca, ILTel: 630-285-0071Fax: 630-285-0075DallasAddison, TXTel: 972-818-7423Fax: 972-818-2924DetroitNovi, MITel: 248-848-4000Houston, TXTel: 281-894-5983IndianapolisNoblesville, INTel: 317-773-8323Fax: 317-773-5453Tel: 317-536-2380Los AngelesMission Viejo, CATel: 949-462-9523Fax: 949-462-9608Tel: 951-273-7800Raleigh, NCTel: 919-844-7510New York, NYTel: 631-435-6000San Jose, CATel: 408-735-9110Tel: 408-436-4270Canada - TorontoTel: 905-695-1980Fax: 905-695-2078
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Worldwide Sales and Service
2018 Microchip Technology Inc. Datasheet DS20005937A-page 37
FeaturesPackagesTable of Contents1.Package Types (not to scale)2.Pin Descriptions2.1.Ground2.2.Device Addresses (A0, A1, A2)2.3.Serial Data (SDA)2.4.Serial Clock (SCL)2.5.Write-Protect (WP)2.6.Device Power Supply3.Description3.1.System Configuration Using 2-Wire Serial EEPROMs3.2.Block Diagram4.Electrical Characteristics4.1.Absolute Maximum Ratings4.2.DC and AC Operating Range4.3.DC Characteristics4.4.AC Characteristics4.5.Electrical Specifications4.5.1.Power-up Requirements and Reset Behavior4.5.1.1.Device Reset4.5.2.Pin Capacitance4.5.3.EEPROM Cell Performance Characteristics5.Device Operation and Communication5.1.Clock and Data Transition Requirements5.2.Start and Stop Conditions5.2.1.Start Condition5.2.2.Stop Condition5.3.Acknowledge and No-Acknowledge5.4.Standby Mode5.5.Software Reset6.Memory Organization6.1.Device Addressing6.1.1.Data Security7.Write Operations7.1.Byte Write7.2.Page Write7.3.Acknowledge Polling7.4.Write Cycle Timing7.5.Write Protection8.Read Operations8.1.Current Address Read8.2.Random Read8.3.Sequential Read9.Device Default Condition from Microchip10.Packaging Information10.1.Package Marking Information10.1.1.8S1 8-Lead JEDEC SOIC10.1.2.8X 8-lead TSSOP10.1.3.8MA2 8-Pad UDFN10.1.4.8U2-1 8-Ball VFBGA10.1.5.8ME1 8-Pad XDFN10.1.6.4U-12 4-Ball WLCSP10.1.7.6U-2 6-Ball WLCSP11.Revision HistoryThe Microchip Web SiteCustomer Change Notification ServiceCustomer SupportProduct Identification SystemMicrochip Devices Code Protection FeatureLegal NoticeTrademarksQuality Management System Certified by DNVWorldwide Sales and Service