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powerpoint presentation on IC 8155
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Subject: professionalpractice
Topic:8155-multipurpose
programmable device
INTRODUCTION TO 8155
The 8155 is a multipurpose programmable peripheral device.
It has a RAM & i/o ports built into itself
Internally latch is present
It is generally used to implement a minimum system with 8085 processor
block schematic OF 8155
A8155
256*8Static RAM
Timer
B
C
CE
IO/M
AD0-AD7
ALE
RD
WR
RESET
VCC (+5V)
PA 0-7
PB 0-7
PC 0-5
Timer in Timer out
GND (0V)
Pin diagram of 8155
Features
A 256 byte RAM 2 programmable 8 bit I/O ports 1 programmable 6 bit I/O port 1 programmable 14 bit binary
counter/timer Internal address latch to demultiplxed
AD0-AD7,using ALE line
Internal block diagram of 8155
Functions of blocksInternal latch: it is used to latch lower address
bus from data bus.
Internal decoder: it is used to select the ports and control reg.
CWR- it is used to select the ports in I/P or O/P mode.
Ports: they can be used in I/P or O/P mode depending upon data pattern written in the control register.
Registers of 8155
Port APort BPort CTimer RegisterControl RegisterStatus Register
Control word (command register) format:
D7 D6 D5 D4 D3 D2 D1 D0
Timer command IEB IEA PC PB PA
D0, D1: mode for PA and PB, 0=i/p, 1=o/p D2, D3: mode for PC D4, D5: interrupt enable for PA and PB, 0=disable 1=enable D6, D7: Timer command:
o 00: No effect o 01: Stop if running else no effect o 10: Stop after terminal count (TC) if running, else no effect o 11: Start if not running, reload at TC if running.
Port C bits (D2, D3):
ALT D3 D2 PC5 PC4 PC3 PC2 PC1 PC0
1 0 0 I I I I I I
2 1 1 O O O O O O
3 0 1 O O O STB - A BF-A INTR-A
4 1 0 STB-B BF-B INtR-B STB-A BF-A INTR-A
I - input O - output
Timer register
M2 M1 T15 T12 T11 T10 T9 T8
TIMER MODE MSB OF CNT LENGTH
T7 T6 T5 T4 T3 T2 T1 T0
LSB OF CNT LENGTH
AD0-AD7
IO/M
RD
WRALE
RESET OUTA15A14
A13
A12
A11
AD0-AD7
IO/M
RD Port A
WRALERESET Port B
Port C
CS
8085 8155
Interfacing of 8155
G2A G2B G1C
B
A
7654210
3:8decoder
Thank you