IBM System/360

Matt BabaianNathan Clark

Paul DesRochesJefferson Miner

Tara Sodano

The IBM System/360• The system’s architecture is still the basis for almost half the

current mainframe computers worldwide.

• The creation of the 360 line was an attempt to create a fully compatible line of processors capable of handling all jobs for all types of customers.

• Five processing units spanned the main part of the product line.

– System/360 Models 30, 40, 50, 65, and 75.

– They were all fully compatible which was an important part of their success.

• There would end up being 18 proposed models with 14 of them actually being produced and shipped.

Models:

30

40

50

60

62

70

92

91

20

65

75

95

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Memory and Registers

• IBM realized that one or more accumulators would be the only realistic starting point for high-speed machines.

• They also considered using multiple accumulators without increasing the instruction format by organizing the registers into a stack in which only the top register would ever be involved in arithmetic. – whenever a load instruction brought an operand from

memory to the top of the stack, operands already there would be “pushed down” one level. A store instruction would move the top number to memory and “push up” those at the second and lower levels.

Registers (con’t)

• 16 32-bit general registers

• 4 64-bit floating-point registers

• three ALUs– Fixed-point– decimal– Floating-Point

• Special Purpose Registers– Address register - the next memory location to be accessed– Instruction Register - the next instructionto be executed– Program Status Word - program counter– Data Register - data coming in from or going to memory, data from

inside the instruction

• Special Data Types– packed decimal– unpacked decimal– fixed point– floating point

Addressing Scheme• The 360 used position independent (the register plus either an

offset or an index) addressing modes.

• On of the strengths of the 360’s addressing was its compatibility.

– The 360 was designed with the current incompatibility of other IBM computers at that time.

• Programs designed for the IBM 7094 or the IBM 1401, two machines incompliant with each other, could run on the 360.

• It was a pioneer in this sense, but IBM’s decision to use 24 bits instead of 32 for addressing, proved in the long run to be unsatisfactory.

Memory Map

• Dr. Abzug “The memory map is horrible”

• Memory Map did not provide the user with adequate means for saving data

• IBM used the cheapest way to create their memory map

Instruction Set

• Five types of instruction formats

• RR - Register to Register

• RS - Register to Storage

• RX - Register to Indexed Storage

• SI - Storage Immediate

• SS - Storage to Storage

Instruction Set

• Instructions were broken up by these five instruction formats

• Within the formats, instructions are grouped by type of instruction

• Examples

60 nanoseconds

• Circuitry and hardware advances

• Advanced implementation techniques– pipelining– multiple functional units– interleaved memory with numerous buffers

Pipelining• the parallel execution of different instructions

• two independent functional units– fixed-point arithmetic– floating point arithmetic

• instruction-processing unit– generate the operand address– move the instruction to the decode area– decode the instruction– issue the instruction

Speed up instruction fetches

• 16 low order interleaved memory modules

• CPU had (64-bit) instruction fetch buffer

• two double-word branch target buffers

Conditional Branch Instructions

• CPU carry out instructions

• store them marked as conditional

• perform a test

• this provided execution parallelism

Instruction Unit

• determined each operand address

• generated memory instructions

• storage module– store instruction address

• queue in three store address buffers

– data • store data buffer

• appropriate operation buffer

Speed

A few interesting factors…

• MST(Monolithic Systems Technology) Circuits

• Number of Machine Cycles

• Innovative Cache (Local Storage)

Speed - MST Circuits

• Significantly faster than predecessor SLT

• Joe Logue - monolithic circuit development

• FET(Field Effect Transistors)

• MOS(Metal Oxide Silicon) Structure

Speed - Machine Cycles

• Reduce number with pipeline provisions

• n f-p additions perform in n + 1 cycles

• One f-p addition every three machine cycles

• Add & multiply units perform independently

• Addition and multiplication can be executed simultaneously

Speed - Cache

• Journal’s editor coins term cache for local storage

• 3-4 times faster than core memory technology

• Overlapped fetch can process 64 bytes of memory

• 16 byte data path & 4-way memory interleaving