IAR Embedded Workbench takes

RISC-V to the next level!

Hyun-Do Lee / FAE

Agenda

• IAR Systems

• Embedded Workbench for RISC-V

• Compiler

• Optimizations

• Debug

• I-jet

• Code quality and Safety

• Static analysis

• Certified toolchain

Providing developers of embedded systems

with world-leading software tools 36 years

in the industry

11 offices worldwide with HQ in

Uppsala, Sweden

Large ecosystem of partners

Global professional technical support in 9 languages

32% of revenue invested in R&D

Listed on

NASDAQ/

Stockholm Uppsala Munich Cambridge Paris Tokyo Seoul

Shanghai San Francisco Dallas Boston Los Angeles

+ Distributor representation in 43 countries

IAR Embedded Workbench for

RISC-V

IAR Embedded Workbench Complete build and debug toolchain for RISC-V

User-friendly IDE features and

broad ecosystem integration

Outstanding performance through

sophisticated optimization

technology

Comprehensive debugger

ISO/ANSI C/C++ compliance

with support for C18 and C++17

Integrated static analysis

IAR Embedded Workbench Device support for RISC-V

RV32I Base Int instruction set

Supported extensions:

M – integer mul & div

F – single precision float

D – double precision float

C – compressed instructions

Support for SiFive E Cores

32-bit embedded cores

Single core options

Out-of-the-box experience on

Xilinx Arty A7 35T/100T board.

IAR Embedded Workbench

RISC-V Instruction Set

Compiler

Compiler

• Proprietary design based on over 35 years of experience

• Based on a platform that is common among different targets to

handle global optimizations, etc.

• Target unique backend for specific adaptations and optimizations

• RISC-V specifics

• Primary focus will be on adding

standard extensions

• Initial prioritization is on code size

IAR C/C++ Compiler

Well-tested Commercial test suites Plum-Hall Validation test suite Perennial EC++VS Dinkum C++ Proofer

In-house developed test suite >500,000 lines of C/C++ test code run multiple times Processor modes Memory models Optimization levels

Language standards ISO/IEC 14882:2015

(C++14, C++17)

ISO/IEC 9899:2012 (C11)

ANSI X3.159-1989 (C89)

IEEE 754 standard for

floating-point arithmetic

Option to

maximize

speed with no

size

constraints

The linker can

remove unused

code

Multiple

optimizations

levels for code

size and

execution

speed

Balance between size

and speed by setting

different optimizations

for different parts of the

code

Major features of the

optimizer can be

controlled individually

Multi-file compilation allows

the optimizer to operate on a

larger set of code

• Our main focus have always been to supply

the best code size and speed on the market

• The RISC-V ISA is clean and straightforward.

That is probably one of the major factors that

have made it successful

Performance (1)

Code size

• Compared to more complex instruction sets RISC-V have

some challenges especially when it comes to size

• Arithmetic with higher resolution than the natural data size

yields larger code

• Absence of carry flags and instructions to save and

restore multiple registers are other examples

Code speed

• When it comes to speed, RISC-V is competitive

• Still, more speed optimizations to come in future versions

Performance(2)

Object Code

Optimizations C Source

Parser

Code Generator

Assembler

Compiler

Function

inlining

Dead code

elimination

Loop

unrolling

Peephole

Crosscall

Scheduling

Linker

High-Level Optimizer

Low-Level Optimizer LW A0,-0x0(GP)

C.ADDI A0,-0xF

SW A0,-0x4(GP)

Target Code

Intermediate Code

01001000111001101001

=

- x

y 15

x = y - 15;

Link time

optimizations

Speed, size or both?

Optimization

Common sub-expressions

Loop unrolling

Function inlining

Code motion

Dead code elimination

Static clustering

Instruction scheduling

Peephole

Effects

Speed ↑ Size ↓

Speed ↑ Size ↑

Speed ↑ Size ↑

Speed ↑ Size →

Speed → Size ↓

Speed ↑ Size ↓

Speed ↑ Size →

Speed ↑ Size ↓

Debug

Debug

• IAR Embedded Workbench for RISC-V offers

a fully integrated debug solution

• Built with the same C-SPY debugger interface

that is used in many of our products

• This includes the possibility to write debug

macros etc.

• Probes

• Our I-jet probes supports RISC-V

• Support for major 3rd party probes

will also be added

Debugger

Dockable

windows

and tab

groups

Integrated debugger for source

and disassembly debugging

Stack usage

Watch

Locals

Registers Semihosted

terminal I/O

Complex

breakpoints

C like macro system

Built-in simulator

RTOS aware

Trace

I-jet in-circuit debugging probe

• Supports RISC-V and Arm cores

• Hi-speed USB 2.0 interface (480Mbps)

• Target power of up to 400mA can be supplied from I-jet with

overload protection

• Target power consumption can be measured with ~200µA

resolution at 200kHz

• JTAG and Serial Wire Debug (SWD) clocks up to 32MHz

(no limit on the MCU clock speed)

• Support for SWO speeds of up to 60MHz

• Unlimited flash breakpoints (*to be added for RISC-V)

IAR C-SPY Debugger overview

IAR Embedded

Workbench C-SPY

Simulator

driver Simulator

I-jet

driver I-jet

Target

HW

IAR C-SPY Debugger

3rd party

driver

JTAG

Emulator

Target

HW

SDK

interface

Target system with application SW

IAR Systems

3rd party

RTOS

Awareness etc.

Code quality and

Functional Safety

CWE (the Common Weakness Enumeration): http://cwe.mitre.org/

CERT (Computer Emergency Response Team): http://www.cert.org/

Complete static analysis tool fully integrated in IAR Embedded Workbench

C-STAT Static analysis

• Intuitive and easy-to-use settings with

flexible rule selection

• Support for export/import of selected

checks

• Support for command line execution

• Extensive and detailed documentation

• List of messages and data base file

available

• Checks compliance with MISRA C:2004,

MISRA C++:2008 and MISRA C:2012

• Includes ~250 checks mapping to

hundreds of issues covered by CWE and

CERT C/C++

Standards IEC 61508 ISO 26262 EN 50128 IEC 62304

Solutions for safety-critical applications

• Certified toolchain* • A special functional safety edition of

IAR Embedded Workbench

• Simplified validation • Functional Safety certificate from TÜ V SÜ D

• Safety report from TÜ V SÜ D

• Safety Guide

• Guaranteed support through the product life cycle

• Prioritized support

• Validated service packs

• Regular reports of known problems *not available yet

Validated product versions

Validated version: IAR Embedded

Workbench for EWXXXFS x.xx.x Validated version y.yy

Validated service packs Validated service packs

Non-validated feature

releases x.xx.x

• For a certified product, a new certified version is released approximately

every 12-18 months

• A certified version is considered a ”frozen” version, on which bug fixes

are applied in terms of validated service packs

• No new product features are added to a certified version or the

corresponding service packs

Thank you for your attention!

www.iar.com