IA-64

Vincent D. Capaccio

IA-64 Overview

• Hewlett-Packard and Intel

• EPIC - Explicitly Parallel Instruction Computing

• 64-bit width

• Superscalar (Functional Units)

• Predication (Pre-computing branches)

• Speculation (Memory Hoisting)

EPIC

• Explicitly Parallel Instruction Computing

• Smaller instruction set then RISC.

• Room on chip for more functional units and registers.

• Relies on Compiler to extract parallelism.

Functional Units (Superscalar)

• Computations completed in Parallel

• 6 Arithmetic Logic Units (ALU’s)

• 6 Specialized Multimedia Functional Units

• 1 Floating-Point Functional Units

Registers

• 128 64-bit General Purpose Registers

r0-r31 are Static, r32-r127 are Dynamic

• 128 44-bit floating-Point Registers

f0-f31 are Static, f32-f127 are Dynamic

• 64 1-bit Predicate Registers

• 8 Branch Registers

• At least 5 CUPID Registers

Predication (Pre-computing branches)

• With x86 ISA - 20%-30% process performance is wasted on guessing which branch to take.

• IA-64 takes BOTH paths (NO guessing)

• Predicate registers are used to know which answer to throw away.

Speculation (Memory Hoisting)

• Speculation is used to try to eliminate memory latency

• IA-64 looks ahead in code are loads data before it is needed.

Questions?