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I350 REFERENCE DESIGN
J4J3
J2
J1H4H3
H2H1
D12C13
P3
N9N8N7N6
N5
N11N10
M5 M12
L6L11
K9K8K7
K10
J9J8J7J5
J12J10
H9H8H7
H10
G9G8
G12
G10
F9F8F7
F11F10
E9E8E7
E10
D7D10
B7B4
B13B10
A7A4
A13A10
L12
K5K12
H5H12
F5F12
L5
P8P11
M9M8M7M6
M10
C7C10
N12
M11
K6
K11
J6
J11
H6
H11
G6
G11
E6
E11
L14
L13K14
D9D8D6
D11
L9L8L7
L10
C11C9C6P2
P1
T1R2
K13
R1G15C12
A1A2
B2D4
C14D14E14F14
T2
C15B15B16C16
E16F15E15F16
C4
D15
P12P13
T14R14
T13R13
T12R12
P9P10
T11R11
T10R10
T9R9
T8R8
T7R7
P6P7
T6R6
T5R5
T4R4
P4P5
T3R3
G1F3F2F1
G2E3E2E1
F4D3D2D1
E4C3C2C1
T16T15P14N13
G16H14
J14H13
N14M14
J13M13
J16J15
L16L15
N16N15
R16R15
H16H15
K16K15
M16M15
P16P15
N4N3N2N1M4M3M2M1L4L3L2L1K4K3K2K1
G3E5
G4
E13
A5B5
A6B6
A11B11
A12B12
A3B3
A8B8
A9B9
A14B14
D16B1
A16A15
G13D13E12F13
2011-06-222.0323852-002I350 REFERENCE DESIGN 1DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
i350
NCSI_TX_EN
NCSI_TXD_1NCSI_TXD_0
NCSI_RXD_1NCSI_RXD_0
NCSI_CRS_DV
NCSI_CLK_OUTNCSI_CLK_IN
NCSI_ARB_OUTNCSI_ARB_IN
i350
VSS_N5VSS_M12VSS_M5
VSS_A4VSS_A7VSS_A10VSS_A13VSS_B4VSS_B7VSS_B10VSS_B13VSS_D7VSS_D10VSS_E7VSS_E8VSS_E9VSS_E10
VSS_F7VSS_F8VSS_F9VSS_F10VSS_F11
VSS_G8VSS_G9VSS_G10
VSS_G12VSS_H7VSS_H8VSS_H9
VSS_H10VSS_J5VSS_J7VSS_J8VSS_J9
VSS_J10VSS_J12
VSS_K7VSS_K8VSS_K9
VSS_K10VSS_L6
VSS_L11VSS_N6VSS_N7VSS_N8VSS_N9
VSS_N10VSS_N11
VSS_P3
i350
VCC1P0_N12
VCC1P0_ASE_L14VCC1P0_ASE_K14
VCC1P0_K11
VCC1P0_K6
VCC1P0_J11
VCC1P0_J6
VCC1P0_H11
VCC1P0_H6
VCC1P0_G11
VCC1P0_G6
VCC1P0_E11
VCC1P0_E6
VCC3P3_L12VCC3P3_K12VCC3P3_K5VCC3P3_H12VCC3P3_H5VCC3P3_F12VCC3P3_F5
VCC1P0_M11
VCC1P0_ASE_L13
VCC1P8_APE_C10VCC1P8_APE_C7
VCC3P3_AGE_L5
VCC1P0_APE_D11VCC1P0_APE_D9VCC1P0_APE_D8VCC1P0_APE_D6VCC3P3_A_P11
VCC3P3_A_P8VCC3P3_A_M10VCC3P3_A_M9VCC3P3_A_M8VCC3P3_A_M7VCC3P3_A_M6
VCC1P0_AGE_L10VCC1P0_AGE_L9VCC1P0_AGE_L8VCC1P0_AGE_L7
PE_TXVTERM4PE_TXVTERM3PE_TXVTERM1
i350
XTAL_CLK_OXTAL_CLK_I
SE_RSET
RSVD_TP_8RSVD_TE_VSSMAIN_PWR_OK
LAN_PWR_GOOD
LAN3_DIS_NLAN2_DIS_NLAN1_DIS_NLAN0_DIS_N
AUX_PWR
PE_TRIM2
PE_TRIM1
RSVD_TX_TCLK
GE_REXT3K
TSENSZTSENSP
FLSH_SOFLSH_SI
FLSH_SCKFLSH_CE_N
EE_SKEE_DOEE_DI
EE_CS_N
DEVICE_OFF_N
i350
LED3_3
LED3_1LED3_2
LED3_0
MDI3_3_n
MDI3_2_n
MDI3_3_p
MDI3_1_n
MDI3_2_p
MDI3_1_p
MDI3_0_nMDI3_0_p
LED2_3
LED2_1LED2_2
LED2_0
MDI2_3_n
MDI2_2_n
MDI2_3_p
MDI2_2_p
MDI2_1_nMDI2_1_p
MDI2_0_pMDI2_0_n
LED1_3
LED1_1LED1_2
LED1_0
MDI1_3_n
MDI1_2_n
MDI1_3_p
MDI1_1_n
MDI1_2_p
MDI1_1_p
MDI1_0_pMDI1_0_n
LED0_3LED0_2LED0_1LED0_0
MDI0_3_nMDI0_3_p
MDI0_2_nMDI0_2_p
MDI0_1_nMDI0_1_p
MDI0_0_nMDI0_0_p
i350
SET3_PSET3_N
SET2_PSET2_N
SET1_PSET1_N
SET0_PSET0_N
SER3_PSER3_N
SER2_PSER2_N
SER1_PSER1_N
SER0_PSER0_N
SDP3_3SDP3_2SDP3_1SDP3_0
SDP2_3SDP2_2SDP2_1SDP2_0
SDP1_3SDP1_2SDP1_1SDP1_0
SDP0_3SDP0_2SDP0_1SDP0_0
SRDS_3_SIG_DETSRDS_2_SIG_DETSRDS_1_SIG_DETSRDS_0_SIG_DET
SFP1_I2C_DATA
SFP0_I2C_DATA
SFP2_I2C_CLK
SFP1_I2C_CLK
SFP0_I2C_CLK
SFP3_I2C_DATA
SFP2_12C_DATA
SFP3_12C_CLK
i350
SMBDSMBCLK
SMBALRT_N
RSVD_JRST_3P3
JTAG_TMSJTAG_TDOJTAG_TDIJTAG_TCK
PE_WAKE_N
PER_0_n PET_0_n
PET_1_nPER_1_n
PER_2_n PET_2_n
PET_3_nPER_3_n
PE_RST_N
PE_CLK_pPE_CLK_n
PER_0_p PET_0_p
PET_1_pPER_1_p
PER_2_p PET_2_p
PET_3_pPER_3_p
2.00 - RELEASED1.00 - PRELIMINARY0.95 - SVR & TSENS PIN CHANGEREVISION CONTROL
161718
9101112131415
PAGE
TOC123
6
87
TITLE
TABLE OF CONTENTSCONTENTS
54
BLOCK DIAGRAMPCIE - SMB - JTAG
3P3 BUCK-BOOST
MDI - PORT_2 & PORT_4SFP POWER
MDI - PORT_0 & PORT_3
SUPPORT CIRCUITS POWER SUPPLIES POWER SUPPLY TREE POWER MUX POWER SUPPLY, 12P0-3P3
INTEGRATED 1P0-SVR & 1P8 LVR
NC-SI TEST (RJ45 & CLK)NC-SI TEST (PHY) NC-SI - I350
SFP
I350 REFERENCE DESIGN 2011-06-222.0323852-002 2DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
DYNAMICALLY THROUGH A REGISTER SETTING.
SWITCHED TO EITHER THE BASE-T INTERFACE OR THE SERDES INTERFACE.CONNECTED TO 4 PCIE FUNCTIONS. EACH PCIE FUNCTION CAN BETHE I350 HAS 4 BASE-T INTERFACES AND 4 SERDES INTERFACES
THE SWITCH IS CONFIGURED WITH A STATIC EEPROM SETTING OR
2011-06-222.0323852-002I350 REFERENCE DESIGN 3DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
PCIE - SMB - JTAG
CONNECTORPCIE2 X4 (4,2,1) 10W
21
F3
2
1F2
21
F1
2
1R260
21
R183
21R187
21
R180
R168
R83
R165
R167R169
C180
C179
C178C177
C176C175
C174C173
R186
R185
R184
R182
R181
2
1R233
2
1R159
2
1R152
21R1
58
21R1
55
B11
B6B5
A32
A19
B30
B12A13A14
B31
B17
A1
B27
B23
B19
B14
B28
B24
B20
B15
A11
A29
A25
A21
A16
A30
A26
A22
A17
A8A7A6A5
B9
B26B25
B22B21
B18
A31
A28A27
A24A23
B16
A20
A18
A15
A12
A4
B13
B7
B32
B29
B4
B10A10A9
B8
A3A2
B3B2B1
J42
G3E5
G4
E13
A5B5
A6B6
A11B11
A12B12
A3B3
A8B8
A9B9
A14B14
D16B1
A16A15
G13D13E12F13
U7
10.0K10.0K
10.0K
4
V12P0_PE_MAIN_UNFUSED
PE_RSVD_5
PER_2_N
PE_RSVD_3
PE_RST_N
0.1UF0.1UF
0.1UF
0.1UF0.1UF
0.1UF0.1UF
10.0K
10.0K
EMPTY0
EMPTY0
EMPTY0
EMPTY0
V3P3_LAN_SUPPORT
PE_JRST
LAN_PET_0_P
LAN_PET_1_NLAN_PET_1_P
LAN_PET_2_P
LAN_PET_3_PLAN_PET_3_N
LAN_PET_2_N
JRST
I350 REFERENCE DESIGN
SMB_ALRT_N
SMB_CLK
PE_CLK_P
PE_RST_N
PE_WAKE_N
PER_3_P
PER_1_P
V3P3_LAN_SUPPORT
PE_PRESENT_10EMPTY
0
0 EMPTYPE_PRESENT_2_X1 PE_PRESENT_1
10.0K
EMPTY
SMB_DATA
EMPT
Y0 0EM
PTY
2011-06-222.0323852-002
JTMSJTDO
JTCK
PER_0_N LAN_PET_0_N
PER_1_N
PER_3_N
PER_0_P
PER_2_P
PE_RSVD_2
IC
V3P3_PE_AUX
PET_3_N
PE_SMB_DATAPE_SMB_CLK
PE_CLK_N
V3P3_PE_MAIN_UNFUSED
V12P0_PE_MAIN
PET_3_P
PET_2_NPET_2_P
PET_1_NPET_1_P
PET_0_NPET_0_P
PE_RSVD_4
PE_JTCKPE_JTDIPE_JTDOPE_JTMS
PE_JRST
PE_WAKE_NV3P3_PE_AUX_UNFUSED
PE_PRESENT_2_X4 PE_PRESENT_1
JTDIPE_CLK_N
10.0K 10.0K 10.0K
PE_CLK_P
0
IC IC
V3P3_PE_MAIN
DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
IN
IN
OUT
ININ
OUTOUT
OUT
FCONN64K_PCI_ExpressX4_1P1
KEY
RSVD5
RSVD4
12V312V2
PRSNT1A_N12V412V5GND35JTAG2JTAG3JTAG4
3_3V2JTAG5
PERST*3_3V3
GND36REFCLKP
PERP<0>
REFCLKNGND37
GND38PERN<0>
GND39PERP<1>PERN<1>GND40GND41PERP<2>
GND42PERN<2>
GND43PERP<3>PERN<3>GND44
12V1
GND1SMCLKSMDAT
GND2
JTAG13_3V1
WAKE_N3_3VAUX
GND3RSVD2
PETN<0>PETP<0>
GND4
GND5PRSNT2_N
PETN<1>PETP<1>
GND6GND7
GND8
PETP<2>PETN<2>
PETP<3>GND9
PETN<3>
RSVD3GND10
GND11PRSNT2A_N
i350
SMBDSMBCLK
SMBALRT_N
RSVD_JRST_3P3
JTAG_TMSJTAG_TDOJTAG_TDIJTAG_TCK
PE_WAKE_N
PER_0_n PET_0_n
PET_1_nPER_1_n
PER_2_n PET_2_n
PET_3_nPER_3_n
PE_RST_N
PE_CLK_pPE_CLK_n
PER_0_p PET_0_p
PET_1_pPER_1_p
PER_2_p PET_2_p
PET_3_pPER_3_p
CONNECT LED2 TO CATHODE OF GREEN SPEED LED AND THE ANODE OF THE ORANGE SPEED LED.
CONNECT LED3 TO CATHODE OF ORANGE SPEED LED AND THE ANODE OF THE GREEN SPEED LED.
THE MDI INTERFACE ON THE I350 IS INTERNALLY TERMINATED.
EXTERNAL MDI TERMINATION IS NOT REQUIREDTHE SYSTEM SIDE CENTER TAP IS NOTCONNECTED TO A VOLTAGE ON THE I350.THE MDI INTERFACE IS INTERNALLY BIASED
CONNECTED TO A VOLTAGE ON THE I350.
THE DUAL PORT SKU: I350DB
MDI 10BASE-T/100BASE-TX/1000BASE-T
THE MDI INTERFACE IS INTERNALLY BIASED
THE SYSTEM SIDE CENTER TAP IS NOT
PORTS 2 AND 3 CAN BE LEFT UNCONNECTED ON
LED3->IF LINKED AT 1000BASE-T THEN LOW
LED2->IF LINKED AT 100BASE-TX THEN LOW
CONNECT LED1 TO ANODE OF LINK/ACTIVITY LEDLED1->NORMALLY HIGH, BLINKS LOW FOR FILTERED ACTIVITY.
CONNECT LED0 TO CATHODE OF GREEN LINK/ACTIVITY LEDLED0->LINK UP IS LOW, LINK DOWN IS HIGH.
1
J24
R270
R272
R240
R241
21 R195
21 R194
21 R192
21 R193
21C124
21C167
21
C158
21C168
21C171
21C149
21
C107
21
C121
21
C106
21
C102
2423
222120
191817
161514
13
9
876
543
2
12
1110
1U22
21 R115
21 R113
21 R277
21 R276
21 R278
21 R103
21 R101
2
1C12
21 R275
21C20
2
1C23
2
1C14
2
1C25
2
1 C18
2
1 C29
2
1 C30
2
1 C19
21C93
21R199
21R198
21R197
21 R196
21 R11921 R107
21 R10821 R120
P12P13
T14R14
T13R13
T12R12
P9P10
T11R11
T10R10
T9R9
T8R8
T7R7
P6P7
T6R6
T5R5
T4R4
P4P5
T3R3
G1F3F2F1
G2E3E2E1
F4D3D2D1
E4C3C2C1
U7
2423
222120
191817
161514
13
9
876
543
2
12
1110
1U17
C7C8
C4C5
C3
C6
C1C2
C12C11C10
C9
J34
S5S4S3S2S1
A7A8
A4A5
A3
A6
A1A2
A12A11A10
A9
J34
5
GND_EARTH_S5
RJ_LED_2_0
MDI_1_0_PMDI_1_0_N
MDI_1_1_PMDI_1_1_N
MDI_1_3_P
MDI_0_1_P
LED_1_3
MDI_0_3_N
160
MDI_2_0_PMDI_2_0_N
MDI_2_1_P
0.1UF
0.1UF
2011-06-222.0323852-002I350 REFERENCE DESIGN
LED_3_3
LED_3_1LED_3_2
LED_3_0
MDI_3_3_N
MDI_3_2_N
MDI_3_3_P
MDI_3_1_N
MDI_3_2_P
MDI_3_1_P
MDI_3_0_NMDI_3_0_P
LED_1_1LED_1_2
LED_1_0
MDI_1_3_N
MDI_1_2_NMDI_1_2_P
1.0UF
0.1UF
0.1UF
RJ_MDI_0_3_PRJ_MDI_0_3_N
RJ_MDI_0_0_PRJ_MDI_0_0_N
MDI_0_1_N
LED_0_0
GND_EARTH_S5
0.1UF0.1UF 0.1UF 0.1UF
0
0
0
0
1808LF1000PF
75
75
75
75
TERM_PLANE_0
LCT_0_1
MDI_0_2_P
LCT_0_3
LCT_0_0MDI_0_0_N
MDI_0_2_N
SCT_0
MDI_0_3_P
MDI_0_0_P
LED_2_3LED_2_2LED_2_1LED_2_0
MDI_2_3_NMDI_2_3_P
MDI_2_1_N
MDI_2_2_PMDI_2_2_N
0.1UF0.1UF0.1UF0.1UF
0
0
0 RJ_LED_2_2RJ_LED_2_3
RJ_LED_2_10
1808LF1000PF
RJ_MDI_2_2_PRJ_MDI_2_2_NRJ_MDI_2_1_N
75
75
75
75
TERM_PLANE_2
R_LED_2_3160
160160
160R_LED_2_0
R_LED_2_2R_LED_2_1
0.1UF
0.1UF
SCT_2
1.0UF
0.1UF
0.1UF
160
LED_0_1
LED_0_3LED_0_2
160
160
RJ_MDI_2_0_PRJ_MDI_2_0_NRJ_MDI_2_1_P
RJ_MDI_2_3_PRJ_MDI_2_3_N
RJ_LED_0_1
RJ_LED_0_0
RJ_LED_0_2
R_LED_0_2
RJ_MDI_0_1_PRJ_MDI_0_2_PRJ_MDI_0_2_NRJ_MDI_0_1_N
RJ_LED_0_3
NC_GND_3
NC_GND_2
NC_GND_1
LCT_0_2
LCT_2_0
LCT_2_1
LCT_2_3
R_LED_0_1
R_LED_0_3
R_LED_0_0
LCT_2_2
DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
C6
C11
C12
C8
L16
L15
C9
C10
L13
L14
L18C7
L17
C3
L24
L19
C5
C4
L20
L21
L22
L23C2
C1
C6
C11
C12
C8
L16
L15
C9
C10
L13
L14
L18C7
L17
C3
L24
L19
C5
C4
L20
L21
L22
L23C2
C1
3 OF 4
CONN24_E74273_001
LED_LINK_2_GC_OALED_LINK_2_GA_OCLED_ACT_2_GCLED_ACT_2_GARJ_2_3_NRJ_2_3_PRJ_2_1_NRJ_2_2_NRJ_2_2_PRJ_2_1_PRJ_2_0_NRJ_2_0_P
1 OF 4
CONN24_E74273-001
LED_LINK_0_GC_OALED_LINK_0_GA_OCLED_ACT_0_GCLED_ACT_0_GARJ_0_3_NRJ_0_3_PRJ_0_1_NRJ_0_2_NRJ_0_2_PRJ_0_1_PRJ_0_0_NRJ_0_0_P
SHIELD5SHIELD4SHIELD3SHIELD2SHIELD1
OUTOUTOUTOUT
OUTOUTOUTOUTOUTOUTOUTOUT
OUTOUTOUTOUTOUTOUTOUTOUT
OUTOUTOUTOUT
E55508_001_bracket
IO1
i350
LED3_3
LED3_1LED3_2
LED3_0
MDI3_3_n
MDI3_2_n
MDI3_3_p
MDI3_1_n
MDI3_2_p
MDI3_1_p
MDI3_0_nMDI3_0_p
LED2_3
LED2_1LED2_2
LED2_0
MDI2_3_n
MDI2_2_n
MDI2_3_p
MDI2_2_p
MDI2_1_nMDI2_1_p
MDI2_0_pMDI2_0_n
LED1_3
LED1_1LED1_2
LED1_0
MDI1_3_n
MDI1_2_n
MDI1_3_p
MDI1_1_n
MDI1_2_p
MDI1_1_p
MDI1_0_pMDI1_0_n
LED0_3LED0_2LED0_1LED0_0
MDI0_3_nMDI0_3_p
MDI0_2_nMDI0_2_p
MDI0_1_nMDI0_1_p
MDI0_0_nMDI0_0_p
MDI 10BASE-T/100BASE-TX/1000BASE-T
EXTERNAL MDI TERMINATION IS NOT REQUIRED
LED1->NORMALLY HIGH, BLINKS LOW FOR FILTERED ACTIVITY.
CONNECT LED2 TO CATHODE OF GREEN SPEED LED AND THE ANODE OF THE ORANGE SPEED LED.
CONNECT LED3 TO CATHODE OF ORANGE SPEED LED AND THE ANODE OF THE GREEN SPEED LED.
CONNECTED TO A VOLTAGE ON THE I350.THE SYSTEM SIDE CENTER TAP IS NOT
THE MDI INTERFACE IS INTERNALLY BIASED
LED0->LINK UP IS LOW, LINK DOWN IS HIGH.
LED2->IF LINKED AT 100BASE-TX THEN LOW
HEATSINK
CONNECT LED0 TO CATHODE OF GREEN LINK/ACTIVITY LED
CONNECT LED1 TO ANODE OF LINK/ACTIVITY LED
LED3->IF LINKED AT 1000BASE-T THEN LOWTHE MDI INTERFACE IS INTERNALLY BIASEDCONNECTED TO A VOLTAGE ON THE I350.THE SYSTEM SIDE CENTER TAP IS NOT
THE MDI INTERFACE ON THE 82580 IS INTERNALLY TERMINATED.
C7
21
21 R106
C37
C10
21 R102
21C21
21C32
21C40
21 R82
2
1 C17
2
1 C28
2
1 C24
2
1 C13
R245
R244
B7B8
B4B5
B3
B6
B1B2
B12B11B10
B9
J34
21 R79
21 R81
21 R114
21 R118
2423
222120
191817
161514
13
9
876
543
2
12
1110
1
U5
21 R80
21
R200
R201
C50
21C47
21C64
21C53
21C31
21 R11621 R104
21 R117
21 R171
21 R172
21 R173
21 R174
21 R105
2
1 C16
2
1 C27
2
1 C26
R279
R280
R274
2
1 C15
R273
2423
222120
191817
161514
13
9
876
543
2
12
1110
1
U10
D7D8
D4D5
D3
D6
D1D2
D12D11D10
D9
J3421C67
6
0402LF
R_LED_1_0R_LED_1_1R_LED_1_2
10%
RJ_MDI_1_0_PRJ_MDI_1_0_N
TERM_PLANE_1
2011-06-222.0323852-002I350 REFERENCE DESIGN
1000PF X7R 1808LF
RJ_MDI_3_0_N
0402LF
5%
0.1UF
10%
0402LF
1/16W
75
10%X5RX5RX5R
1/16W
GND_EARTH_S5
0.1UF
MDI_1_3_N
MDI_1_3_P
0.1UF
SCT_1
1.0UF
0.1UF
LCT_1_3
LCT_1_1
LCT_1_2
LCT_1_0
0.1UF
MDI_1_2_NMDI_1_2_P
MDI_1_1_NMDI_1_1_P
75
75
75
0.1UF
0402LF
TERM_PLANE_3
01/16W
RJ_LED_1_1
160
75 5%0402LF 0402LF
RJ_LED_3_3
R_LED_3_1
1/8W
CHIP
MDI_1_0_N
LED_1_0160
MDI_3_0_NMDI_3_0_P
1808LF10%1000PF
10%
0
CHIP
MDI_3_2_NMDI_3_2_P
MDI_3_3_NMDI_3_3_P
MDI_3_1_NMDI_3_1_P
R_LED_3_3
R_LED_3_0
SCT_3
R_LED_3_2
RJ_LED_3_1
RJ_LED_3_2
CHIP 0402LF1601/16W 5%
0402LF1/16W 5% CHIP160
0.1UF
0.1UF
0.1UF
1.0UF0402LF10% X5R
CHIP5%1601/16W 0402LF
1/16W 160 5% CHIP 0402LF
LCT_3_3
LCT_3_2
LCT_3_1
LCT_3_0
0.1UF
0805LF CHIP
5% 0805LF1/8W CHIP75
1/8W 5%75 0805LF
75 0805LF5% CHIP1/8W
10%
0.1UF
X5R
0402LF
1/16W 0CHIP0603LF5%
0CHIP5% 0603LF
1/16W
10%
0.1UF
X5R X5R10%
0.1UF
CHIP0603LF5%1/16W 0
5%0603LF CHIP
RJ_LED_1_2
RJ_LED_1_3
00603LF
0.1UF
5%
0603LF
160
CHIP
X5R
1/16W 5%00603LF
0CHIP 0603LF
1/16W 5%CHIP
10%
160
0.1UF
X5R
0402LF
MDI_1_0_P
RJ_LED_1_0
10%
0.1UF
X7R
RJ_MDI_3_1_P
RJ_MDI_3_2_N
RJ_MDI_3_3_PRJ_MDI_3_3_N
RJ_MDI_1_1_PRJ_MDI_1_2_PRJ_MDI_1_2_NRJ_MDI_1_1_NRJ_MDI_1_3_PRJ_MDI_1_3_N
R_LED_1_3LED_1_3LED_1_2LED_1_1
LED_3_0LED_3_1LED_3_2LED_3_3
RJ_LED_3_0
RJ_MDI_3_1_N
RJ_MDI_3_2_P
RJ_MDI_3_0_P
DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
HS_OPLIN
IO1IO2
ININ
IN
IN
ININ
ININ
ININ
2 OF 4
CONN24_E74273_001
LED_LINK_1_GC_OALED_LINK_1_GA_OCLED_ACT_1_GCLED_ACT_1_GARJ_1_3_NRJ_1_3_PRJ_1_1_NRJ_1_2_NRJ_1_2_PRJ_1_1_PRJ_1_0_NRJ_1_0_P
IN
IN
C6
C11
C12
C8
L16
L15
C9
C10
L13
L14
L18C7
L17
C3
L24
L19
C5
C4
L20
L21
L22
L23C2
C1
IN
ININ
C6
C11
C12
C8
L16
L15
C9
C10
L13
L14
L18C7
L17
C3
L24
L19
C5
C4
L20
L21
L22
L23C2
C1
IN
ININ
ININ
4 OF 4
CONN24_E74273_001
LED_LINK_3_GC_OALED_LINK_3_GA_OCLED_ACT_3_GCLED_ACT_3_GARJ_3_3_NRJ_3_3_PRJ_3_1_NRJ_3_2_NRJ_3_2_PRJ_3_1_PRJ_3_0_NRJ_3_0_P
ININ
ININ
SFP MODULES MAY NEED TO BE SHUT DOWN WHILE IN LOW POWER STATESTHESE FETS ALLOW SOFTWARE TO CONTROL THE SFP MODULE POWER.
SFP_1 POWER CONTROL
SFP_3 POWER CONTROL
SFP_0 POWER CONTROL
SFP_2 POWER CONTROL
21R204
21R203
21R191
21R202
2
1
3
Q32
1R135
2
1 C113
2
1 C119
2
1R136
2
1R219
2
1
3
Q22
1R133
2
1 C114
2
1 C120
2
1R134
2
1R222
2
1R111
2
1
3
Q1
2
1 C111
2
1 C117
2
1R112
2
1R232
2
1R218
2
1 C112
2
1R110
2
1
3
Q4 2
1 C118
2
1R109
7
V3P3_LAN_SUPPORT
SFP_1_PFET_S
SI2301BDS
0.1UF
3.3K
SFP_3_POWER
1206LF
V3P3_SFP_1
1/2WCHIP
1206LF
1206LF
01%1/2WEMPTY
01%1/2WEMPTY
1206LF
1/2WEMPTY
01%
1/2W1%
1206LF
0
EMPTY
SFP_0_POWER
10UF
2011-06-222.0323852-002I350 REFERENCE DESIGN
SFP_3_PFET_S
SI2301BDS
SFP_1_POWER
0
SFP_2_POWER
0
3.3K
0
3.3K
0
3.3K
SI2301BDS
10UF
1206LF
CHIP1/2W
V3P3_LAN_SUPPORT
V3P3_SFP_3V3P3_SFP_2
V3P3_LAN_SUPPORT
SFP_2_PFET_S
0
0.1UF
0.1UF
1/2WCHIP
1%0
1206LF
10UF
0.1UF
1%
V3P3_LAN_SUPPORT
SI2301BDS
V3P3_SFP_0
01%
SFP_0_PFET_S
10UF
CHIP1/2W
1206LF
01%
DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
D
S
FET_P
GIND
S
FET_P
G
D
S
FET_P
G
IN
IND
S
FET_P
GIN
SHOULD BE AC CAPS ON RXNOTE: SERDES RESISTORS
BACKPLANE DESIGNSFOR BX & KX DESIGNS
CONNECTIONS AREUSED IN STANDARDINTEL SOFTWAREOTHER CONNECTIONSREQUIRE CUSTOMIZED
SDPX_1 REMAINS AN INPUT IN D3
THESE SDP
SOFTWARENOTE:
REQUIRE AC COUPLING
THE DUAL PORT SKU: I350DBPORTS 2 AND 3 CAN BE LEFT UNCONNECTED ON
BY THE ILOS BIT IN THE EEPROM.
THE POLARITY OF SIG_DET CAN BE CONTROLED
SFP
SFP_V3P3_R_0
SFP_T_0_N
1/2W
GND_SFP_CAGE
8
SFP_TX_DISABLE_2 R40 510R32 510SFP_TX_DISABLE_3
510R55SFP_TX_DISABLE_1R29 510SFP_TX_DISABLE_0
R57 3.3K
R164.7UF
K1
K4
V3P3_SFP_3
L73.3UHIND
C840.1UF
R225
R226
R236
R22421
R76
R15R33R48
R59R34R25
R27R42R67
R17R30R44
R84R85
R88R89
R92R93
R96R97
R87R86R91R90R95R94R99R98
C96 C95 C82 C79
L4 L5
C81 C80
R60
R47
R26
R18R19
R68
R69
20
17
1
14
11 10
1615
2319
1845
89
7
1213
6
G9G8G7G6G5G4G3
G20
G2
G19G18G17G16G15G14G13G12G11
G10
G1
J11
C101 C100 C77 C76
L8 L9
C78 C75
R45
R56
R58
R65
R43
20
17
1
14
11 10
1615
2319
1845
89
7
1213
6
G9G8G7G6G5G4G3
G20
G2
G19G18G17G16G15G14G13G12G11
G10
G1
J12
C99 C94 C86
L11
C85 C83
R28
R13
R14
R39R53
R52
R38
20
17
1
14
11 10
1615
2319
1845
89
7
1213
6
G9G8G7G6G5G4G3
G20
G2
G19G18G17G16G15G14G13G12G11
G10
G1
J9
R54R66
R41
R24
R62R51
R46
C89C91C88C90C97C98
L6 L10
20
17
1
14
11 10
1615
2319
1845
9
7
1213
6
G9G8G7G6G5G4G3
G20
G2
G19G18G17G16G15G14G13G12G11
G10
G1
J10
T16T15P14N13
G16H14
J14H13
N14M14
J13M13
J16J15
L16L15
N16N15
R16R15
H16H15
K16K15
M16M15
P16P15
N4N3N2N1M4M3M2M1L4L3L2L1
K3K2
U7
8
SFP_R_1_NSFP_R_1_P
SFP_T_1_N
SFP_T_2_P
SFP_TX_DISABLE_0SFP_TX_FAULT_0
SFP_MOD_ABS_1SFP_TX_DISABLE_1
SFP_MOD_ABS_2
SFP_TX_DISABLE_3
GND_SFP_CAGE
SFP_SDA_0
SER_3_NSER_3_P
SER_2_N
0.1UF
IND
V3P3_LAN_SUPPORT
SFP_V3P3_R_3
3.3UH
GND_SFP_CAGE
V3P3_LAN_SUPPORT
SFP_RS1_0
SFP_RX_LOS_0
SFP_RS0_0
2011-06-222.0323852-002I350 REFERENCE DESIGN
SER_1_PSER_1_N
SFP_SDA_3
IND3.3UH
V3P3_SFP_1
GND_SFP_CAGE
SFP_TX_FAULT_0
0
8.2K
SFP_3_POWERSFP_TX_FAULT_3
SFP_MOD_ABS_3
SDP_2_3
SFP_RX_LOS_1SFP_RX_LOS_2
SFP_RX_LOS_0
SFP_SDA_2 3.3K
SFP_SCL_1SFP_SDA_1
SFP_SCL_2SFP_SDA_2
SFP_SCL_3
SFP_SCL_2
0
0
8.2K
3.3K
8.2K
8.2K
0
0
3.3K
8.2K
8.2K
8.2KSFP_TX_FAULT_3
V3P3_LAN_SUPPORT
SFP_T_0_PSFP_T_0_N
SFP_T_1_P
SFP_TX_FAULT_2SFP_TX_DISABLE_2
SFP_1_POWERSFP_TX_FAULT_1
SFP_0_POWER
SFP_MOD_ABS_0
0
0
0
0
SDP_0_3SDP_1_0
SDP_1_2SDP_1_3
SDP_2_2
SDP_3_0SDP_3_1
SDP_3_3
SFP_TX_FAULT_2
SFP_RX_LOS_2
SFP_RS1_2
SFP_R_3_N
SFP_R_2_P
GND_SFP_CAGE
SER_0_P
SET_3_P
0
SFP_T_3_NSFP_T_3_P
SFP_V3P3_T_3
SFP_R_3_P
SFP_T_1_PSFP_T_1_N
SFP_T_3_NSFP_T_3_P
SFP_T_2_N
0
IND
SFP_SCL_0
SFP_MOD_ABS_0
SER_0_N
0.1UF
4.7UF
SFP_R_1_N
SFP_R_2_N
4.7UF4.7UF4.7UF4.7UF
4.7UF4.7UF
3.3UH
0.1UF
IND3.3UH
IND3.3UH
V3P3_SFP_2
SFP_V3P3_T_0
SFP_R_0_P
0
0
SFP_R_0_P
0
V3P3_SFP_0
0
1206LF
SFP_R_3_P
00
0000
0000
00
0
0
0
0
0.1UF 0.1UF 0.1UF 0.1UF
0.1UF 0.1UF
GND_SFP_CAGEGND_SFP_CAGEGND_SFP_CAGE
0
0
0
00
0
IND3.3UH
0.1UF0.1UF0.1UF
SFP_T_0_P
SFP_T_2_NSFP_T_2_P
SFP_V3P3_T_2SFP_V3P3_R_2
SFP_R_2_PSFP_R_2_N
SFP_R_0_NSFP_R_1_P
SFP_R_0_N
SFP_RX_LOS_3
SDP_0_2
SDP_1_1
SDP_2_1
SDP_3_2
SER_2_P
SET_1_N
3.3KSFP_SDA_0
0.1UF
SET_0_PSET_0_NSET_1_P
SET_2_PSET_2_N
3.3UH
8.2K
0
8.2K
SDP_0_0
SET_3_N
SFP_V3P3_T_1SFP_V3P3_R_1
SFP_TX_FAULT_1
SFP_SDA_1
SFP_RS0_1
SFP_RS1_1
V3P3_LAN_SUPPORT
SFP_RX_LOS_1
8.2K
0
0
3.3K
8.2K
8.2K
3.3K0.1UF
IND
SDP_0_10
0.1UF
SFP_2_POWER
GND_SFP_CAGE
SDP_2_0
SFP_SCL_1
SFP_MOD_ABS_1
3.3KSFP_SDA_3SFP_SCL_3
SFP_MOD_ABS_3
SFP_RS0_3
SFP_RX_LOS_3
SFP_RS1_3SFP_R_3_N
SFP_SCL_0
SFP_RS0_2
SFP_MOD_ABS_2
DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
CHASSIS GND
SCONN20_SFP
VEER_11
RX_LOS
RS1
VEER_10
RS0
MOD-ABS
SCLSDA
TX_DISABLETX_FAULT
VEET_1
RD-RD+
VEER_14
VCCR_15VCCT_16
VEET_17
TD+TD-
VEET_20
CGND_20
CGND_18CGND_19
CGND_17CGND_16CGND_15
CGND_13CGND_14
CGND_12CGND_11
CGND_9CGND_10
CGND_8
CGND_6CGND_7
CGND_5CGND_4CGND_3
CGND_1CGND_2
CHASSIS GND
SCONN20_SFP
VEER_11
RX_LOS
RS1
VEER_10
RS0
MOD-ABS
SCLSDA
TX_DISABLETX_FAULT
VEET_1
RD-RD+
VEER_14
VCCR_15VCCT_16
VEET_17
TD+TD-
VEET_20
CGND_20
CGND_18CGND_19
CGND_17CGND_16CGND_15
CGND_13CGND_14
CGND_12CGND_11
CGND_9CGND_10
CGND_8
CGND_6CGND_7
CGND_5CGND_4CGND_3
CGND_1CGND_2
CHASSIS GND
SCONN20_SFP
VEER_11
RX_LOS
RS1
VEER_10
RS0
MOD-ABS
SCLSDA
TX_DISABLETX_FAULT
VEET_1
RD-RD+
VEER_14
VCCR_15VCCT_16
VEET_17
TD+TD-
VEET_20
CGND_20
CGND_18CGND_19
CGND_17CGND_16CGND_15
CGND_13CGND_14
CGND_12CGND_11
CGND_9CGND_10
CGND_8
CGND_6CGND_7
CGND_5CGND_4CGND_3
CGND_1CGND_2
CHASSIS GND
SCONN20_SFP
VEER_11
RX_LOS
RS1
VEER_10
RS0
MOD-ABS
SCLSDA
TX_DISABLETX_FAULT
VEET_1
RD-RD+
VEER_14
VCCR_15VCCT_16
VEET_17
TD+TD-
VEET_20
CGND_20
CGND_18CGND_19
CGND_17CGND_16CGND_15
CGND_13CGND_14
CGND_12CGND_11
CGND_9CGND_10
CGND_8
CGND_6CGND_7
CGND_5CGND_4CGND_3
CGND_1CGND_2
i350
SET3_PSET3_N
SET2_PSET2_N
SET1_PSET1_N
SET0_PSET0_N
SER3_PSER3_N
SER2_PSER2_N
SER1_PSER1_N
SER0_PSER0_N
SDP3_3SDP3_2SDP3_1SDP3_0
SDP2_3SDP2_2SDP2_1SDP2_0
SDP1_3SDP1_2SDP1_1SDP1_0
SDP0_3SDP0_2SDP0_1SDP0_0
SRDS_3_SIG_DETSRDS_2_SIG_DETSRDS_1_SIG_DETSRDS_0_SIG_DET
SFP1_I2C_DATA
SFP0_I2C_DATA
SFP2_I2C_CLK
SFP1_I2C_CLK
SFP0_I2C_CLK
SFP3_I2C_DATA
SFP2_12C_DATA
SFP3_12C_CLK
SUPPORT CIRCUITS
THIS IMPLEMENTATION ISREQUIRED FOR PROPER CRYSTAL
MAIN_PWR_OK IS HIGH WHEN FULL DEVICE POWER IS AVAILABLE
* WHEN MAIN_PWR_OK TRANSITIONS FROM HIGH TO LOW THE KEEP_PHY_LINK_UP BIT IS CLEARED.THIS PREVENTS THE DEVICE FROM USING TOO MUCH POWER EVEN IN THE CASE THAT THE BMC WAS TRYING TO BLOCK PHY STATUS CHANGES.
IF THE POWER SUPPLIES CAN PROVIDE ENOUGH POWER TO POWERVILLE TO MAINTAIN A 1000BASE-T LINK AT ALL TIMES AND IF THE BMC WANTS LINK TO SURVIVE WHEN THE KEEP_PHY_LINK_UP IS SET EVEN IF MAIN POWER IS NOT AVAILABLE
A FLASH DEVICE IS NOT REQUIRED
INTEGRATED INTO THE BIOSIF PXE AND/OR ISCSI BOOT CODE IS
LOADING
TSENSE
THE MAIN_PWR_OK SHOULD BE PULLED UP TO 3.3V AT ALL TIMES.
AND LOW WHEN ONLY AUX POWER IS AVAILABLE *
THE EXACT 3.3K OHM VALUE OF THE PULL-UP RESISTER IS NOT CRITICAL. 0 OHM TO 10K OHM IS OK.
IN THIS CASE, ENSURE PULL-UPS ARE CONNECTED TO POWER SUPPLIES DERVIVED FROM AUX POWER.
2
1 C191
2
1 C190
2
1R160
325
67
1
U12
R231 C109
C108C11021
Y1
21
R234
2
1R237
21R238
2
1R247
21R264
R258 R235
2
1
R2682
1
R266
2
1
R2692
1
R267
21R239
21R265
21R25321R25221R25721R254
21
J27
21
J25
3
8
1 2
7
4
56
U13
P2P1
T1R2
K13
R1G15C12
A1A2
B2D4
C14D14E14F14
T2
C15B15B16C16
E16F15E15F16
C4
D15
U7
XTAL_OUT FLASH_SCK
EEPROM_SI
XTAL_CLK_IN
AUX_PWR
LAN0_DIS_NLAN1_DIS_N
LAN3_DIS_N
DEVICE_OFF_N
PE_TRIM1
PE_TRIM2
V3P3_LAN
V3P3_PE_MAIN
323852-002
EEPROM_SO
EEPROM_WP_N
FLASH_HOLD_N
EEPROM_CS_N
REXT3K
27.0PF
EEPROM_HOLD_N
FLASH_WP_N
1%
0
XTAL_IN
V3P3_LAN_SUPPORT
COG
V3P3_PE_AUX
3.01K 1%
25.000MHZ
V3P3_LAN_SUPPORT
EEPROM_SCK
TSENS_PTSENS_Z
TX_TCLOCK
I350 REFERENCE DESIGN 2.0 2011-06-22
3.3K
3.3K
3.3K3.3K
1%
3.3K
3.3K
3.3K
3.3K3.3K
3.3K
COG
3.3K
EMPTY
EMPTY
V3P3_LAN_SUPPORT
9
MAIN_PWR_OKLAN_PWR_GOOD
2.37K
XTAL_CLK_OUT
10.0PF
27.0PF
1.50K
3.3K3.3K
LAN2_DIS_N
COG
FLASH_SO
FLASH_CS_N
FLASH_SI
V3P3_LAN_SUPPORT
0.1UF
V3P3_LAN_SUPPORT
V3P3_LAN_SUPPORT
SE_RSET
3.3K
3.3K
0.1UF
DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
AT25256CS_NWP_NSISCKHOLD_N
SO
M25P40
GND
VCC
Q
HOLD_N
W_N
S_N
C
D
2
1
2
1
i350
XTAL_CLK_OXTAL_CLK_I
SE_RSET
RSVD_TP_8RSVD_TE_VSSMAIN_PWR_OK
LAN_PWR_GOOD
LAN3_DIS_NLAN2_DIS_NLAN1_DIS_NLAN0_DIS_N
AUX_PWR
PE_TRIM2
PE_TRIM1
RSVD_TX_TCLK
GE_REXT3K
TSENSZTSENSP
FLSH_SOFLSH_SI
FLSH_SCKFLSH_CE_N
EE_SKEE_DOEE_DI
EE_CS_N
DEVICE_OFF_N
POWER SUPPLIES
2
1 C105
2
1 C22
2
1 C159
2
1 C55
2
1 C60
2
1 C33
2
1 C163
2
1 C164
2
1 C146
2
1 C145
2
1 C150
2
1 C126
2
1 C115
2
1 C148
2
1 C153
2
1 C122
2
1 C141
2
1 C116
2
1 C144
2
1 C152
2
1 C130
2
1 C123
2
1 C156
2
1 C134
2
1 C129
2
1 C128
2
1 C132
2
1 C125
2
1 C143
2
1 C151
2
1 C155
2
1 C181
2
1 C138
2
1 C137
2
1 C139
2
1 C182
2
1 C131
2
1 C127
2
1 C165
2
1 C183
2
1 C142
2
1 C154
L12
K5K12
H5H12
F5F12
L5
P8P11
M9M8M7M6
M10
C7C10
N12
M11
K6
K11
J6
J11
H6
H11
G6
G11
E6
E11
L14
L13K14
D9D8D6
D11
L9L8L7
L10
C11C9C6
U7
P3
N9N8N7N6
N5
N11N10
M5 M12
L6L11
K9K8K7
K10
J9J8J7J5
J12J10
H9H8H7
H10
G9G8
G12
G10
F9F8F7
F11F10
E9E8E7
E10
D7D10
B7B4
B13B10
A7A4
A13A10
U7
1000PF1000PF
1000PF
47UF
1000PF
10UF
10
1000PF
2011-06-22
1000PF 1000PF
1000PF
1000PF
1000PF
I350 REFERENCE DESIGN
0.01UF
1000PF
2.0323852-002
1000PF
V3P3_LAN
V1P0_LAN
V1P8_LAN
0.01UF 1.0UF
1000PF
1000PF
47UF
1206LF
10UF 1.0UF 0.01UF
1.0UF 0.01UF 1000PF
1.0UF 0.01UF 1000PF
47UF 10UF
0.01UF
1000PF
1.0UF
1000PF
0.01UF
1.0UF
1.0UF
1.0UF
0.01UF
0.01UF1.0UF
DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
i350
VCC1P0_N12
VCC1P0_ASE_L14VCC1P0_ASE_K14
VCC1P0_K11
VCC1P0_K6
VCC1P0_J11
VCC1P0_J6
VCC1P0_H11
VCC1P0_H6
VCC1P0_G11
VCC1P0_G6
VCC1P0_E11
VCC1P0_E6
VCC3P3_L12VCC3P3_K12VCC3P3_K5VCC3P3_H12VCC3P3_H5VCC3P3_F12VCC3P3_F5
VCC1P0_M11
VCC1P0_ASE_L13
VCC1P8_APE_C10VCC1P8_APE_C7
VCC3P3_AGE_L5
VCC1P0_APE_D11VCC1P0_APE_D9VCC1P0_APE_D8VCC1P0_APE_D6VCC3P3_A_P11
VCC3P3_A_P8VCC3P3_A_M10VCC3P3_A_M9VCC3P3_A_M8VCC3P3_A_M7VCC3P3_A_M6
VCC1P0_AGE_L10VCC1P0_AGE_L9VCC1P0_AGE_L8VCC1P0_AGE_L7
PE_TXVTERM4PE_TXVTERM3PE_TXVTERM1
i350
VSS_N5VSS_M12VSS_M5
VSS_A4VSS_A7VSS_A10VSS_A13VSS_B4VSS_B7VSS_B10VSS_B13VSS_D7VSS_D10VSS_E7VSS_E8VSS_E9VSS_E10
VSS_F7VSS_F8VSS_F9VSS_F10VSS_F11
VSS_G8VSS_G9VSS_G10
VSS_G12VSS_H7VSS_H8VSS_H9
VSS_H10VSS_J5VSS_J7VSS_J8VSS_J9
VSS_J10VSS_J12
VSS_K7VSS_K8VSS_K9
VSS_K10VSS_L6
VSS_L11VSS_N6VSS_N7VSS_N8VSS_N9
VSS_N10VSS_N11
VSS_P3
THEY SHOULD BE OPTIMIZED FOR EACH DESIGNBY POWER INTEGRITY ENGINEER.
POWER SUPPLIES SHOWN ARE SUGGESTED EXAMPLES.
12-TO-4.4 V BUCK
VIN = 8 TO 40 V
SVR FOR V3P3
SHEET 14P ~ 8.74 W
POWER SUPPLY TREE
VIN = 1.8 TO 5.5 VLTC3533
I_MAX = 1.46 AV = 3.3 V ± 9%PMAX = 5.23 W
IOUT_MAX = 2 A (BUCK)1.5 A (BOOST)
EFFICIENCY ~ 90%P_IN ~ 5.8 WV = 3.7-4.0 V
IOUT_MAX = 2.5 AVIN = 0 TO VCC VLTC4352
I_MAX ~ 1 AV ~ 12 V ± 8%PMAX ~ 11 WEFFICIENCY ~ 80%
IOUT_MAX = 5 A
IDEAL DIODE
V5P0_SATAEXTERNALAUX PWR
TPS40055
TPS40055 SVR12P0-3P3V
I350-SVR
SHEET 16
SHEET 15
DIODE_ORV3P3
SHEET 13 I350-LVR
SHEET 16
BUCK/BOOSTENABLEV3P3
SHEET 14
21R154
21R140
21R130
21R137
43
21
J49
43
21
J23
43
21
J45
21
J48
21
J33
21
J44
43
21
J46
21
J47
21J39
21 J41
21 J40
CONN
V1P8_LAN
323852-002
V3P3_LAN_SUPPORT
11
CONN
CONNTHLF
V3P3_OR
V12P0_PE_MAIN
V1P0_POWER
I350 REFERENCE DESIGN
CONNTHLF
2011-06-222.0
1/2W1%
THLF
V3P3_LAN
1206LF
CONN
CONN
CHIP
1206LF
THLF
CHIP
1206LF
1206LF
V1P8_POWER
V3P3_POWER
1%1/2W
V1P0_LAN
1/2W0
V3P3_PE_AUX
THLFCONN 1%
THLF
THLF CONN
1/2W0 1%
CHIP0
0
CHIP
THLF
DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
CONN
4CO
NN4
CONN
4
2121
21
CONN
4
21
2
1
2
1
2
1
POWER MUX (AUX / MAIN SWITCH)
IDEAL DIODE USED FOR AUX
43
21
J2
21F4 12
CR4
987
321
654
121110
151413
J1
2
1 C13612
CR1
2
1 C34
2
1 C62
2
1 C36
2
1 C185
2
1 R127
2
1 R126
2
1 R132
2
1 R129
2
1C8
21
C352
1R1384
3
6521
U4
123
5
127
89
11
613
104
U2
CR2
12
CR3
12
MBRS540LT3
MBRS540LT3
NTGS4141N
V3P3_PE_AUX
MBRS540LT3
8.2K0.1UF
EMPTY
100K
100K
EMPTY
MBRS130LT3GEMPTY
V3P3_CONN
10UF
100K
10UF
100K
2011-06-222.0323852-002I350 REFERENCE DESIGN
V3P3_PE_AUX
V12P0_PE_CONN
V5P0_CONN_UNFUSED
V3P3_PE_AUX
0.1UF
10UF 100UF
TPS40055_OUTPUT
10UF
V3P3_PE_MAIN
20%
V3P3_OR
1812LF
DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
CONN
4
CONN15_E33878_001
12V_1512V_1412V_13
GND_12GND_11GND_10
VCC_9VCC_8VCC_7
GND_6GND_5GND_4
VCC3_3VCC3_2VCC3_1
G
S1
D2 D3 D4D1
G
LTC4352
FAULT
STATUS
OUTGATE
SOURCE
CPO
VIN
EPADGND
REV
0V
UV
VCC
TPS40055 SWITCHING REGULATORPOWER SUPPLY (12P0-3P3)
DNS
VOUT_MAX = ???
IOUT_MAX = 5A
VOUT_MIN = ???DNS
2
1 C38
2
1 C39 C42
R141 C43
2
1C186 R147
R142 R148
R150 C48
C46 2
1C187
2
1C49
2
1R151
3
4
56
Q5
C9
21
R157
1
2
78
Q5
L1
R170
2
1
R162
C188
C59
21
R163
C65 C189 C133
2
1 C41
15
7
412
65
2
17
910
1 16
13
8
3
11
14
EU1
13
12.1K
2011-06-22
V12P0_PE_MAIN
0.1UF
3300PF 1%374
1%
49.90K1%
49.90K
KFF_5VRT_5VBP5_5V
0.1UF
169.00K
10UF
2.67K
16V0.1UF
49.90K
4700PF
VFB_5V
TPS40055_OUTPUT
2.1UH
100.0PF
1.0UF16V
X5R
1210LF
X5R
16V22UF22UF22UF
2200PF
10.0K
0
16V1.0UF
LDRV_5V
1%
6.34K
ILIM_5V
BOOST_5VHDRV_5V
BP10_5V
I350 REFERENCE DESIGN 2.0323852-002
10UF
1%
25V
1%
120PF
SW_5V
1210LF
1%
25V10UF
1%
16V25V
X5R
1210LF
16V
1%
SS_5V
COMP_5V
DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
S
D
D
G
S
D
D
GTPS40055PWP
POW
ERPA
D
ILIMVIN
BOOST
HDRV
SW
BP10
LDRV
PGNDCOMP
VFB
SS
SGNDSYNC
BP5
RTKFF
VOUT_MAX = 3.41VVOUT_MIN = 3.18V
I3533-MAX
3.3V ENABLE
MANY DESIGNS MAY NOT REQUIRE A BOOST CIRCUIT.VOLTAGE DROP FROM DIODE OR CIRCUIT.VOLTAGE BOOST REQUIRED TO COMPENSATE FOR
= 1.5A
(REQUIRED FOR 4-PORT SFP OPERATION)
LTC3533 BUCK/BOOST REGULATOR FOR 3.3V
2
1 C66
2
1
C69
2
1R175
2
1R178
2
1R177
45 31
2
U15
21C160
21R261
2
1 C562
1 C170
2
1R153
2
1R156
2
1R146
21C169
21C184
21R271
2
1 C161
2
1R2562
1 C63
21
R145
L2
810
14
743
12
1
911
65
15
13
2
U6
6.8UH
1000PF
340K
142011-06-22323852-002
2.20
10UF
2.0I350 REFERENCE DESIGN
V3P3_POWER
10UF
0
47.0PF
1%
1%200K
6.800PF
8.2K
390K
1%33.2K
V3P3_OR
1000PF
1% 1%1.00M
0.1UF1%12.1K
0.1UF
EN_3.3V
0.1UF
V3P3_OR
7.68K
NC_76
DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
TPS3803-01D
RESET_NGND
VDDSENSENC
LTC3533
PAD
PGND
_6
PVOUT
VOUT
FB
VC
BURST
PGND
_5
SGND
RT
RUN/SS
VIN
PVIN SW2
SW1
INTEGRATED 1.0V SVR & 1.8V LVR
SVR REF-DES RLC100X RELATES TO DATA SHEET REFERENCES
1. 1 X 47 µF ±10%2. 3 X 22 µF ±10%3. 3 X 100 NF ±10%4. 3 X 10 NF ±10%5. 3 X 1 NF ±10%
TOTAL BULK CAPACITANCE OF INPUT (V3.3_LAN).SHOULD BE GREATER THAN LOAD (V1P8 & V1P0).
C209-211 LARGE BULK CAPS NOT REQUIRED.CAN BE USED AS NEEDED IF EXCESS RIPPLEIS OBSERVED AND IS PLATFORM DEPENDANT.
P-FET
CAD NOTE:
CAD NOTE:
USE PLANE SHAPE CONNECTIONSKEEP VR PARTS CLOSE TO BGA
N-FET
OR SHORT THICK TRACES
PLACE C1002 AT BGA PADS C-OUT RECOMENDATION
2
1 C194
2
1 C192
2
1 C211
2
1 C210
2
1 C209
G14
G7
D5
C5
G5
F6
C8
U7 321
4
8765
Q6
C172C166 C147
2
1 C162
2
1 C157
2
1 C52
2
1 C44
2
1 C140
2
1 C51321
4
8765
U921
R164
21R149
2
1R166
2
1 C45C135
2
1 C58
R1003 C1003
C100
2
C1001R1002
R1001
2
1 C61
2
1 C193
2
1 C68
2
1 C57
3
421
U11
C54
L1001
6.3VEMPTY
1.0UH
2200PF
0.1UF0.1UF
0.01UF 0.01UF
0.1UF
V3P3_LAN
22UF6.3VEMPTY
6.3V
0.1UF
0
10.0
PF
180UF
VR_EN
680PF39K
SVR_FB
680
1000PF
10V
0.1UF47UF6.3V
V1P0_POWER
0.01UF
1K
V3P3_LAN
0
22UF
1P8_CTRL
22UF
10UF
I350 REFERENCE DESIGN 323852-002 2.0
BCP69T1
SVR-COMP
10UF
V1P8_POWER
4.7K
DMN2009LSS
180UF
V1P0_POWER
V1P0_POWER
180UF
EMPTY
COG
2011-06-22
1000PF
0.1UF
15
SVR_LDRV
DMP2022LSS
1000PF
1.0UF
SVR_SW
SVR_HDRV
DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
i350
VR_EN
SVR_SW
SVR_LDRV
SVR_HDRV
SVR_FB
SVR_COMP
LVR_1P8_CTRL
S1 S2
D3 D4
S3
D2D1
G
S1 S2
D2 D3 D4
S3
D1
G
IF NCSI INTERFACE IS CLOCKED
SHOULD BE CONNECTED TO NCSI_CLK_OUTFROM INSIDE THE I350 THE NCSI_CLK_IN
I350-NCSI
R121R7010.0K
NCSI_ARB_OUT
NCSI_CLK_OUT
NCSI_CRS_DVNCSI_RXD_0NCSI_RXD_1NCSI_TXD_0NCSI_TXD_1NCSI_TX_EN
2
1
2
1R100
J4J3
J2
J1H4H3
H2H1
D12C13
U721
R230
2
1R228
21R229
2
1R49
2
1R190
2
1
2
1R73
2
1R37
2
1R71
10.0K 10.0K 10.0K
NCSI_CLK_IN
NCSI_ARB_IN
10.0K 10.0K
V3P3_LAN_SUPPORT
16
33
10.0KEMPTY
0
10.0K
2011-06-222.0323852-002I350 REFERENCE DESIGN
10.0K
DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
i350
NCSI_TX_EN
NCSI_TXD_1NCSI_TXD_0
NCSI_RXD_1NCSI_RXD_0
NCSI_CRS_DV
NCSI_CLK_OUTNCSI_CLK_IN
NCSI_ARB_OUTNCSI_ARB_IN
IN
INOUT
OUT
OUTOUT
ININ
NC-SI TEST INTERFACETEST INTERFACE IS NOT REQUIRED IN A NORMAL DESIGNCONNECT NS-SI INTERFACE TO A MANAGEMENT CONTROLLER
NCSI MODE DIS BTB DIS
10MBPS
ISO_EN
BTB
NCSI MODE EN
ENABLE FX
BTB EN
FULL DUPLEX
NC-SI PHY SUPPLIES
ISO_DIS
TSR > 50 US
ENABLE AUTONEG
DISABLE FX MODE
100MBPS
21
R3
21
R74
12
DS1
21
R77
321
J22
21
R75
21
R50
21
R63
21
R35
321
J21
21
R12
21
R10
21
R72
21
R6
21
R7
2
1
C4
21
R64
21
R1892
1R2
1
21
R5
21
R188
21
R23
21
R22
21
R11
21
R20
21
R4
21
R61
2
1 C73
2
1 C71
2
1 C87
2
1 C9221
FB921
FB2
2
1 C5
2
1 C6
2
1 C70
2
1C74
4546
42313847
247
13
4140
14
16
20191817
15
3332
119
3456
10
48
37
30
12
29282726
25
34
2221
U1
17
EMPTY
10.0K
10.0K V3P3_NCSI_PLL
MDC
10.0K
0.1UF0.1UF10UF10UF
10UF10UF10UF10UF
10.0K
EMPTY
V2P5_NCSI
V3P3_LAN_SUPPORT
2011-06-222.0323852-002I350 REFERENCE DESIGN
V3P3_LAN_SUPPORT
V2P5_NCSI
V3P3_LAN_SUPPORT
V2P5_NCSI_PLL V2P5_NCSI_C
NCSI_TX_NNCSI_TX_P
FIBER_EN
NCSI_TX_EN
10.0K
NCSI_SPD100
ISOLATE
10.0K
EMPTY
NCSI_LINK_ACT
DUPLEXAUTONEG_EN
NCSI_ENNCSI_BTB
V3P3_LAN_SUPPORT
XI
NCSI_RXD_1NCSI_RXD_0NCSI_CRS_DVNCSI_PHY_CLK
TXER
NCSI_RX_PNCSI_RX_N
NCSI_TXD_1NCSI_TXD_0
6.49K1%
10.0K
10.0K
10.0K
V3P3_LAN_SUPPORT
22.60K
V3P3_LAN_SUPPORT
GREE
N
330
MDIO
10.0K
V3P3_LAN_SUPPORT
V3P3_LAN_SUPPORT
10.0K
10.0K
10.0K
10.0K
10.0K
EMPTY
EMPTY
600600
10.0K
0
1%
0.1UF
10.0K
EMPTY
10.0K
10.0K
DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
CONN3
CONN3
ININ
OUTOUT
IN
ININ
TXD1TXD2
PD_N
CRS_RMII_BTBCOL_RMII
TXP
LED3_NWAYEN
LED1_SPD100_NFEFLED0_TEST
RXER_ISORXDV_CRSDV_PCS_LPBK
RXC
FXSD_FXEN
XO
TXD0TXEN
KS8721
LED2
RST_N
TXD3
MDCMDIO
XI
TXN
INT_N_PHYAD0RXD3_PHYADRXD2_PHYAD2RXD1_PHYAD3RXD0_PHYAD4RXN
VDDIO_0VDDIO_1
VDDC
VDDPLLVDDRCVVDDRXVDDTX
TXC_REFCLKTXER
REXTRXP
RJ45 MAGJACK
CLOSE TO PHY
CLOSE TO PHY
AS POSIBLE
+-50 PPM
AS CLOSE TO THE DEVICE
50MHZ NC-SI CLOCK
CONNECT NS-SI INTERFACE TO A MANAGEMENT CONTROLLER
CLOSE TO SOURCE
TEST INTERFACE IS NOT REQUIRED IN A NORMAL DESIGN
NC-SI TEST INTERFACE
21 J28
21R78
2
1C72
2
1C10421
R223
21
R220
2
1C11
2
1C103 21R227
21R221
4312
Y2
7632
8
5
U3
21
FB1
2
1
C1
21R1
21R2
21
R8
21
R9
2
1
C2
2
1C3
21
R31
21
R36
C2
C1
A2
A1
87654321
JA1
18
V2P5_NCSI
NCSI_LINK_ACT
NCSI_SPD100
0.01UF
V3P3_LAN_SUPPORT
2011-06-222.0323852-002I350 REFERENCE DESIGN
0.1UF
V2P5_NCSI
50MHZ
0.1UF
GND_SFP_CAGE
49.9
49.9
49.9
0.1UF
49.9
130
130
33
33
33
0
OSC
10.0K
600
V3P3_LAN_SUPPORT
V3P3_LAN_SUPPORT
0.01UF
NCSI_CLK_IN
NCSI_CLK_OUT
V3P3_LAN_SUPPORT
1%
NCSI_PHY_CLK
EMPTY
CT
0.01UF
1%
NCSI_TX_N
NCSI_TX_P
NCSI_RX_N
NCSI_RX_P
0.1UF1% 1%
DOCUMENT NUMBER REV DATECODE
B
SIZETITLE SHEET
5 4
A
12
A
B
C
78
B
C
DD
1345678 2
6 3
LAN ACCESS DIVISION2111 N.E. 25th AVENUEHILLSBORO, OR 97124
2
1
VDD GNDOE OUT
OE
Q0
Q3Q2Q1ICLK
ICS553
31
57
42
68
C2A2
C1A1
