Hybrid Solid- and Liquid-Cooling Solution for Isothermalization of Insulated Gate Bipolar Transistor Power Electronic Devices

IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 3, NO. 4, APRIL 2013 601

Hybrid Solid- and Liquid-Cooling Solution forIsothermalization of Insulated Gate Bipolar

Transistor Power Electronic DevicesPeng Wang, Senior Member, IEEE, Patrick McCluskey, and Avram Bar-Cohen

Abstract— Rapid increases in the power ratings and continuingminiaturization of power electronic devices have pushed chipheat fluxes well beyond the range of conventional thermalmanagement techniques. The heat flux of power electronicdevices for hybrid electric vehicles is currently at the level of100–200 W/cm2 and is projected to increase to 500 W/cm2 innext generation vehicles. Such high heat fluxes lead to higher andless uniform insulated gate bipolar transistor (IGBT) chip tem-perature and significantly degrade the device performance andsystem reliability. Maintaining the maximum temperature belowa specified limit, while isothermalizing the surface temperatureof the chip, has become a critical issue for thermal managementof power electronics. In this paper, a hybrid solid- and liquid-cooling system design, which combines cold plate liquid coolingand TE solid-state cooling, is proposed for thermal managementof a 10×10 mm IGBT chip. The liquid-cooling cold plate isused for global cooling of the entire IGBT module while theembedded thin-film TE cooler (TEC) is employed for isother-malization of the individual IGBT chip. A detailed package-level 3-D thermal model is developed to explore the potentialapplication of this cooling concept, with the primary attentionfocused on isothermalization and temperature reduction of IGBTchip associated with variations in TEC sizes, TE materials,applied current on TEC, cooling system designs, working fluidtemperature, cold plate cooling capacity, and IGBT chip heat flux.The results demonstrate that the hybrid solid and liquid coolingis a very promising thermal management solution that can elim-inate more than 90% of the temperature nonuniformity on theIGBT chip.

Index Terms— Insulated gate bipolar transistor (IGBT), powerelectronics, thermoelectric cooling, two-phase cooling.

I. INTRODUCTION

THE CONTINUING trends toward device miniaturizationand high performance have placed increasing demands

on the thermal management systems used for power elec-tronic devices, especially for insulated gate bipolar transistors(IGBTs). The heat flux of power electronic devices for hybridelectric vehicles is now at the level of 100–200 W/cm2

and is projected to increase to 500 W/cm2 in the nextgeneration [1]–[3]. Such high heat fluxes lead to higher and

Manuscript received March 17, 2012; revised September 3, 2012; acceptedSeptember 23, 2012. Date of publication December 28, 2012; date of currentversion March 28, 2013. Recommended for publication by Associate EditorV. Calmidi upon evaluation of reviewers’ comments.

The authors are with the Department of Mechanical Engineering, Universityof Maryland, College Park, MD 20742 USA (e-mail: [email protected];[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2012.2227056

less uniform IGBT chip temperature and degrade the deviceperformance and system reliability significantly. Therefore,exploring and applying advanced cooling technologies tomaintain the maximum IGBT junction temperature below aspecified limit, 125 °C for silicon-based IGBT, 175 °C fortrench IGBT, and 200 °C for silicon carbide-based IGBT,have become essential for thermal management of powerelectronics.

Effective cooling of IGBT chip is able to improve not onlythe reliability, through eliminating overstress failures, andreducing the severity of fatigue mechanisms at higher tem-peratures and higher frequencies of thermal cycling, but alsothe performance of power electronics systems. For example,it has been demonstrated that for three-phase inverters with1.7-kV IGBT technology, increasing the cooling capacity from50 W/cm2 (typical for an air-cooled heat sink) to 120 W/cm2

(typical for liquid-cooled cold plate) makes it possible todouble the output current of the inverter, from 40 to 80 A/cm2

[4]. In a 1200 V/150 A IGBT inverter module driving a50-HP three-phase ac motor, the use of liquid-cooled coldplate and jet impingement have been shown to enhance themodule output power rating by 30% and 80%, respectively,in comparison with conventional air-cooling technology [5],[6]. These results suggest that a significant energy saving canresult from the use of an effective cooling strategy, which thencompensates for the energy investment and cost associatedwith integrating the cooling device into the power electronicssystem.

Single-phase or two-phase liquid-cooling solutions, suchas microchannel heat sink cooling, spray cooling, and jetimpingement cooling, can provide very high heat transfercoefficients and low thermal resistance. Lee and Mudawar[7]–[9] designed an R134a-cooled two-phase microchannelheat sink capable of providing a heat transfer coefficient up to50 000 W/m2-K. Fabbri et al. [10] developed a single-phasespray-cooling system showing that a heat transfer coefficientof 15 000 W/m2-K can be obtained with the water as theworking fluid. Silk et al. [11] demonstrated that a two-phasespray cooling with PF-5060 as the working fluid can achievea heat transfer coefficient of 24 000 W/m2-K. Compared tomicrochannel cooling and spray cooling, jet impingementcooling can offer much higher heat transfer capability. Forexample, Natarajan and Bezama [12] demonstrated that asingle-phase water submerged jet can reach a heat transfercoefficient as high as 52 000 W/m2-K. These state-of-the-art cooling technologies can meet high heat flux cooling

2156-3950/$31.00 © 2012 IEEE

602 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 3, NO. 4, APRIL 2013

IGBT Chip

AlN

Cu

Cu

Uniform Heat Flux100 ~ 200W/cm2

DB

C

Solder

Liquid Cooling Cold Plate

Solder

Fig. 1. Schematic for IGBT package integrated with liquid-cooling coldplate.

TABLE I

DIMENSIONS AND MATERIALS PROPERTIES OF A

TYPICAL IGBT PACKAGE

Material Dimensions (mm)Thermal

Conductivity(W/m-K)

Heat Flux(W/cm2)

Si IGBT chip 10 × 10 × 0.50 120 100–200

DBC copper 30 × 30 × 0.32 398

AlN substrate 30 × 30 × 0.64 170

Cold platebase

50 × 50 × 6.00 170

95Pb5Sn or96Sn4Ag

solder0.10 50

requirements for IGBT chip, if they can be interfaced properlywith the IGBT electronic packaging technology.

However, these high heat flux cooling solutions, whenapplied on the back side of the direct-bonded copper (DBC)substrate and designed for thermal management of the entireIGBT module, cannot remove the nonuniform temperaturedistribution on the individual IGBT chips. Fig. 1 illustratesa typical IGBT package with a copper cold plate solderedonto the DBC substrate and Table I gives the materials anddimensions of the components of the IGBT package. In thistypical configuration, the IGBT chip is solder bonded tothe DBC substrate that provides electrical isolation and heatspreading with the help of an aluminum nitride (AlN) layersandwiched between thin copper layers. The DBC substrateis then assembled onto the cold plate with another layer ofsolder. A 3-D package-level thermal model is developed andperformed for various IGBT heat fluxes and effective heattransfer coefficients achievable by liquid-cooling cold plateto examine the impact of IGBT heat flux and liquid-coolingcapacity on the temperature nonuniformity of IGBT chip sur-face. Fig. 2 shows the temperature profile along the diagonalposition of IGBT chip with a heat flux ranging from 100 to200 W/cm2 and an effective heat transfer coefficient varyingfrom 10 000–30 000 W/m2-K, which is applied on the coldplate at the working fluid temperature of 30 °C. It is interestingto find that an increase in effective heat transfer coefficientwill reduce the IGBT temperature but has no effect on the

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Fig. 2. Temperature profile along the diagonal position of IGBT chip with aheat flux of (a) 100 W/cm2 and (b) 200 W/cm2. The working fluid temperatureis fixed at 30 °C.

temperature distribution on the IGBT surface. Furthermore,it can be seen that the maximum temperature variation—thedifference between the maximum and minimum temperatureson the IGBT surface—increases with the IGBT heat flux, from7 °C at 100 W/cm2 to 14 °C at 200 W/cm2. This thermalcharacteristic implies that improving cooling capacity of coldplate cannot suppress the parabolic-like temperature profile onthe IGBT surface and remove the temperature nonuniformity.From the viewpoints of electrical design, failure predication,thermal-stress development, and system reliability, maintain-ing the IGBT surface temperature as uniform as possible andkeeping all the components of IGBT chip operated at the sametemperature is highly desirable [13]. Therefore, a new andnovel cooling solution has to be found and integrated intothe existing cooling scenario of power electronics system forisothermalization of IGBT chip.

In recent years, advanced thermoelectric (TE) solid-statecooling technology, based on polycrystalline miniaturized

WANG et al.: HYBRID SOLID- AND LIQUID-COOLING SOLUTION FOR ISOTHERMALIZATION 603

TE cooler (TEC) [14], [15], nanostructured superlattice TEC[16], [17], minicontact enhancement technology [18], [19],and silicon and germanium substrate self-cooling [20]–[22]have received great attention and considerable progress hasbeen made at the research level for high-flux thermal manage-ment for microprocessors and electro-optic components. Thesesolid-state cooling devices have compact structure, offer highreliability, can be locally applied, provide high cooling flux,and can be integrated with IC processing. Although thin-filmTE cooling technology has been successfully demonstratedfor thermal management of 1250 W/cm2 400 × 400 μmhot spot for silicon microprocessor [23], [24], there is noattempt on application of thin-film TEC for cooling high-fluxIGBT chip. In this paper, we propose a hybrid solid-/liquid-cooling solution, which combines cold plate liquid coolingand TE solid-state cooling, for thermal management of a10 × 10 mm IGBT chip at a heat flux of 100–200 W/cm2.The innovation of this cooling concept is that the cold plate isused for global cooling of the entire IGBT module [25], andthe embedded thin-film TEC is employed for isothermalizationof the individual chips. The objective of this paper is toevaluate the potential application of this hybrid cooling systemfor IGBT power electronics, with a primary focus on therole of TE cooling for isothermalization of the IGBT chip.The influence of applied current, TEC sizes, TE materials,cooling system designs, working fluid temperature, cold platecooling capacity, and heat flux on IGBT chip are addressedand discussed in details.

II. STRUCTURE OF HYBRID COOLING SOLUTION

The schematic of the proposed thermal packaging for IGBTchip is shown in Fig. 3 and three cooling configurationsare presented: 1) the thin-film TEC is embedded into thecopper layer of the DBC substrate; 2) the thin-film TECis embedded into the cold plate base; and 3) the thin-filmTEC is embedded into the cold plate base and enhancedwith a trench in the DBC substrate, where the trench is usedto partially eliminate the heat-spreading effect of the DBCsubstrate, thereby concentrating the TE cooling power mostlyonto the IGBT chip. Copper is used for cold plate to facilitategood heat dissipation because of high thermal conductivity.A 95Pb5Sn or 96Sn4Ag solder, instead of thermal grease, isapplied at the DBC substrate/cold plate interface to ensuregood thermal contact.

Two different types of TECs are proposed and integratedinto the IGBT package for evaluation of isothermalizationfeasibility and effectiveness. One is the polycrystalline Bi2Te3-based bulk TEC fabricated by bulk miniaturization technology[18], [19]. The Seebeck coefficient is 200 μV/K, the electricalresistivity is 10 μ�-m, and the thermal conductivity is1.5 W/m-K, which contributes to the TE figure-of-merit value(ZT ) of 0.9 at 300 K as reported by Semenyuk [19]. The otheris the Bi2Te3-based superlattice TEC fabricated by metal-organic chemical-vapor deposition process [20]. The averagedSeebeck coefficient is measured to be 301 μV/K while theaverage electrical resistivity is 10.8 μ�-m and the measuredthermal conductivity is 1.2 W/m-K, which leads to a ZT of

IGBT Chip

AlNCu

Cu


DB

C

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Liquid Cooling Cold Plate

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Uniform Heat Flux

DB

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Solder

Liquid Cooling Cold PlateTEC

(b)

IGBT Chip

AlNCu

Cu


DB

C

Solder

Solder

Liquid Cooling Cold PlateTEC

(c)

Fig. 3. Hybrid solid- and liquid-cooling designs for IGBT isothermalization.(a) Thin-film TEC embedded in the copper layer of the DBC substrate.(b) Thin-film TEC embedded in the cold plate base. (c) Thin-film TECembedded in the cold plate base and enhanced with trench structure in theDBC substrate.

2.1 at 300 K [19], [20]. The electrical contact resistance at thesuperlattice/metal interface was measured to be 10−11 �-m2

based on transmission-line modeling measurements [19].Four different TEC structures are investigated with

the TE element array of 6 × 6, 10 × 10, 13 × 13,and 16 × 16, respectively. The detailed structure of TEelements for each configuration is shown in Fig. 4. TheTE element has a dimension of 400 × 400 × 20 μm withan element-to-element gap of 200 μm, which translatesthe TE element packing density of 40% on the TEC. Thefootprint area of the TEC is 3.8 × 3.8 mm2, 6.2 × 6.2 mm2,8.0 × 8.0 mm2, 9.8 × 9.8 mm2 for 10 × 10, 13 × 13,and 16 × 16 array TEC, respectively, corresponding to thefootprint coverage of 14.4%, 38.4%, 64.0%, and 96.0% onthe IGBT chip. A 100-μm-thick AlN is used as the substratein the TEC to support TE elements and provide good heatconduction. The total TEC thickness, including TE elements,AlN substrates, and metallization layers, is 220 μm so thatit can be embedded into the 320-μm-thick copper layer inthe DBC substrate. It should be noted that the Bi2Te3-basedsuperlattice TEC developed for on-chip hot spot cooling hasthe TE element thickness only around 5 μm and the total


(a) (b)

(c) (d)

Fig. 4. Layout of the TE elements inside the thin-film TEC.(a) 6 × 6 TE array. (b) 10 × 10 TE array. (c) 13 × 13 TE array. (d) 16 ×16 TE array. The top AlN ceramic substrate is removed to show the internalstructure of the TEC.

Fig. 5. Mesh structure around the TE elements for 6 × 6 array TEC.

TEC thickness is as thin as 100 μm [19], [20]. This typeof ultrathin TEC can obviously provide much more room toaccommodate the TEC into the IGBT package and improvethe flexibility of the cooling design and implementation.

III. FINITE ELEMENT ANALYSIS MODELING

A package-level thermal model with a thin-film TEC inte-grated into the cold plate base or the DBC substrate, includingIGBT chip, thermal interface materials, DBC substrate, coldplate base, and thin-film TEC has been developed. The detailedmeshing structure of TEC and IGBT chip is shown in Fig. 5,and the geometric parameters and material properties for thepackaging materials are listed in Table I. The commercial finiteelement software, ANSYS, is used in this paper and a totalelement number of 200 000–300 000 is created for the entirepackage. The elements are densely located at the TE elementswhere the largest temperature gradient is expected to occur.To accurately measure the average temperatures of the hot andcold junctions of the TEC and the IGBT surface, a uniformmap meshing with a uniform node distribution is applied forthe TE elements and the IGBT chip.

The details of the solid-state circuitry at the active side ofthe IGBT are ignored in this model but the heat generatedfrom these components is modeled as a uniform heat flux of100–200 W/cm2 on the 10×10 mm IGBT surface. The netTE cooling effect, including Peltier cooling and parasitic Jouleheating from the electrical contact at TE element/metallizationlayer interface, can be expressed as an internal surface heatflux boundary condition applied on the cold junction of eachof the TE elements, according to

q ′′cold-junction = −STc I + I 2(ρc/ATE)

ATE(1)

where S is the Seebeck coefficient, Tc is the average absolutetemperature of the cold junction of the TE element, I is theapplied current, ρc is the electrical contact resistance, and ATEis the cross-sectional area of the TE element. Similarly, the netTE heating effect, including Peltier heating and parasitic Jouleheating from electrical contact at the TE element/metallizationlayer interface, can be expressed as an internal surface heatflux boundary condition on the hot junction of the TE elementsas follows:

q ′′hot-junction = ST I + I 2(ρc/ATE)

ATE(2)

where Th is the average absolute temperature of the hotjunction of the TEC. The Joule heat inside the TE elementis given as a volumetric heat generation

q ′′TE = I 2 RTE

VTE(3)

where RTE and VTE is the electrical resistance and volume ofthe TE element.

To simplify the modeling effort, the detailed internal struc-ture of the cold plate is not included in this model and,instead, an effective convective heat transfer coefficient of10 000–30 000 W/m2-K is applied as a boundary condition onthe top surface of the cold plate base to simulate the liquid-cooling capacity. The working fluid temperature of 30 °C isused for most of this paper, but 105 °C is also examined forthe effect of working fluid temperature on isothermalizationeffectiveness. In addition, homogeneous and constant materialproperties and uniform thicknesses are assumed for the IGBTchip, thermal interface materials, DBC substrate, and coldplate base as shown in Table I.

IV. RESULTS AND DISCUSSION

A. Cooling Metrics

To characterize the thermal performance of the TEC and itssuccess in reducing and isothermalizing the IGBT chip tem-perature, four distinct cooling metrics are defined, includingthe following.

1) Tave: The temperature averaged over the entire IGBTchip surface. This metric can be used to characterizethe global cooling capability of hybrid cooling solutiongiven by

Tave = T1 + T2 + · · · + TN

N(4)


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(d)

Fig. 6. Temperature profile along the diagonal position of IGBT chip when the bulk TEC is embedded in the copper layer of the DBC substrate. (a) 6 × 6TE array. (b) 10 × 10 TE array. (c) 13 × 13 TE array. (d) 16 × 16 TE array. The working fluid temperature is 30 °C, the IGBT heat flux is 100 W/cm2,and the effective heat transfer coefficient of the cold plate is 10 000 W/m2-K.

where T1, T2, . . . , TN is the temperature on each nodeof the IGBT surface and N is the total number of nodeson the IGBT surface.

2) T ∗ave: The ratio of the IGBT temperature rise relative

to the working fluid temperature (with solid and liquidhybrid cooling) to that if there is no TEC in thepackage (liquid cooling only). This metric can be used tocharacterize the global cooling effectiveness contributedby the TEC as follows:

T ∗ave = (Tave − Tfluid)with TEC

(Tave − Tfluid)without TEC(5)

where Tfluid is the working fluid temperature. If�Tave∗ = 1, the embedded TEC has no impact on aver-age IGBT temperature. For �Tave∗ < 1, the embeddedTEC can reduce the IGBT average temperature, but if�Tave∗ > 1, the embedded TEC will increase the IGBTaverage temperature.

3) �Tmax: The maximum temperature variation over theentire IGBT surface. This metric can be used to char-acterize the isothermalization, or temperature nonunifor-mity, of IGBT chip achieved by TEC cooling

�Tmax = Tmax − Tmin (6)

where Tmax and Tmin is the maximum and minimumtemperature on the IGBT surface, respectively.

4) �Tmax∗: The ratio of the maximum temperature varia-tion (with hybrid solid and liquid cooling) to that if thereis no TEC in the package (liquid cooling only). Thismetric quantifies the isothermalization effectiveness ofthe TEC, defined as

�∗T = �T ∗with TEC

�T ∗without TEC

= (Tmax − Tmin)with TEC

(Tmax − Tmin)without TEC.

(7)When �Tmax∗ = 1, the embedded TEC has no effect on

isothermalization of the IGBT. If �Tmax∗ > 1, the embeddedTEC will increase the temperature nonuniformity of the IGBT.For �Tmax∗ < 1, the embedded TEC can reduce the parabolictemperature distribution on the IGBT, but for �Tmax∗ = 0, theembedded TEC can make a completely uniform temperaturedistribution on the IGBT surface.

B. Bulk TEC Embedded in DBC Substrate

The initial attempt is to integrate a small thin-film TEC,which has a 6 × 6 TE element array and a footprint areaof 3.8 × 3.8 mm2, into the DBC substrate, and then solder


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Fig. 7. Temperature profile along the diagonal position of IGBT chip cooledby a 16 × 16 TE-array superlattice TEC embedded in the copper layer of theDBC substrate. The working fluid temperature is 30 °C, the IGBT heat fluxis 100 W/cm2, and the effective heat transfer coefficient of the cold plate is10 000 W/m2-K.

TABLE II

TEMPERATURE REDUCTION AND ISOTHERMALIZATION OF IGBT CHIP

USING A 16 × 16 TE-ARRAY SUPERLATTICE TEC EMBEDDED IN THE

DBC SUBSTRATE. THE WORKING FLUID TEMPERATURE IS 30 °C, THE

IGBT HEAT FLUX IS 100 W/cm2, AND THE EFFECTIVE HEAT TRANSFER

COEFFICIENT OF THE COLD PLATE IS 10 000 W/m2-K

Current (A) 0 4 5 5.5 6 7 8 No TEC

Tave (°C) 80.5 56.2 51.3 49.2 47.5 44.1 41 53.4

Tave* 2.2 1.1 0.9 0.8 0.7 0.6 0.5 N/A

�Tmax (°C) 24.3 5.7 1.7 1.1 1.8 4.6 7.6 7.0

�Tmax* 3.47 0.81 0.24 0.16 0.26 0.66 1.09 N/A

it directly on the backside of the IGBT chip [see Fig. 3(a)].Although silicon-based IGBT chip [Fig. 6(a)], with a thermalconductivity of 120 W/m-K, has a very good heat-spreadingability, it cannot fully spread the TE cooling power over theentire chip. Thus, TE cooling is still highly localized at thechip just below the TEC, and an “M” shape temperatureprofile is observed on the active surface of the chip. Two high-temperature pumps shown on the temperature profile is causedby the backflow of the TE heat to the IGBT chip and increasedwith the applied current on the TEC. This observation confirmsour previous conclusion that thin-film TEC is a very promisingcooling solution for thermal management of localized highheat flux hot spot and is capable of removing high-temperaturegradient peak. However, it seems a 6 × 6 TE array TEC isnot an applicable solution to isothermalization of the entireIGBT chip. Fig. 6(b) shows that when a thin-film TEC whichhas a 10 × 10 TE array and a footprint area of 6.2 ×6.2 mm2 is used, a partial isothermalization is achieved atthe applied current of 8 A. It is found that there is <0.5 °Ctemperature variation on the IGBT zone located within a radiusof 8 mm. When the TE array increases to 13 × 13 and16 × 16, IGBT isothermalization can be improved but at alarger current as shown in Fig. 6(c) and (d). A more detailed

TABLE III



COLD PLATE BASE. THE WORKING FLUID TEMPERATURE IS 30 °C, THE

IGBT HEAT FLUX IS 100 W/cm2, AND THE COLD PLATE HEAT

TRANSFER COEFFICIENT IS 10 000 W/m2-K

Current (A) 0 4 5 6 6.5 7 8 No TEC

Tave (°C) 59.1 51.8 50.5 49.4 48.9 48.4 47.7 53.4

Tave* 1.2 0.9 0.9 0.8 0.8 0.8 0.8 N/A

�Tmax (°C) 13.5 5.2 3.4 1.6 1 0.7 1.9 7.0

�Tmax∗ 1.93 0.74 0.49 0.23 0.14 0.10 0.27 N/A

analysis shows that the 13 × 13 TE-array TEC can remove57% of the temperature nonuniformity (�Tmax∗ = 0.43) atthe applied current of 10 A but cannot reduce the averageIGBT temperature (Tave∗ = 1). However, the thin-film TECwith a 16 × 16 TE array is able to not only remove 77% oftemperature nonuniformity (�Tmax∗ = 0.23), but also reducethe IGBT average temperature by 2 °C at the applied currentof 10 A.

C. Superlattice TEC Embedded in DBC Substrate

Nanostructured Bi2Te3 superlattice TEC has a very highSeebeck coefficient of 301 μV/K in comparison with200 μV/K for bulk TEC but has the similar thermal con-ductivity and electrical resistivity. Therefore, it is expectedthat thin-film superlattice TEC will significantly improve thecooling performance and isothermalization of IGBT chip.Fig. 7 shows the temperature profile on the IGBT chip whena 16 × 16 TE-array TEC is embedded in the DBC substrateand solder bonded onto the IGBT chip. Table II shows thedetailed thermal performance for this cooling solution andindicates that the superlattice TEC, at the optimized currentof 5.5 A, can reduce the maximum temperature variation by84% (�Tmax∗ = 0.16), with the temperature nonuniformitydecreasing from 7.0 °C to 1.1 °C. At the same current, thesuperlattice TEC can reduce the average IGBT temperaturefrom 53.4 °C to 49.2 °C, which demonstrates that thin-filmsuperlattice TEC can be used for both temperature reductionand isothermalization of IGBT chip. It should be noted that thecurrent optimized for IGBT isothermalization is not the sameas that for minimization of the IGBT average temperature.Table III shows that the average IGBT temperature is reducedif the applied current increases and at the applied current of8 A, thus, more than half of the temperature rise of the IGBTcan be removed.

D. Superlattice TEC Embedded in Cold Plate

With a concern that thin-film TEC, when directly solderedonto the backside of the chip, might mechanically and elec-trically interact with the electric circuitry of IGBT chip, anew configuration with which a thin-film TEC is embeddedinto the cold plate base so that the IGBT chip is completelyinsulated with the powered TEC is examined. The proposedcooling structure is shown in Fig. 3(b), in which a TEC is


TEC (I=8A)

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Fig. 8. Temperature profile along the diagonal position of IGBT chip cooledby a 16 × 16 TE-array superlattice TEC embedded in the cold plate base. Theworking fluid temperature is 30 °C, the IGBT heat flux is 100 W/cm2, andthe cold plate heat transfer coefficient of the cold plate is 10 000 W/m2-K.

(a) (b)

(c) (d)

Fig. 9. Schematic of the trench structure in the DBC. (a) No trench.(b) Trench only cut through the top copper layer of the DBC substrate.(c) Trench cut to the middle of the AlN layer of the DBC substrate. (d) Trenchcut to the bottom copper layer of the DBC substrate.

embedded and soldered into the cold plate base and thenthe whole cooling package, including the cold plate and theembedded TEC, is solder bonded onto the DBC substrate. Thetemperature profile of the IGBT surface with various currentapplied to the 16 × 16 TE-array superlattice TEC is depictedin Fig. 8 and the detailed cooling parameters are given inTable III. These results show that at the applied current of 7 A,the superlattice TEC can reduce the maximum temperaturevariation to 0.7 °C, which corresponds to a removal of 90%temperature nonuniformity on the IGBT surface. In addition,at the same current, the TEC can reduce the average IGBTtemperature by 6 °C, which corresponds to a removal of 20%temperature rise on the IGBT.

E. Superlattice TEC on Trench-Enhanced DBC Substrate

When a thin-film TEC is embedded in the cold plate baseand separating the IGBT chip with the DBC substrate, someof the TE cooling power is lost through lateral heat flow alongthe DBC substrate because of the heat-spreading effect of theDBC substrate. Therefore, the TEC will cool not only theIGBT, but also the entire DBC substrate degrading the cooling

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TEC (I=6A)

TEC (I=5A)

TEC (I=4A)

No TEC

Tem

pera

ture

(o C

)

Diagonal Position on IGBT (mm)

Fig. 10. Temperature profile along the diagonal position of IGBT chip cooledby a 16 × 16-array superlattice TEC embedded in the cold plate base andenhanced with a trench in the DBC substrate. The working fluid temperatureis 30 °C, the IGBT heat flux is 100 W/cm2, and the heat transfer coefficientof the cold plate is 10 000 W/m2-K.

TABLE IV


USING A 16 ×16-ARRAY SUPERLATTICE TEC EMBEDDED IN THE COLD

PLATE BASE AND ENHANCED WITH A TRENCH IN THE DBC SUBSTRATE.

THE WORKING FLUID TEMPERATURE IS 30 °C, THE IGBT HEAT FLUX IS

100 W/cm2, AND THE COLD PLATE HEAT TRANSFER COEFFICIENT IS

10 000 W/m2-K

Current (A) 0 4 5 6 6.5 7 No TEC

Tave (°C) 63.8 52.2 49.9 48.1 47.2 46.4 53.4

Tave* 1.4 0.9 0.9 0.8 0.7 0.7 N/A

�Tmax (°C) 14.9 5.2 3 1.1 0.4 0.8 7.0

�Tmax* 2.13 0.74 0.43 0.16 0.06 0.11 N/A

performance on the IGBT. We propose a trench structure thatcan be fabricated in the DBC substrate to partially eliminatethe heat-spreading effect, so that the TE cooling power can bedirected right onto the IGBT. However, the trench structureis helpful to concentrate the TE cooling power right onto theIGBT chip and enhance the IGBT cooling performance. Onthe other hand, it restricts the heat-spreading effect of theDBC, and thus makes the heat dissipated from IGBT moredifficult to diffuse to the cold plate through the DBC substrate.Fig. 9 shows the schematic of several trench structure designsin the DBC substrate, which illustrates that several differentimplementations are possible, including cutting the trench onlythrough the top copper layer of the DBC [Fig. 11(b)], to themiddle of the AlN layer of the DBC [Fig. 11(c)], or to thebottom copper layer of DBC [Fig. 11(d)].

The etched trench, about 200 μm in depth and cut throughthe bottom copper layer in the DBC substrate as shown inFig. 9(d), is examined in this paper. Fig. 10 and Table IV showthe temperature profiles and cooling performances with variouscurrents applied on a 16 × 16 TE-array superlattice TEC.


Fig. 11. Temperature contour of IGBT chip. (a) Without embedded TECcooling. (b) With 16 × 16 TE-array superlattice TEC embedded in the coldplate base and enhanced with a trench in the DBC substrate. The workingfluid temperature is 30 °C, and the heat transfer coefficient of the cold plateis 10 000 W/m2-K.

0 2 4 6 8 10 12 1438

40

42

44

46

48

50

52

54

56

58

No TEC Cooling h = 10,000 W/m2-K

h = 20,000 W/m2-K h = 30,000 W/m2-K

Tem

pera

ture

(o C

)


TEC Cooling at I = 6.5A

h = 10,000 W/m2-K

h = 20,000 W/m2-K

h = 30,000 W/m2-K

Fig. 12. Comparison of IGBT temperature profile at various effective heattransfer coefficient. A 16 × 16 TE-array superlattice TEC embedded in thecold plate base and enhanced with a trench in the DBC substrate. The workingfluid temperature is 30 °C, the IGBT heat flux is 100 W/cm2, and the heattransfer coefficient of the cold plate varies from 10 000–30 000 W/m2-K.

It is found that at the optimized current of 6.5 A, thesuperlattice TEC can remove 96% of the IGBT temperaturenonuniformity and reduce the IGBT average temperature by6.2 °C. In comparison with nontrench cooling configuration,the trench-enhanced cooling configuration can achieve betterisothermalization (�Tmax∗ = 0.06 for trench configurationversus �Tmax∗ = 0.10 for nontrench configuration) and bettertemperature reduction performance (Tave∗ = 0.7 for trenchconfiguration versus �Tave∗ = 0.8 for nontrench configura-tion), but at lower current (I = 6.5 A for trench configurationversus I = 7 A for nontrench configuration).

Fig. 11 compares the temperature contour of the IGBTpackages with hybrid solid and liquid cooling [Fig. 11(a)] andwith liquid cooling only [Fig. 11(b)]. Here only the half modelis shown so that the temperature profile inside the chip packagecan be illustrated. It can be seen that if the thin-film TEC isintegrated into the IGBT package and powered on at 6.5 A,the cold plate base temperature will increase from 30 °C to35 °C, but the IGBT peak temperature is reduced by 8.7 °C,from 56.1 °C to 47.4 °C, and the temperature nonuniformityreduces from 7.0 °C to 0.4 °C.

TABLE V


USING A 16 ×16 TE-ARRAY SUPERLATTICE TEC EMBEDDED IN THE

COLD PLATE BASE AND ENHANCED WITH A TRENCH IN THE DBC

SUBSTRATE. THE WORKING FLUID TEMPERATURE IS 30 °C, THE IGBT

HEAT FLUX IS 100 W/cm2, AND THE TEC IS OPERATED AT THE

OPTIMIZED CURRENT OF 6.5 A

Metrics Heat Transfer Coefficient (W/m2-K)

10 000 20 000 30 000

Tave (°C) 47.3 44.3 43.3

Tave* 0.7 0.7 0.7

�Tmax (°C) 0.4 0.4 0.4

�Tmax∗ 0.06 0.06 0.06

F. Effect of Cold Plate Cooling Capability

It has been demonstrated that TE cooling performance intraditional air-cooled TE systems can be enhanced by system-level optimization. For example, using a high-performanceheat sink and fan system, the more aggressive external coolingcan reduce the hot junction temperature of the TEC andless heat will be conducted back to the TEC cold junction.In this paper, the impact of liquid-cooling capacity of thecold plate is examined. The effective heat transfer coefficientvarying from 10 000–30 000 W/m2-K is applied to the coldplate base and its effect on isothermalization and temperaturereduction is investigated using the configuration shown inFig. 3(c), where the superlattice TEC is embedded in thecold plate base and enhanced with a trench in the DBCsubstrate. The results shown in Fig. 12 and Table V sug-gest that at the optimized current of 6.5 A, an increaseof the heat transfer coefficient from 10 000–30 000 W/m2-Kcan only reduce the IGBT average temperature (Tave) by4 °C, but has no effect on cooling effectiveness (Tave∗). Theresults also show that increasing heat transfer coefficient hasno effect on both maximum temperature variation (�Tmax)and isothermalization effectiveness (�Tmax∗) on IGBT chip,which implies that heat conduction thermal resistance is thedominant factor in the IGBT electronic package. Therefore,an improvement of cold plate cooling capability has littleadvantage in improving IGBT cooling.

G. Effect of Working Fluid Temperature

One of the goals of thermal management of power elec-tronics for hybrid electronic vehicles is to use glycol–watermixture as the working fluid at 105 °C in the near term[26]. Therefore, it is interesting to study the temperaturereduction and isothermalization performance of the IGBTunder high-temperature fluid systems. We study the cold platewith the working fluid temperature held constant at 105 °C,representing a 50/50 glycol–water mixture, and use the optimalcooling configuration shown in Fig. 3(c) as the testing vehicle.Fig. 13 and Table VI show the thermal performance of thesuperlattice TEC for cooling IGBT chip. The results indicatethat operation of the cold plate at 105 °C fluid temperaturewill offer better temperature reduction (8.1 °C for 105 °C fluid


0 2 4 6 8 10 12 14114

116

118

120

122

124

126

128

130

132

I=5.5A

I=5.0A

I=4.5A

Tem

pera

ture

(o C

)


No TEC

I=4.0A

I=6.5A

I=6.0A

125oC

Fig. 13. Temperature profile along the diagonal position of IGBT chip whena 16×16-array superlattice TEC is embedded in the cold plate base andenhanced with a trench in the DBC substrate. The working fluid temperatureis 105 °C, the IGBT heat flux is 100 W/cm2, and the heat transfer coefficientof the cold plate is 10 000 W/m2-K.

TABLE VI


USING A 16 × 16-ARRAY SUPERLATTICE TEC EMBEDDED IN

MICROCHANNEL AND ENHANCED WITH TRENCH IN DBC. THE

WORKING FLUID TEMPERATURE IS 105 °C, THE IGBT HEAT FLUX IS

100 W/cm2, AND THE HEAT TRANSFER COEFFICIENT OF THE COLD

PLATE IS 10 000 W/m2-K

Current (A) 0 4 4.5 5 5.5 6 No TEC

Tave (°C) 138.8 124.4 123 121.6 120.3 119 128.4

Tave* 1.1 1.0 0.9 0.9 0.9 0.9 N/A

�Tmax (°C) 14.9 5.2 3 1.1 0.4 0.8 7

�Tmax∗ 2.13 0.74 0.43 0.16 0.06 0.11 N/A

temperature versus 6.2 °C for 30 °C fluid temperature), but hasthe same maximum temperature variation (�Tmax = 0.4) andisothermalization effectiveness as that operated at 30 °C fluidtemperature (�Tmax∗ = 0.06). However, the TEC needs lesscurrent to achieve the optimal operation condition at 105 °Cfluid temperature compared with 30 °C fluid temperature(5.5 A for 105 °C fluid temperature versus 6.5 A for 30 °Cfluid temperature). This is because the TE cooling power islinearly preoperational to the temperature at the cold junction(Tc), and higher TEC operating temperature due to higher fluidtemperature results in larger TE cooling power and thus bettercooling performance. The results show that the TE coolingpower, when the TEC is operated at 105 °C fluid temperature,is around 20% higher than that at 30 °C fluid temperature.

Fig. 13 also suggests that if there is no TEC cooling inthe system, the peak chip temperature will reach 131 °Cand exceeds the maximum allowable temperature of silicon-based IGBT chip by 6 °C. However, if the superlattice TECis integrated in the cold plate and activated at the currentlarger than 4.5 A, the maximum IGBT temperature can be

0 2 4 6 8 10 12 1464

66

68

70

72

74

76

78

80

82

84

Tem

pera

ture

(o C

)


No TEC TEC (I=8A) TEC (I=10A) TEC (I=12A) TEC (I=14A) TEC (I=16A) TEC (I=18A) TEC (I=20A)

Fig. 14. Temperature profile along diagonal position of IGBT chip cooledby a 16 × 16 TE-array superlattice TEC embedded in the cold plate base andenhanced with a trench in the DBC substrate. The working fluid temperatureis 30 °C, the IGBT heat flux is 200 W/cm2, and the heat transfer coefficientof the cold plate is 10 000 W/m2-K.

TABLE VII



COLD PLATE BASE AND ENHANCED WITH A TRENCH IN THE DBC

SUBSTRATE. THE WORKING FLUID TEMPERATURE IS 30 °C AND IGBT

HEAT FLUX IS 200 W/cm2, AND THE HEAT TRANSFER COEFFICIENT OF

THE COLD PLATE IS 10 000 W/m2-K

Current (A) 0 8 10 12 14 16 18 No TEC

Tave (°C) 97.6 76.2 73.5 71.9 70.6 70.8 71.2 76.5

Tave∗ 1.5 1.0 0.9 0.9 0.9 0.9 0.9 N/A

�Tmax (°C) 29.8 10.8 7.2 4.2 1.3 1.8 3.7 14.1

�Tmax∗ 2.13 0.77 0.51 0.30 0.09 0.13 0.26 N/A

controlled below 125 °C, showing the TEC is very helpfulto enhance the existing cooling scenario of power electronicssystems to control the IGBT chip temperature below itsthermal specification limit.

H. High-Flux IGBT Chip

In addition to cooling 100 W/cm2 IGBT chip, we alsoexplore this hybrid cooling system for higher power electronicssystems with an IGBT heat flux of 200 W/cm2. Fig. 14shows the temperature profile along the diagonal position of a200 W/cm2 IGBT chip cooled by a 16×16 TE-array superlat-tice TEC embedded in the cold plate and enhanced with trenchin the DBC substrate. The working fluid temperature is fixedat 30 °C and the heat transfer coefficient of the cold plate isassumed to be 10 000 W/m2-K. Table VII shows that at theoptimized current of 14 A, the average IGBT temperature isreduced by 6 °C and the maximum temperature variation isreduced by 12.7 °C, which corresponds to a removal of 91%temperature nonuniformity for a 200 W/cm2 IGBT chip.


V. CONCLUSION

A hybrid solid- and liquid-cooling solution, which com-bines cold plate liquid cooling and TE solid-state cooling,was proposed for thermal management of IGBT chip witha major attention focused on isothermalization of IGBTchip. The innovation of this cooling concept is that thecold plate was used for global cooling of the entire IGBTmodule while the embedded thin-film TEC was employedfor isothermalization of the chip. A package-level 3-D ther-mal model was developed to explore the potential appli-cation of this cooling concept and the effects of appliedcurrent, TEC sizes, TE materials, cooling system architec-tures, working fluid temperatures, cold plate cooling capacity,and IGBT chip heat flux were investigated and discussedin details.

Three different cooling architectures for IGBT isothermal-ization were proposed and examined. It was found that a trenchin the DBC substrate can avoid heat-spreading effect and thusconcentrated the TE cooling power mostly onto the IGBTchip, thereby providing the best isothermalization and tem-perature reduction performance among all the configurations.The results demonstrated that thin-film superlattice TEC cansuccessfully isothermalize IGBT chip and eliminated 94% ofthe temperature nonuniformity for the 100 W/cm2 IGBT chipand 91% for 200 W/cm2 IGBT chip. The impact of cold platecooling capability on IGBT isothermalization was investigatedby varying the effective heat transfer coefficient from 10 000–30 000 W/m2-K. It was found that an increase in cold platecooling capability only slightly reduced the IGBT averagetemperature but did not change the nonuniform temperaturedistribution of the IGBT, implying that heat conduction wasthe dominant factor in the IGBT packaging and an improve-ment of external convective cooling capability had little impacton isothermalization of the chip. Furthermore, it was observedthat higher working fluid temperature led to an elevated IGBTtemperature, which was advantageously translated to largerTE cooling power, so that the optimal operating condition forisothermalization could be achieved at lower applied current.The results revealed that the hybrid solid and liquid cooling isa promising thermal management solution for both isother-malization and temperature reduction of high-power IGBTchip.

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[3] A. G. Pautsch, A. Gowda, L. Stevanovic, and R. Beaupre, “Doubled-sided cold plate cooling of a power electronics modules using poweroverlay,” in Proc. Amer. Soc. Mechan. Eng. InterPACK Conf., Jul. 2009,pp. 89190–89198.

[4] L. Meysenc, M. Jylhakallio, and P. Barbosa, “Power electronics coolingeffectiveness versus thermal inertia,” IEEE Trans. Power Electron., vol.20, no. 3, pp. 687–692, May 2005.

[5] A. Bhunia, Q. Cai, and C. L. Chen, “Liquid impingement and phasechange for high power density electronic cooling,” in Proc. 41st Amer.Inst. Aeronaut. Astronaut. Aerosp. Sci. Meeting Exhibit. Conf., Jan. 2003,pp. 1–8.

[6] A. Bhunia, Q. Cai, and C. L. Chen, “Jet impingement cooling ofan inverter module in the harsh environment of a hybrid vehicle,” inProc. Amer. Soc. Mechan. Eng. Summer Heat Transfer Conf., Jul. 2005,pp. 72574–72579.

[7] J. Lee and I. Mudawar, “Two-phase flow in high-heat-flux micro-channelheat sink for refrigeration cooling applications: Part I—pressure dropcharacteristics,” Int. J. Heat Mass Transfer, vol. 48, no. 5 pp. 928–940,2005.

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[13] A. Bhunia and C. L. Chen, “On the scalability of liquid microjet arrayimpingement cooling for large area systems,” J. Heat Transfer, vol. 133,no. 6, pp. 064501-1–064501-7, 2011.

[14] V. Semenyuk, “Thermoelectric cooling of electro-optic components,” inThermoelectrics Handbook: Macro to Nano, D. M. Rowe, Ed. BocaRaton, FL: CRC Press, 2006, ch. 58.

[15] V. Semenyuk, “Miniature thermoelectric modules with increasedcooling power,” in Proc. 25th Int. Conf. Thermoelectr., 2006,pp. 322–326.

[16] A. Bar-Cohen and P. Wang, “On-chip thermal management and hot spotremediation,” in Nano-Bio-Electronic, Photonic and MEMS Packaging,C. P. Wong, K. Moon, and Y. Li, Eds. New York: Springer-Verlag, 2010,ch. 12.

[17] A. Shakouri, “Nanoscale thermal transport and micro refrirgeratorson a chip,” Proc. IEEE, vol. 94, no. 8, pp. 1613–1638, Aug.2006.

[18] P. Wang, A. Bar-Cohen, and B. Yang, “Enhanced thermoelectriccooler for on-chip hot spot cooling,” in Proc. Pacif. Rim/Amer. Soc.Mech. Eng. Int. Electron. Packag. Tech. Conf. Exhibit., Jul. 2007,pp. 33798– 33805.

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Peng Wang (SM’10) received the Ph.D. degree in mechanical engineeringfrom the University of Maryland, College Park, in 2007, with a major focuson on-chip hot spot cooling for microprocessors.

He is currently a Research Scientist with the University of Maryland atCollege Park, College Park leading research effects in thermal management ofelectronics and developing innovative mini/micro-scaled cooling technologiesfor electronics and automotive industries in the Thermal Packaging of Elec-tronic and Photonic Systems Laboratory. Previously, he worked as a ThermalPackaging Consultant in Silicon Valley to develop thermal management strate-gies and characterization methodologies for electronics and telecommunica-tions companies, such as Dell, nVidia, Santa Clara, CA, Brocade, San Jose,CA, Cisco Systems, San Jose, CA, Alcatel-Lucent, New Providence, NJ, andJuniper Networks, Sunnyvale, CA. Since 2000, his work has been concentratedin research and development of advanced cooling technologies for chip-level,package-level, and system-level thermal management of electronics. He hasauthored or co-authored one book, one book chapter, and more than 40journal and conference papers. His current research interests include air-cooling, solid-state thermoelectric cooling, single-phase liquid cooling, two-phase evaporative heat sink, two-phase thermosyphon, and micro heat pipefor high power and high heat flux electronics.

Patrick McCluskey received the Ph.D. degree in materials science andengineering from Lehigh University, Bethlehem, PA.

He is currently an Associate Professor of mechanical engineering with theUniversity of Maryland, College Park, where he is engaged in research onthermal management, reliability, and packaging of electronic microsystems foruse in extreme temperature environments and high-power applications with theCenter for Advanced Life Cycle Engineering. He has authored or co-authoredmore than 100 refereed research papers and has edited three books.

Dr. McCluskey was the Technical Chairman for multiple internationalconferences and workshops and is an Associate Editor of the IEEETRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING

TECHNOLOGY. He is a fellow of the International Microelectronics andPackaging Society and is a member of the ASME, the IEEE, and the SAE.

Avram Bar-Cohen is currently with the Defense Advanced Research ProjectsAgency (DARPA), Arlington, VA. He was with Ben Gurion University, BeerSheva, Israel, in 1972. From 1998 to 2001, he was with the University ofMinnesota Center, where he was involved in the development of technologicalleadership and was the Sweatt Chair in Technological Leadership. From 2001to 2010, he was the Chair of Mechanical Engineering with the University ofMaryland, College Park, where he was a Distinguished University Professorwith the Department of Mechanical Engineering and is currently on leaveto the DARPA. He has guided 65 Ph.D. and Masters degree students. Hehas authored or co-authored about 400 journal papers, refereed proceedingspapers, and chapters in books. He has co-authored Design and Analysis ofHeat Sinks (Wiley, 1995) and Thermal Analysis and Control of ElectronicEquipment (McGraw-Hill, 1983), and has co-edited 16 books. He holds eightU.S. and three Japanese patents. He has delivered 65 keynotes, and plenaryand invited lectures at major technical conferences and institutions. His currentresearch interests include high-reliability consumer electronics, computingplatforms, microwave communication and radar systems, and air-cooled cardcages and heat sinks, along with direct liquid cooling of microprocessors andRF components

Dr. Bar-Cohen was a recipient of the Edwin F. Church Medal in 1994,the Electronic and Electrical Packaging Division’s Outstanding ContributionAward in 1994, the THERMI Award from the IEEE/Semi-Therm Conferencein 1997, the ASME/IEEE ITHERM Achievement Award in 1998, the ASME’sHeat Transfer Memorial Award in 1999, the Curriculum Innovation Award in1999, the Worcester Reed Warner Medal in 2000, the IEEE CPMT Society’sOutstanding Sustained Technical Contributions Award in 2002, the InterPackAchievement Award in 2007, the Luikov Medal from the International Centerfor Heat and Mass Transfer in Turkey in 2008. He was the Founding Chairof the IEEE Intersociety Conference on Thermal Management in ElectronicEquipment (ITHERM) in 1988. He is an Honorary Member of the ASME andis the President of the Assembly for International Heat Transfer Conferences.

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