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Hybrid CMOS + Spintronics for the Next Big Leap in Energy Efficient Computing
Vivek DeIntel Fellow & Director of Circuit Technology Research
Intel Labs
Workshop on the Future of Spintronics
June 5, 2016
1
The Internet of Everything (IoE)
2
Paradigm shifts across architecture, circuits, design & technology
Universal-Scalable-Efficient Cognitive Computing
3
Exploit Moore’s Law integration, spike timing, sparsity & resiliency
Voltage Scaling & Variation Tolerance
4
Variation-tolerant NTV design essential for energy efficiency
Near Threshold Voltage (NTV) Multi-Voltage Design NTV & Variability
Within-Die & Die-to-Die Variations
Fine-Grain Power Management
5
Autonomous & distributed fine-grain power management is essential
Autonomous Power Control
Fine-Grain & Scalable Integrated Voltage Regulators
Distributed Memory + Compute
6
Integrated high-density & energy-efficient memory is critical
Conventional
Distributed
Merolla et al., 2014 Science
Embedded SRAM Array
Transposable SRAM Cell
Seo et al., 2011 CICC
3D Integration: SRAM
3D Integration: DRAM
Emerging Technologies: Memory
7
Integrated dense & non-volatile memory for synaptic weight storage
Integrated ReRAM
Cruz-Albrecht et al., 2013 Nanotechnology
Embedded STT-RAM
Yuasa et al., 2013 IEDM
Emerging Technologies: Neurosynapse
8
TFET, spintronics & nano-oscillators for beyond-CMOS neurosynapse
Tunnel FET (TFET) Spintronics Nano-oscillators
Verhulst et al., 2014 IEDM
Neel wall based synapse
STDP
Spin-orbit torque domain wall motion
Kaushik Roy, Purdue, 2015
Spin Torque Oscillator (STO)
Pattern matching
D. Nikonov et al., 2015 JXCDC
Beyond CMOS Technology Outlook
9
Big leaps in energy efficiency trigger technology transitions!
Technology Outlook
D. Nikonov & I. Young, 2015 JXCDC
Moore’s Law: Economics AND Power
W. Holt, 2016 ISSCC
Summary
10
Variation-Tolerant NTV DesignAutonomous Fine-Grain Power Management
Emerging Technology
Learning, Resiliency & Stochasticity
Architecture
Circuits & Design